Class / Patent application number | Description | Number of patent applications / Date published |
365230050 | Multiple port access | 30 |
20080198681 | MULTIPLE PORT MEMORY WITH PRIORITIZED WORD LINE DRIVER AND METHOD THEREOF - A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port. | 08-21-2008 |
20080212392 | MULTIPLE PORT MUGFET SRAM - A circuit includes a multi gate field effect transistor based static random access memory device having a cross coupled inverter cell. A first set of multi gate field effect transistor access devices are coupled to the memory device to provide a first port. A second set of multi gate field effect transistor access devices are coupled to the memory device to provide a second port. Further ports may be provided in further embodiments. | 09-04-2008 |
20080225623 | MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS - A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode. | 09-18-2008 |
20080259712 | FAST READ PORT FOR REGISTER FILE - Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response. | 10-23-2008 |
20080285372 | MULTI- PORT MEMORY DEVICE FOR BUFFERING BETWEEN HOSTS AND NON-VOLATILE MEMORY DEVICES - A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode. | 11-20-2008 |
20080291767 | MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL - A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer. | 11-27-2008 |
20080291768 | BITCELL WITH VARIABLE-CONDUCTANCE TRANSFER GATE AND METHOD THEREOF - A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first transfer gate is configurable to at least four conductance states based on a state of the first word line and a state of the second word line. The memory device further comprises control logic to configure, for an access to the bit cell, the state of the first word line and the state of the second word line based on an access type of the access. | 11-27-2008 |
20080291769 | Multiport semiconductor memory device - In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD-Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented. | 11-27-2008 |
20080316851 | Semiconductor memory device - Disclosed is a semiconductor memory device including a plurality of memory cells, each of which is connected to word lines of first and second ports and to bit lines of the first and second ports, and first and second inter-port switches for electrically connecting first bit lines of the first port and second bit lines of the second port when row addresses of the first and second ports match each other. | 12-25-2008 |
20090003119 | PSEUDO DUAL-PORT MEMORY - A pseudo dual-port memory device is disclosed. One embodiment provides an internal data RAM for a microprocessor, and a method for operating a memory device. In one embodiment, a memory device for a microprocessor or microcontroller comprises: a first part with memory cells that are single-port memory cells; and a second part with memory cells that are dual-port memory cells. In another embodiment, a method for operating a memory device is provided, the memory device including at least one single-port memory and at least one dual-port memory, the method including: accessing the single-port memory of the memory device when a non-conflicting access is to be carried out at the memory device; and accessing the dual-port memory of the memory device when a conflicting access is to be carried out at the memory device. | 01-01-2009 |
20090059711 | Routing access with minimized bus area in multi-port memory device - A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area. | 03-05-2009 |
20090103390 | Three Dimensional Twisted Bitline Architecture for Multi-port Memory - Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise. | 04-23-2009 |
20090129194 | Access collision within a multiport memory - A multiport memory | 05-21-2009 |
20090154283 | System for Blocking Multiple Memory Read Port Activation - A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch. | 06-18-2009 |
20100124141 | SEMICONDUCTOR MEMORY DEVICE OF DUAL-PORT TYPE - To provide a plurality of DRAM cells, a plurality of sense amplifiers connected to corresponding bit line pairs, a first column switch and a second column switch assigned to each of the sense amplifiers, data lines connected via the column switches to the sense amplifiers, a first port PORT | 05-20-2010 |
20100157715 | SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION - A semiconductor device that can implement a method comprising selecting a group of rows of auxiliary cells forming part of an auxiliary memory unit, the auxiliary cells being arranged into rows and columns; driving a plurality of bitlines each connected to a respective column of the auxiliary cells, so as to set each of the auxiliary cells to a first logic state; writing input data to selected ones of a plurality of main cells, wherein each of the auxiliary cells corresponds to a respective set of the main cells; selecting a particular row of auxiliary cells that includes at least one auxiliary cell whose corresponding main cells are among the selected cells; and driving the bitlines so as to set the at least one auxiliary cell to a second logic state different from the first logic state. | 06-24-2010 |
20100177585 | Memory subsystem - Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device. In alternative embodiments of the present invention, the memory controller and memory are together integrated within a computational engine or another electronic device. Alternative embodiments of the present invention include a multi-access memory that interfaces to a simpler memory controller for connection to, or integration within, a computational engine or other electronic device. | 07-15-2010 |
20100232249 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 09-16-2010 |
20100254210 | Multiple-Port SRAM Device - A static random access memory (SRAM) cell having a dedicated read port separated from a write port comprises a first and a second bit-line placed in parallel forming a complimentary bit-line pair for the dedicated read port, a first and second metal line adjacently flanking in both side of and in parallel to the first bit-line, the first and second metal line being formed in the same metal layer as the first bit-line and having a first and second predetermined distance to the first bit-line, respectively, and a third and fourth metal line adjacently flanking in both side of and in parallel to the second bit-line, the third and fourth metal line being formed in the same metal layer as the second bit-line and having a third and fourth predetermined distance to the second bit-line, respectively, wherein the first predetermined distance is equal to the third distance and the second predetermined distance is equal to the fourth distance for keeping the first and second bit-lines having balanced capacitance loading. | 10-07-2010 |
20100271898 | ACCESS TO MULTI-PORT DEVICES - Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided. | 10-28-2010 |
20100329066 | NON-BLOCKING MULTI-PORT MEMORY FORMED FROM SMALLER MULTI-PORT MEMORIES - A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the memories, each of the subset of memories being provided in a corresponding one of the groups, a number of the copies of the data unit being greater than two. Multiplexers may be implemented, each of which being associated with a corresponding one of the groups of the memories. One of the plurality of multiplexers may be configured to selectively supply one of the copies of the data unit from one of the memories. A read port may receive the one of the copies of the data unit from the one of the multiplexers and output the one of the copies of the data unit. | 12-30-2010 |
20110075504 | Dual Beta Ratio SRAM - A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. | 03-31-2011 |
20110255361 | MULTI-PORT MEMORY HAVING A VARIABLE NUMBER OF USED WRITE PORTS - A multi-port memory is operated according to a method. Data is written, in a first mode, to a storage node of a memory cell from a first port through a first conductance. The first mode is characterized by a power supply voltage being applied at a power node at a first level. Data is written, in a second mode, to the storage node of the memory cell simultaneously from the first port through the first conductance and a second port through a second conductance. The second mode is characterized by the power supply voltage being applied at the power node at a second level different from the first level. | 10-20-2011 |
20110261640 | Semiconductor memory device and data processing system including the semiconductor memory device - A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving a read command to the first memory cell array and sequentially a write command to the second cell memory array, a first address generator configured to produce a first internal address for designating the first area of the first memory cell array when receiving the transfer command from the command decoder; and a second address generator configured to produce a second internal address for designating the second area of the second memory cell array when receiving the transfer command from the command decoder. | 10-27-2011 |
20120120752 | Dual-Port Semiconductor Memory and First-In First-Out (FIFO) Memory Having Electrically Floating Body Transistor - Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device. | 05-17-2012 |
20120195151 | Semiconductor Memory Device and Method - In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port. | 08-02-2012 |
20120287743 | CLOCK HANDOFF CIRCUIT AND CLOCK HANDOFF METHOD - A clock handoff circuit outputting data in synchronism with a first clock input thereto as output data in synchronism with a second clock, includes: a dual port RAM capable of performing writing and reading independently of each other; a write address control section controlling write addresses of the dual port RAM in which the input data is written; a blank address detecting section detecting blank addresses among the write addresses in which the input data is not written; and a read address conversion section converting the write addresses of the dual port RAM excluding the blank address into read addresses from which the output data are read out. | 11-15-2012 |
20140146631 | VCCMIN FOR A DUAL PORT SYNCHRONOUS RANDOM ACCESS MEMORY (DPSRAM) CELL UTILIZED AS A SINGLE PORT SYNCHRONOUS RANDOM ACCESS MEMORY (SPSRAM) CELL - One or more techniques for improving Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the DPSRAM cell. For example, the second word line signal is sent in response to a logical low at a first bit line or a logical low at a second bit line. In this way, Vccmin is improved for the DPSRAM cell. | 05-29-2014 |
20140241100 | SYNCHRONOUS MULTIPLE PORT MEMORY WITH ASYNCHRONOUS PORTS - A memory system includes a multi-port memory having a first port and a second port. First registers and second registers provide first and second addresses, respectively, to the first and second ports. An access controller controls the multi-port memory to launch an access for the valid address provided by the first input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the first clock and to launch an access for the valid address provided by the second input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the second clock. | 08-28-2014 |
20140347950 | Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 11-27-2014 |