Class / Patent application number | Description | Number of patent applications / Date published |
365218000 | Erase | 40 |
20080247255 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS OF USING THE SAME - An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source. | 10-09-2008 |
20080285368 | METHOD FOR NROM ARRAY WORD LINE RETRY ERASING AND THRESHOLD VOLTAGE RECOVERING - A method for erasing and recovering a memory array is disclosed. The memory array includes a plurality of sectors of memory cells. After erasing a sector of the memory array, all of the memory cells of the memory array are checked to find programmed memory cells in the other un-erased sectors of the memory array. If a programmed memory cell is found, the programmed memory cell will be programmed and verified until the threshold voltage of the programmed memory cell reaches a program verify voltage. | 11-20-2008 |
20080285369 | BLOCK ERASE FOR VOLATILE MEMORY - A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells. | 11-20-2008 |
20090046530 | RESETTABLE MEMORY APPARATUSES AND DESIGN - Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of memory units; and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic is to write reset information into a portion of the memory units when one of the resettable memory cells has a reset value and one of the memory units is written into. Alternatively, a resettable memory may include: a memory unit; a resettable finite state machine to change state in response to write request to the memory unit; and a selector coupled to the finite state machine and the memory unit to select one from a reset value and an output from the memory unit based on at least a state of the finite state machine. | 02-19-2009 |
20090080277 | MEMORY CELL FUSE CIRCUIT AND CONTROLLING METHOD THEREOF - A controlling method of a memory cell fuse circuit is provided. The memory cell fuse circuit at least includes a reference cell fuse circuit and a plurality of normal cell fuse circuit. The reference cell fuse circuit includes a reference fuse cell and each the normal cell fuse circuit includes a normal fuse cell. The controlling method includes steps of: power on read and sensing digits of the memory cell fuse circuit; detecting if any normal fuse cell is non blank as failed; programming the reference fuse cell if at least one normal fuse cell is failed until all normal fuse cells are blank; programming and reading the normal fuse cell of each the normal cell fuse circuit; and outputting data of each the normal fuse cell. | 03-26-2009 |
20090129190 | DRIVING A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS - A memory matrix ( | 05-21-2009 |
20090168579 | RANDOM ACCESS MEMORY DATA RESETTING METHOD - A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period. | 07-02-2009 |
20090185441 | Integrated Circuit and Method to Operate an Integrated Circuit - Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation. | 07-23-2009 |
20100118634 | Semiconductor apparatuses and methods of operating the same - A method of operating a semiconductor device is provided including applying a constant source voltage to a source line. | 05-13-2010 |
20100135095 | ASSISTANCE IN RESET OF DATA STORAGE ARRAY - A system is capable of assisting in reset of a data storage array including data storage array including one or more data storage array nodes. The system includes a control unit coupled to the data storage array configured to produce a control signal to reset the data storage array, and a reset unit communicatively coupled to the data storage array and the control unit configured to reset the data storage array by charge injection to the one or more data storage array nodes. | 06-03-2010 |
20100157710 | Array Operation Using A Schottky Diode As a Non-Ohmic Isolation Device - A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The NOD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied. | 06-24-2010 |
20100165772 | Self aligned back-gate for floating body cell memory erase - In some embodiments all cells within a word-line of a floating body cell memory are erased. A back-gate of the floating body cell memory is self-aligned with the word line, and the erasing is performed using a back-gate bias. Other embodiments are described and claimed. | 07-01-2010 |
20110026350 | Resettable Memory Apparatuses and Design - In one aspect of the present invention, a memory apparatus comprises a plurality of resettable memory cells, a plurality of memory units, and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic designed to write reset information into a portion of the memory units in response to one of the resettable memory cells having a reset value when one of the memory units is written into. | 02-03-2011 |
20110069571 | Word Line Decoder Circuit Apparatus and Method - One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. | 03-24-2011 |
20110261638 | Method for Storing Data into a Memory - A method for storing data into a memory is provided. In this method, at first, data desired to be written into the memory is provided, wherein the data comprises a plurality of data records. Then, a memory space of the memory for storing the data is provided. Thereafter, a data-writing step is performed to write the data into the memory. In the data-writing step, at first, it is determined that if the values of all the data records of the data are cleared values to provide a first determined result. Then, it is determined that if the data matches an erasing unit of the memory to provide a second determined result. Thereafter, the contents of the memory space are erased, when both the first determined result and the second determined result are yes. | 10-27-2011 |
20110280093 | DATA PROTECTIVE STRUCTURE, ELECTRONIC DEVICE, AND METHOD OF ERASING DATA - The present invention includes: a circuit board which is provided with an electronic circuit part; a first case and a second case ( | 11-17-2011 |
20120269020 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line. | 10-25-2012 |
20120269021 | MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT - A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different. | 10-25-2012 |
20120294104 | NONVOLATILE MEMORY SYSTEMS USING TIME-DEPENDENT READ VOLTAGES AND METHODS OF OPERATING THE SAME - An elapsed time with respect to a programming operation on a memory cell of a nonvolatile memory is determined, a read voltage is adjusted based on the determined elapsed time and a read operation is performed on the memory cell using the adjusted read voltage. Determining the elapsed time may be preceded by performing the programming operation in response to a first access request and determining the elapsed time may include determining the elapsed time in response to a second access request. Memory systems supporting such operations are also described. | 11-22-2012 |
20120320697 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a plurality of memory strings, a plurality of memory blocks, a plurality of source-lines, and a control circuit. Each of the memory strings includes a plurality of stacked memory transistors. Each of the memory blocks includes the memory strings. Each of the source-lines are connected to the respective memory strings. The control circuit is configured to output signals to a switch circuit depending on the types of operations for the memory transistors. The switch circuit is capable of connecting the plurality of source-lines electrically and commonly depending on the signals. | 12-20-2012 |
20120320698 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ERASING DATA THEREOF - A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation. | 12-20-2012 |
20130003480 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core. | 01-03-2013 |
20130016577 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEMAANM NAGADOMI; YasushiAACI Yokohama-shiAACO JPAAGP NAGADOMI; Yasushi Yokohama-shi JP - A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations. | 01-17-2013 |
20130100754 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA THEREOF - A memory string includes a semiconductor layer, a charge accumulation layer, and a conductive layer. The semiconductor layer extends in a direction perpendicular to the semiconductor substrate and functions as a body of a memory cell. The charge accumulation layer may accumulate charges. The conductive layer sandwiches the charge accumulation layer with the semiconductor layer, and functions as a gate of the memory cell. The control circuit performs, before a read operation, a refresh operation of rendering the selected memory cell and a non-selected memory cell conductive to conduct a current from a first end to a second end of the memory string. | 04-25-2013 |
20130107653 | NONVOLATILE MEMORY HAVING STACKED STRUCTURE AND RELATED METHOD OF OPERATION | 05-02-2013 |
20130141998 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages. | 06-06-2013 |
20130148454 | DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. | 06-13-2013 |
20130182520 | MEMORY DEVICE BASED ON CONDUCTANCE SWITCHING IN POLYMER/ELECTROLYTE JUNCTIONS - A non-volatile memory device including at least a first electrode and a second electrode provided on a substrate, the first and second electrodes being separated from each other; an organic semiconductive polymer electrically connecting the first and second electrodes; an electrolyte in contact with the organic semiconductive polymer; and a third electrode that is not in contact with the first electrode, the second electrode, and the organic semiconductive polymer; wherein the organic semiconductive polymer has a first redox state in which it exhibits a first conductivity, and a second redox state in which it exhibits a second conductivity. | 07-18-2013 |
20130182521 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is operated by forming channels in a cell string including a plurality of memory cells and coupled between a bit line and a source line, applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively, and applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells. | 07-18-2013 |
20130223173 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle. | 08-29-2013 |
20130250710 | Non-Volatile Memory Device, Circuit Board, Printing Material Container And Printer - A non-volatile memory device includes first and second memory regions to store data and a memory control unit. Each of the first and second memory regions is configured by a plurality of physical pages. Each of the physical pages is configured by a plurality of regions corresponding to a plurality of logical addresses. The memory control unit performs control of batch erasing and batch writing on every physical page. When a first physical page in the first memory region includes a first region corresponding to a first logical address, which is a target to be written, and when a second physical page in the second memory region includes a second region corresponding to the first logical address, which is a target to be written, the memory control unit selects either the first physical page or the second physical page as a physical page for writing. | 09-26-2013 |
20140050041 | DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY - A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required. | 02-20-2014 |
20140056091 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device, given the case where memory cells have an erase state less than a first reference voltage and a plurality of program states greater than the first reference voltage, includes performing an erase operation so that the memory cells have a soft erase state less than a second reference voltage, and performing a program operation so that each of the memory cells has the soft erase state or one program state greater than the second reference voltage. | 02-27-2014 |
20140056092 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device, comprising a memory cell block configured to include word lines disposed between a drain select line and a source select line, a voltage generation circuit configured to generate a compensation voltage when an erase operation is performed, and a row decoder configured to apply the compensation voltage to word lines adjacent to each of the drain select line and the source select line, and apply a word line voltage less than the compensation voltage to the other word lines, and a method of operating the same are disclosed. | 02-27-2014 |
20140241092 | SUB-BLOCK DISABLING IN 3D MEMORY - Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described. | 08-28-2014 |
20140269132 | NEGATIVE CHARGE PUMP REGULATION - A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump. | 09-18-2014 |
20140269133 | Background Auto-refresh Apparatus and Method for Non-Volatile Memory Array - A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed. | 09-18-2014 |
20150078111 | INCREASED I/O RATE FOR SOLID STATE STORAGE - A storage device issues parallel or concurrent write and erase commands, to write data in response to a request, and to erase blocks marked for deletion to free storage space for subsequent write requests. The storage device receives a write request from a disk controller to write data to a storage array. The storage device determines that one or more blocks are marked for deletion. In response to receiving the write request and determining that blocks are marked for deletion, the storage device issues a write command on a first media access channel for a first location of the storage array, and issues an erase command on a second media access channel for a different storage location of the storage array. Thus, the commands are issued concurrently on different channels. | 03-19-2015 |
20150117129 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD THEREOF - A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory cells, and a control logic suitable for controlling the peripheral circuit unit during the program and erase operations and counting a pulse number of the program and erase voltages to store a resultant count number as status data. | 04-30-2015 |
20150303203 | NONVOLATILE MEMORY DEVICE HAVING SINGLE-LAYER GATE, METHOD OF OPERATING THE SAME, AND MEMORY CELL ARRAY THEREOF - A nonvolatile memory device includes a single-layer gate, a first area, and a second area. The first area includes a first well region, a first contact region arranged in the first well region, and source and drain regions arranged at both sides of the single-layer gate in the first well region. The second area includes a second well region, a second contact region arranged to overlap a part of the single-layer gate in the second well region, and a third contact region arranged in the second well region. | 10-22-2015 |