Entries |
Document | Title | Date |
20080198641 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND LAYOUT METHOD THEREOF - A semiconductor integrated circuit device includes a memory macro and M (N is an integer more than 1) passage wirings. The memory macro includes a memory cell array comprising memory cells which are arranged in a matrix, digit line pairs connected with the memory cells and extending in a column direction, and a column peripheral circuit connected with the digit line pairs and comprising a sense amplifier circuit. The M (M is an integer more than 1) passage wirings are arranged to extend in a row direction orthogonal to the digit line pairs. The arrangement of the M passage lines above the column peripheral circuit is forbidden. | 08-21-2008 |
20080205112 | Apparatus for Hardening a Static Random Access Memory Cell from Single Event Upsets - A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first inverter and a second inverter connected to each other in a cross-coupled manner. The SEU hardened memory cell also includes a first resistor, a second resistor and a capacitor. The first resistor is connected between an input of the first inverter and an output of the second inverter. The second resistor is connected between an input of the second inverter and an output of the first inverter. The capacitor is connected between an input of the first inverter and an input of the second inverter. | 08-28-2008 |
20080205113 | Inter-transmission multi memory chip, system including the same and associated method - A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip. | 08-28-2008 |
20080212353 | SRAM design with separated VSS - An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other. | 09-04-2008 |
20080219037 | INTEGRATED CIRCUIT, MEMORY DEVICE, METHOD OF OPERATING AN INTEGRATED CIRCUIT, AND METHOD OF DESIGNING AN INTEGRATED CIRCUIT - An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of logical elements and a bus carrying signals for said plurality of logical elements. The integrated circuit also comprises a routing unit having an input coupled to said bus and a plurality of outputs to route signals received at said input to at least one of said outputs. The integrated circuit also comprises a plurality of lines coupled to said plurality of outputs to conduct said signals from said routing unit to at least one of said plurality of logical elements, wherein at least one of said plurality of lines couples said routing unit to only one of said logical elements. | 09-11-2008 |
20080239782 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line which is provided above a semiconductor substrate and runs in a first direction, a source line which is provided above the semiconductor substrate and runs in the first direction, an active area which is provided in the semiconductor substrate and extends in the first direction, first and second selection transistors which are formed on the active area and share a source region electrically connected to the source line, a first memory element having one end electrically connected to a drain region of the first selection transistor and the other end electrically connected to the bit line, and a second memory element having one end electrically connected to a drain region of the second selection transistor and the other end electrically connected to the bit line. | 10-02-2008 |
20080239783 | Semiconductor memory devices having strapping contacts - Semiconductor memory devices having strapping contacts with an increased pitch are provided. The semiconductor memory devices include cell regions and strapping regions between adjacent cell regions in a first direction on a semiconductor substrate. Active patterns extend in the first direction throughout the cell regions and strapping regions and are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines extend in the first direction throughout the cell regions and the strapping regions and are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines extend in the second direction to intersect the active patterns and the first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. Strapping contacts are in the strapping regions and configured such that the active patterns contact with the first interconnection lines through the strapping contacts. | 10-02-2008 |
20080247212 | MEMORY SYSTEM HAVING POINT-TO-POINT (PTP) AND POINT-TO-TWO-POINT (PTTP) LINKS BETWEEN DEVICES - A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link. | 10-09-2008 |
20080266926 | TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES - Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit. | 10-30-2008 |
20080266927 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a 6F | 10-30-2008 |
20080273366 | DESIGN STRUCTURE FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY - A design structure embodied in a machine readable medium used in a design process includes a static random access memory (SRAM) device having a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation. | 11-06-2008 |
20090021973 | SEMICONDUCTOR MEMORY DEVICE - Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line. | 01-22-2009 |
20090021974 | SEMICONDUCTOR DEVICE - A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate. | 01-22-2009 |
20090027941 | SEMICONDUCTOR MEMORY DEVICE WITH POWER SUPPLY WIRING ON THE MOST UPPER LAYER - A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit. | 01-29-2009 |
20090059641 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are disclosed. | 03-05-2009 |
20090059642 | Memory Controller With Multi-Modal Reference Pad - A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller. | 03-05-2009 |
20090067210 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 03-12-2009 |
20090073739 | DYNAMIC RECONFIGURATION OF SOLID STATE MEMORY DEVICE TO REPLICATE AND TIME MULTIPLEX DATA OVER MULTIPLE DATA INTERFACES - Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner. | 03-19-2009 |
20090080229 | SINGLE-LAYER METAL CONDUCTORS WITH MULTIPLE THICKNESSES - A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are formed having different thicknesses at different locations. | 03-26-2009 |
20090080230 | eDRAM Hierarchical Differential Sense AMP - In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches. | 03-26-2009 |
20090086521 | MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME - Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states. | 04-02-2009 |
20090086522 | ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME - An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL | 04-02-2009 |
20090091963 | MEMORY DEVICE - A first DRAM device comprises a first input connected to a first trace line to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line to receive the address signal and a second input to receive the operating voltage. A first signal termination structure is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage. | 04-09-2009 |
20090091964 | Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region - A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity type, which is located between the first well region and the second well region. The memory cell further includes a first tap diffused layer of the first conductivity type for supplying a potential to the first well region, a second tap diffused layer of the first conductivity type for supplying the potential to the second well region, the first and second tap diffused layers being arranged substantially on a diagonal line in the layout of the SRAM cell, and a metal interconnection connected to the first and second tap diffused layers, the metal interconnection passing on the third well region in the SRAM cell. | 04-09-2009 |
20090097298 | Integrated Circuit, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell - According to one embodiment of the present invention, an integrated circuit includes an arrangement of memory cells. Each memory cell is connected to a programming current path used for programming the memory cell, and a sensing current path used for sensing the memory state of the memory cell. The programming current path and the sensing current path are at least partly separated from each other. | 04-16-2009 |
20090109721 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE. - An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines. | 04-30-2009 |
20090129137 | Semiconductor storage device - A semiconductor storage device includes a memory array compartmentalized into first and second regions alternately arranged. The second regions are formed by odd and even columns alternately arranged. The semiconductor storage device includes: a memory mat array arranged in each first region; a sense amp array arranged in each second region; local IO lines arranged in each second region and connected to the sense amp array; main IO lines crossing the first and second regions; and a read/write amplifier arranged in each second region and at an intersection region where the local IO lines cross the main IO lines. The read/write amplifier in an odd column is connected to a local IO line therein and to a local IO line in the next odd column. The read/write amplifier in an even column is connected to a local 10 line therein and to a local IO line in the next even column. | 05-21-2009 |
20090154215 | REDUCING NOISE AND DISTURBANCE BETWEEN MEMORY STORAGE ELEMENTS USING ANGLED WORDLINES - Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and other segments that are angled from a direction parallel to the x-axis based in part on a predetermined angle. Adjacent storage elements can be positioned at respective ends of an angled segment of a wordline to facilitate increasing the distance between such storage elements, as compared to the distance between storage elements associated with an orthogonal memory array, where the increase in distance can be based in part on the predetermined angle. The size of the memory array can be the same or substantially the same size, as compared to an orthogonal memory array. | 06-18-2009 |
20090154216 | Semiconductor memory device and semiconductor device group - A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region. | 06-18-2009 |
20090175062 | FEEDBACK STRUCTURE FOR AN SRAM CELL - Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure. | 07-09-2009 |
20090175063 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL ARRAY HAVING MEMORY CELLS USING FLOATING BODY TRANSISTORS - A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines. | 07-09-2009 |
20090185408 | MEMORY DEVICE, MEMORY SYSTEM AND METHOD FOR DESIGN OF MEMORY DEVICE - A memory device may include, but is not limited to, at least one memory module, and a plurality of lumped constant circuit elements. The at least one memory module is electrically coupled to a transmission system that has a characteristic impedance. The plurality of lumped constant circuit elements with an inductance is placed on the transmission system symmetrically with reference to the at least one memory module. The plurality of lumped constant circuit elements in cooperation with the at least one memory module performs as at least one low-pass filter. | 07-23-2009 |
20090196086 | HIGH BANDWIDTH CACHE-TO-PROCESSING UNIT COMMUNICATION IN A MULTIPLE PROCESSOR/CACHE SYSTEM - A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set. | 08-06-2009 |
20090201712 | PRESETABLE RAM - A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided on a single mask layer in a semiconductor fabrication process for the memory cell. A program-selectable one of two sets of vias may communicate with one reset device to the reset line and the other reset device to ground. In this way a single and programmatically determinable logic state may be produced in the memory cell with reset signaling. Otherwise, the memory cell is capable of retaining a logic state according to read/write processes. The memory cell may be implemented in an array where all or some of the cells may be reset at once. | 08-13-2009 |
20090213635 | SEMICONDUCTOR MEMORY DEVICE HAVING REPLICA CIRCUIT - A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively. | 08-27-2009 |
20090231899 | PHASE CHANGE RANDOM ACCESS MEMORY AND LAYOUT METHOD OF THE SAME - A phase change random access memory (PRAM) includes a cell array divided into an active region and a dummy active region. A bitline is formed across the active region and the dummy active region and a global wordline is formed in the active region so as to intersect with the bitline. The cell array includes a phase change memory cell formed at an intersection point of the bitline and the global wordline that is electrically connected with the bitline and the global wordline. The cell array further includes a phase change dummy cell formed below the bitline in the dummy active region that is electrically isolated from the bitline. The dummy cell maintains a turn-off state as the dummy cell and the bitline are electrically isolated from each other. | 09-17-2009 |
20090237972 | MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS - A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells. | 09-24-2009 |
20090244949 | Memory Device and Method Providing Logic Connections for Data Transfer - In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections. | 10-01-2009 |
20090244950 | SEMICONDUCTOR MEMORY DEVICE HIGHLY INTEGRATED IN DIRECTION OF COLUMNS - First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns. | 10-01-2009 |
20090257262 | DRAM AND MEMORY ARRAY - A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size. | 10-15-2009 |
20090257263 | Method and Apparatus for Computer Memory - A method and apparatus for forming computer memory | 10-15-2009 |
20090268500 | WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE - Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance. | 10-29-2009 |
20090268501 | Novel SRAM Cell Array Structure - This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer. | 10-29-2009 |
20090268502 | Semiconductor device with non-volatile memory and random access memory - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data. | 10-29-2009 |
20090285006 | Semiconductor Memory and Method for Operating a Semiconductor Memory - A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier. | 11-19-2009 |
20090296446 | SEMICONDUCTOR MEMORY - A semiconductor memory of an aspect of the present invention including a main bit line, a first and second sub-bit line, a first resistive memory element which has a first terminal being connected with the main bit line, a first select transistor which has one end of a first current path being connected with the second terminal of the first resistive memory element and the other end of the first current path being connected with the first sub-bit line, a second resistive memory element which has a third terminal being connected with the main bit line, and a second select transistor which has one end of a second current path being connected with the fourth terminal of the second resistive memory element and the other end of the second current path being connected with the second sub-bit line. | 12-03-2009 |
20090303769 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 12-10-2009 |
20090303770 | Memory chip and semiconductor device - A memory chip is provided, including internal signal/data terminals disposed in a central part of the memory chip and memory cell arrays arranged around the internal terminals to surround the same and electrically connected thereto. A semiconductor device is also provided, having a memory chip and a logic chip stacked with an interposer interposed therebetween. The logic chip has internal signal/data terminals disposed in its central part and electrically connected to the memory chip. The memory chip includes internal signal/data terminals disposed in its central part, and memory arrays arranged around the internal terminals to surround the same and connected thereto. The internal terminals of the logic chip are connected to the internal terminals of the memory chip via through holes (through electrodes) in the interposer. | 12-10-2009 |
20090310396 | DIGITAL MEMORY WITH CONTROLLABLE INPUT/OUTPUT TERMINALS - Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being presented is the same as a previously presented digital value. | 12-17-2009 |
20100020584 | High Speed Memory Module - A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three positions for connecting memory modules. A plurality of memory chips may be mounted on the circuit board. The circuit board may include a plurality of D/Q traces to couple a corresponding plurality of D/Q signals from respective contacts to the plurality of memory chips or to one or more buffer chips that isolate the system memory bus from the memory chips. Each of the plurality of D/Q traces may have a predetermined trace impedance selected to provide a predetermined D/Q signal quality level when the memory module is installed in any of the three positions on the system memory bus and equivalent memory modules are installed in the other two positions. | 01-28-2010 |
20100020585 | METHODS AND APPARATUS OF STACKING DRAMS - Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. | 01-28-2010 |
20100027309 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 02-04-2010 |
20100034005 | SEMICONDUCTOR MEMORY APPARATUS FOR CONTROLLING PADS AND MULTI-CHIP PACKAGE HAVING THE SAME - A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups. | 02-11-2010 |
20100061133 | MEMORY MODULE AND METHOD OF PERFORMING THE SAME - A memory module and a method of performing the same for access of an external electronic device are provided herein. The memory module includes a NAND-type flash memory, a dynamic random access memory (DRAM) unit, and a memory controller. The dynamic random access memory unit which is electrically connected to the NAND-type flash memory includes a dynamic random access memory and an internal power. The memory controller is used for controlling at least one of both the NAND-type flash memory and the dynamic random access memory unit. When the memory module is disconnected with the external electronic device, the internal power of the dynamic random access memory unit powers the dynamic random access memory, actively. Accordingly, data stored in the dynamic random access memory will be retained. | 03-11-2010 |
20100061134 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may include an interface chip having a via to accommodate connection of the memory device to the substrate. Other apparatus, systems, and methods are disclosed. | 03-11-2010 |
20100067280 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100091542 | Memory Module Having a Memory Device Configurable to Different Data Pin Configurations - A memory module includes a memory device having a plurality of data pins and conductive lines electrically connected to the plurality of data pins. The memory device is configurable, using at least one input to the memory device, to a data pin configuration selected from among a plurality of different data pin configurations. The plurality of different data pin configurations include a first data pin configuration that uses a first number of data pins of the memory device, and a second data pin configuration that uses a second, different number of data pins. | 04-15-2010 |
20100091543 | SEMICONDUCTOR MEMORY APPARATUS INCLUDING A COUPLING CONTROL SECTION - A semiconductor memory apparatus is disclosed having a dual open bit line structure In the dual open bit line structure, bit lines or bit line bars are each arranged side by side in adjoining cell mats. The semiconductor memory apparatus includes a coupling control section connected between at least one pair of adjoining bit lines or at least one pair of adjoining bit line bars and is driven by a bit line equalize signal. The coupling control section prevents a coupling phenomenon from occurring between pairs of bit lines and bit line bars. | 04-15-2010 |
20100091544 | COUPLINGS WITHIN MEMORY DEVICES - A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed. | 04-15-2010 |
20100097835 | 4 F2 MEMORY CELL ARRAY - An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch. | 04-22-2010 |
20100110749 | Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads - A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad. | 05-06-2010 |
20100118582 | MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME - A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The memory module also comprises of a plurality of chip select pin terminals configured to transfer a plurality of chip select signals provided from an external device to the plurality of memory chips. | 05-13-2010 |
20100128508 | SEMICONDUCTOR MEMORY DEVICE - The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first resistance value and a second resistance value higher than the first resistance value. The contact arrangement portion is formed to arrange a plurality of contacts on a plane. The contacts are connected to the first wirings or the second wirings. The probe can move along the plane to electrically contact with either of the contacts. | 05-27-2010 |
20100128509 | Three-Dimensional Semiconductor Devices and Methods of Operating the Same - Provided are a three-dimensional semiconductor device and a method of operating the same. The three-dimensional semiconductor device includes: a plurality of word line structures on a substrate; active semiconductor patterns between the plurality of word line structures; and information storage elements between the plurality of word line structures and the active semiconductor patterns. Each of the plurality of word line structures includes a plurality of word lines spaced apart from each other and stacked, and the active semiconductor patterns include electrode regions and channel regions, the electrode regions and the channel regions having different conductive types and being alternately arranged. | 05-27-2010 |
20100135056 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit. | 06-03-2010 |
20100135057 | MULTI-PORT MEMORY DEVICE HAVING SERIAL INPUT/OUTPUT INTERFACE - A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged. | 06-03-2010 |
20100142249 | NONVOLATILE MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile memory cells, write global bit lines shared by the plurality of memory banks, read global bit lines shared by the plurality of memory banks, and a dummy global bit line arranged between the write global bit lines and the read global bit lines, wherein the dummy global bit line is configured and operable to reduce noise affecting a write bit line involved in a write operation or noise affecting a read global bit line involved in a read operation. | 06-10-2010 |
20100142250 | SEMICONDUCTOR MEMORY AND SYSTEM - A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines when one of the access control circuits is used, and swaps the connections between a pair of data terminals and a pair of data lines when the other one of the access control circuits is used. Accordingly, it is possible to give a data signal at the same logic level to bit lines with different logics from each other. Stress can be given between a contact arranged between a pair of the access control circuits and bit lines adjacent to both sides of the contact. Consequently, designing of a test pattern can be simplified, and test efficiency can be improved. | 06-10-2010 |
20100142251 | MEMORY DEVICES HAVING PROGRAMMABLE ELEMENTS WITH ACCURATE OPERATING PARAMETERS STORED THEREON - Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for each memory device in the system. | 06-10-2010 |
20100142252 | RECONFIGURABLE INPUT/OUTPUT IN HIERARCHICAL MEMORY LINK - A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected together, typically by point-to-point links. When the memory system configuration is such that at least one of the ports in at least one of the memory devices is not used, one or more other ports can use the pins that may otherwise have been used by the unused ports. As a result, a set of reconfigurable, shared pins is defined in which two ports share the pins. The port that is not being used in a particular application for the memory device is not connected to the shared pins, and another port that is being used in the application is connected to the shared pins. This allows for the used of fewer package pins and, consequently, reduced package size. | 06-10-2010 |
20100165694 | Memory Cell Array - Disclosed is a memory cell array including: word lines and first and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and a switching element formed inside a contact hole, the switching element includes first and second conductive layers and a gap in which a resistance value is changed by applying a predetermined voltage, each word line is connected to a gate electrode, each first bit line is connected to a second electrode, each second bit line is connected to the second conductive layer, and data is written by supplying a write voltage to the first bit line connected to the selected memory cell and specifying the word line connected to the memory cell, and data is read by supplying a read voltage to the first bit lines connected to the memory cell and specifying the word line connected to the memory cells. | 07-01-2010 |
20100165695 | Memory Cell Array - Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less. | 07-01-2010 |
20100177546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 07-15-2010 |
20100188877 | Storage device - The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type. | 07-29-2010 |
20100188878 | SEMICONDUCTOR DEVICE THAT SUPRESSES MALFUNCTIONS DUE TO VOLTAGE REDUCTION - A semiconductor device includes a first pad that supplies power to sense amplifiers, a second pad that supplies power to a first circuit connected to the sense amplifiers, a third pad that receives a signal input or outputs a signal at a frequency equal to or higher than a first frequency, and a fourth pad that receives a signal input or outputs a signal at a second frequency lower than the first frequency. The first pad is arranged between and adjacent to the second pads respectively, or arranged between and adjacent to the second and fourth pads respectively. Additionally, the first pad is arranged between the third pads, which are respectively arranged on both sides of the first pad, to be adjacent to the second pad so as to hold the second pad or to be adjacent to the fourth pad so as to hold the fourth pad. | 07-29-2010 |
20100195364 | Semiconductor device - The invention provides a semiconductor device having, in each of stacked chip dies, not only vias the number of which corresponds to the number of signals input to and output from a single chip die but also vias the number of which corresponds to the number of signals input to and output from the stacked chip dies, and switches for controlling the input and output to and from the vias. The conduction and non-conduction of the switches are controlled by means of ROMs, whereby signals from the plurality of chip dies stacked can be output in parallel. This eliminates the need of increasing the data transfer speed of each chip die in accordance with the transfer speed of the system. | 08-05-2010 |
20100202181 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction. | 08-12-2010 |
20100202182 | MEMORY DEVICES, SYSTEMS AND METHODS USING MULTIPLE 1/N PAGE ARRAYS AND MULTIPLE WRITE/READ CIRCUITS - A memory device architecture includes N arrays respectively for storing a 1/N of a page and N write/read circuits, where N is a natural number, respectively for writing or reading a 1/N of the page to/from each of the N arrays. | 08-12-2010 |
20100214814 | SEMICONDUCTOR MEMORY DEVICE, MEMORY DEVICE SUPPORT AND MEMORY MODULE - In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal. | 08-26-2010 |
20100220510 | Optimized Selection of Memory Chips in Multi-Chips Memory Devices - A method includes accepting a definition of a type of multi-unit memory device ( | 09-02-2010 |
20100254173 | DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS - A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory. | 10-07-2010 |
20100259963 | Data line layouts - A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads. | 10-14-2010 |
20100259964 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 10-14-2010 |
20100277965 | Memory System Having Multiple Vias at Junctions Between Traces - An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line. | 11-04-2010 |
20100302830 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a number of chips, each of the chips including a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal, a chip operation detection unit configured to output an operation state signal in response to the first signal, and an internal circuit configured to operate in response to a power source voltage and a control signal in response to the second signal being received. | 12-02-2010 |
20100309708 | SEMICONDUCTOR MEMORY - Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA | 12-09-2010 |
20100315853 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit including a memory macro, such as a DRAM, an SRAM, a ROM, a flash memory, or the like, and a logic circuit, memory macro test-dedicated pads are provided on the memory macro, whereby an increase in the number of normal pads is reduced or prevented to reduce or prevent an increase in the chip area. Moreover, by fixing arrangement (positions) of the pads provided on the memory macro between memory macros of a plurality of memory macro-including semiconductor integrated circuits, a single common probe card for a single chip can be used for the memory macro-including semiconductor integrated circuits, thereby providing low-cost testing. | 12-16-2010 |
20100321973 | MEMORY MODULE, SYSTEM AND METHOD OF MAKING SAME - A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices. The first and second portions of memory devices are grouped into a plurality of memory device stacks, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of a plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals. | 12-23-2010 |
20110007541 | FLOATING BODY MEMORY CELL SYSTEM AND METHOD OF MANUFACTURE - A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc. | 01-13-2011 |
20110019457 | Flash memory - A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. | 01-27-2011 |
20110019458 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS - A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array. | 01-27-2011 |
20110026292 | Semiconductor device having hierarchically structured bit lines and system including the same - To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded. | 02-03-2011 |
20110026293 | SEMICONDUCTOR DEVICE - In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other. | 02-03-2011 |
20110026294 | INFORMATION RECORDING AND REPRODUCING DEVICE - According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first and second layers and is capable of reversibly transitioning between a first state and a second state with a resistance higher than in the first state. One of the first and second layers includes a resistivity distribution layer perpendicular to a stacking direction of the first and second layers, and the recording layer. The resistivity distribution layer includes a low and a high resistivity portion. Resistivity of the high resistivity portion is higher than resistivity of the low resistivity portion. The low resistivity portion contains a transition element identical to a transition element contained in the high resistivity portion. | 02-03-2011 |
20110026295 | SEMICONDUCTOR MEMORY - To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output circuits of the signal terminals; test-purpose signal terminals fewer than the signal terminals; a selection portion which, as data to be written to the memory cells, selects data input from the signal terminals or data input from the test-purpose signal terminals, and repetitively allocates inputs of the test-purpose signal terminals to inputs of the signal terminals based on an arrangement of the signal terminals; and a test-purpose power source terminal connected to the power source terminal, and arrangement intervals of the test-purpose signal terminals and the test-purpose power source terminal are larger than an arrangement interval of the signal terminals. | 02-03-2011 |
20110038194 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion. | 02-17-2011 |
20110044085 | Serially Interfaced Random Access Memory - A serially interfaced massively parallel Random Access Memory (RAM) includes a matrix of control logic sections on one integrated circuit die, augmented by a switching matrix with an external interface to multiple high speed serial signaling means. A matrix, of the same dimension, of dense memory element arrays is implemented on a different integrated circuit die. One control logic section die and one or more others containing memory sections are joined by appropriate means to form one integrated circuit stack, implementing a matrix of independent memory units. The switching matrix translates command and data content encoded on the external signaling means bidirectionally between internal data and control signals and connects these signals to the control logic sections. Each independent memory unit ably performs atomic read-alter-writes to enable software mutual exclusion operations (MUTEXes). Each and every matrix may guard against defects by having additional rows and/or columns. | 02-24-2011 |
20110058401 | Semiconductor memory device having pad electrodes arranged in plural rows - To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area. | 03-10-2011 |
20110063884 | STRUCTURE AND METHOD FOR BACKING UP AND RESTITUTION OF DATA - A structure and a method for backing up and restitution of data allowing management of a memory space. The backup and restitution structure includes a matrix of connectors distributed in line and in column, on said matrix. Each connector of one line is connected to its two adjacent connectors. Each connector of one column is connected to its two adjacent connectors. Each line of connectors is connected to a memory of the first-in, first-out type, by a connector situated at one end of the line. Each column of connectors is connected to an input and, or output port of a data stream of the structure by a connector situated at one end of the column. Each connector propagates a data stream. An embodiment is suitable for an onboard computing system including a component, associating a computing structure and a memory space produced for example on one electronic circuit board. | 03-17-2011 |
20110069523 | Semiconductor memory device and multilayered chip semiconductor device - Disclosed here is a semiconductor memory device including: a semiconductor substrate; a plurality of pads formed on the semiconductor substrate and configured to permit data input and output; and a memory core block and an I/O block integrated on the semiconductor substrate. The data items are input and output to and from the plurality of pads at twice a maximum access rate in effect. | 03-24-2011 |
20110069524 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values. | 03-24-2011 |
20110069525 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell is connected to a first interconnection and a second interconnection and includes a plurality of layers. The plurality of layers includes a memory layer and a carbon nanotube-containing layer which is in contact with the memory layer and contains a plurality of carbon nanotubes. | 03-24-2011 |
20110069526 | HIGH PERFORMANCE SOLID-STATE DRIVES AND METHODS THEREFOR - A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses. | 03-24-2011 |
20110085367 | SWITCHED MEMORY DEVICES - A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of memory devices. Each of a plurality of data channels is configured to provide a data path between the control circuit and one of the groups of memory devices. A plurality of switches is configured to connect and disconnect one of the memory devices in a select one of the groups of memory devices to one of the plurality of data channels and concurrently connect and disconnect another of the memory devices in the select group of memory devices to a different one of the plurality of data channels. | 04-14-2011 |
20110085368 | Non-volatile memory device and method of manufacturing the same - The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines. | 04-14-2011 |
20110096584 | SEMICONDUCTOR DEVICE HAVING OPEN BIT LINE ARCHITECTURE - When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X | 04-28-2011 |
20110103123 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third data line pair; a second amplifier amplifying data on the second data line pair and delivering the amplified data to the third data line pair; a third amplifier connected to the third data line pair; and a switch control circuit controlling the second switch. Based upon a first control signal that controls precharging and equalization of the first data line pair, the switch control circuit renders the second switch conductive when precharging and equalization of the first data line pair is not carried out, and renders the second switch non-conductive when precharging and equalization of the first data line pair is carried out. | 05-05-2011 |
20110103124 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials. | 05-05-2011 |
20110128766 | Programmable Resistance Memory - A nonvolatile integrated circuit memory includes mode control circuitry that allows it to be configured as any of a plurality of memory types. | 06-02-2011 |
20110128767 | Memory With Intervening Transistor - Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition. | 06-02-2011 |
20110134678 | Semiconductor device having hierarchical structured bit line - A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained. | 06-09-2011 |
20110149629 | Semiconductor Memory Apparatus and Method of Operating the Same - A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal. | 06-23-2011 |
20110157950 | MEMORY CHIPS AND JUDGEMENT CIRCUITS THEREOF - A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indicates which mode the memory chip is operating at. The judgment circuit includes a detection unit and a sampling unit. The detection unit is coupled to a first voltage source and the option pad and further controlled by a control signal to generate at least one detection signal according to the current status of the option pad. The sampling unit samples the at least one detection signal after the control signal is asserted to generate the judgment signal. When the control signal is asserted, a level of the at least one detection signal is varied by a voltage provided by the first voltage source. | 06-30-2011 |
20110157951 | 3D CHIP SELECTION FOR SHARED INPUT PACKAGES - A multi-chip package with die having shared input and unique access IDs. A unique first ID is assigned and stored on die in a die lot. A set of die is mounted in a multi-chip package. Free access IDs are assigned by applying a sequence of scan IDs on the shared input. On each die, the scan ID on the shared input is compared with the unique first ID stored on the die. Upon detecting a match, circuitry on the die is enabled for a period of time to write an access ID in nonvolatile memory, whereby one of the die in the multi-chip package is enabled at a time. Also, the shared input is used to write a free access ID in nonvolatile memory on the one enabled die in the set. The unique first IDs can be stored during a wafer level sort process. | 06-30-2011 |
20110157952 | SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF - Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip. | 06-30-2011 |
20110157953 | MEMORY DEVICE HAVING DATA PATHS - Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus. | 06-30-2011 |
20110164446 | APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES - A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector. | 07-07-2011 |
20110170328 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to the present invention includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include a second portion, a second lead portion and a second inclined portion. The first and second portions are located in parallel with a same pitch, the first and second lead portions are located with a pitch which is larger than the pitch of the first and second portions, the first and second inclined portions extend the same direction at a predetermined angle. | 07-14-2011 |
20110188285 | PERMANENT SOLID STATE MEMORY - A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The data layer is at least partially conductive such that a voltage applied between a selected first wire in the first wire array and a selected second wire in the second wire array creates a heating current through the data layer at a data point between the first wire and the second wire. The heating current causes a data layer material to melt and recede to form a permanent void. Control elements are operably connected to apply voltages to predetermined combinations of wires to form permanent voids at data points throughout the solid state memory device. | 08-04-2011 |
20110188286 | ELECTROMECHANICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction. The bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position. | 08-04-2011 |
20110199805 | Selective access memory circuit - A selective access memory circuit (SAMC) is described. The SAMC is a class of complex programmable memory device (CPMD) that reconfigures access to memory cells by using gates in an integrated gate array mechanism configured at regular intervals in memory arrays. CPMDs are applied to embedded controllers, microprocessors, DSPs and system on chip (SoC) circuit architectures. | 08-18-2011 |
20110199806 | UNIVERSAL STRUCTURE FOR MEMORY CELL CHARACTERIZATION - An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type and are not connected together, where each node in the first storage node set is connected to a port in the first port set, where each node in the second storage node set is connected to a port in the second port set, where each of the other nodes is connected to one of the other ports, and where each of the other ports is connected to one and only one of the other nodes. | 08-18-2011 |
20110228583 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array. | 09-22-2011 |
20110249482 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first active area in a semiconductor substrate, memory cells on the semiconductor substrate, first bit lines, first line, a second line, a third line, and a fourth line. The first line extends in a direction that intersects with the first bit lines and transmits a control potential applied to unselected ones of second bit lines connected to the memory cells. The second line is electrically connected to the first line and extends along the first bit lines. The third line is electrically connected to the second line and extends in a direction that intersects with the first bit lines. The fourth line electrically connects both the third line and portions in the active area corresponding to nodes to which the control potential is applied. | 10-13-2011 |
20110249483 | STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE - A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip. | 10-13-2011 |
20110255323 | MEMORY/LOGIC CONJUGATE SYSTEM - There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories | 10-20-2011 |
20110255324 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SECURING GATE PERFORMANCE AND CHANNEL LENGTH - A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged to cross with the word lines, and delimiting a plurality of crossing regions where the word lines intersect the bit lines and a plurality of unit memory cell regions with each cell region bounded by an adjacent pair of the word lines and an adjacent pair of the bit lines; and gate electrodes for the respective unit memory cell regions, each gate electrode electrically connected with any one of a pair of word lines which delimit a corresponding unit memory cell, and formed such that at least a portion of the gate electrode is bent toward a bit line direction. | 10-20-2011 |
20110261603 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND BUNDLING OF CONTROL SIGNALS - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together. | 10-27-2011 |
20110267866 | EXTENSIBLE THREE DIMENSIONAL CIRCUIT HAVING PARALLEL ARRAY CHANNELS - An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access layer. The crossbar array layers include parallel channels, the parallel channels being formed from two classes of vias, the first class being pillar vias connected to relatively short stub lines, and the second class being traveling-line vias connected to long lines that travel away from the via; pillar vias and traveling-line vias being configured to connect to crossing lines such that each crossing point between the lines is uniquely addressed by one pillar via and one traveling-line via. Programmable crosspoint devices are disposed between the crossing lines. | 11-03-2011 |
20110292708 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 12-01-2011 |
20110305058 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING SAME - A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines. | 12-15-2011 |
20110305059 | Semiconductor Memory Devices - Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer. | 12-15-2011 |
20110305060 | WIRING SUBSTRATE IN WHICH EQUAL-LENGTH WIRES ARE FORMED - In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil. | 12-15-2011 |
20110317465 | Methods and Systems for Reducing Heat Flux in Memory Systems - The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus. | 12-29-2011 |
20120002456 | METHOD OF ARRANGING PADS IN SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE USING THE METHOD, AND PROCESSING SYSTEM HAVING MOUNTED THEREIN THE SEMICONDUCTOR MEMORY DEVICE - A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip. | 01-05-2012 |
20120008361 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes cell gate lines arranged in parallel over a semiconductor substrate, gate lines for select transistors disposed over the semiconductor substrate adjacent to the gate lines of the outermost memory cells, from among the gate lines for the memory cells, and metal lines coupled to the select transistors through contacts. | 01-12-2012 |
20120020138 | TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME - A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor. | 01-26-2012 |
20120033477 | MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS - Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used to implement the filter. In some examples, signal components at 800 MHz may be attenuated by a stub, which may improve ringback. | 02-09-2012 |
20120039104 | METHOD AND APPARATUS FOR BURIED WORD LINE FORMATION - An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate. | 02-16-2012 |
20120044734 | BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME - A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an i | 02-23-2012 |
20120044735 | STRUCTURES WITH INCREASED PHOTO-ALIGNMENT MARGINS - Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery. | 02-23-2012 |
20120081941 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type. | 04-05-2012 |
20120106227 | INTEGRATED CIRCUIT - An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as test data in response to the write command in a test operation mode, and output the stored test data in response to the read command, and a connection selection unit configured to selectively connect a data input/output terminal of the normal data storage unit or a data output terminal of the test data storage unit to a global line based on whether the integrated circuit is in a first or second one of the normal operation mode and the test operation mode, respectively. | 05-03-2012 |
20120106228 | METHOD AND APPARATUS FOR OPTIMIZING DRIVER LOAD IN A MEMORY PACKAGE - An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect. | 05-03-2012 |
20120106229 | Semiconductor device - To include stacked plural core chips, each of which includes a first through silicon via for transferring write data and a second through silicon via for transferring read data, and an interface chip commonly connected to the core chips. The interface chip includes a data input/output terminal, an input buffer provided between the data input/output terminal and the first through silicon via, and an output buffer provided between the data input/output terminal and the second through silicon via. With this configuration, the write data and the read data are transferred through the different through silicon vias, whereby the collision of data is not caused even when continuous accesses are made to different ranks. | 05-03-2012 |
20120106230 | SEMICONDUCTOR MEMORY DEVICE - The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first resistance value ant a second resistance value higher than the first resistance value. The contact arrangement portion is formed to arrange a plurality of contacts on a plane. The contacts are connected to the first wirings or the second wirings. The probe can move along the plane to electrically contact with either of the contacts. | 05-03-2012 |
20120113705 | CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD - Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin. | 05-10-2012 |
20120127774 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - All interface pins for transmitting and receiving a signal having a predetermined function of a semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circuit element. The one side of the semiconductor integrated circuit element is adjacent to two of sides of a BGA substrate, the two sides being not parallel to the one side. Of balls provided on the BGA substrate, balls electrically connected to the interface pins for transmitting and receiving a signal having a predetermined function are provided between the one side of the semiconductor integrated circuit element and the two sides of the BGA substrate. | 05-24-2012 |
20120134194 | BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM - A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device. | 05-31-2012 |
20120147651 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL LAYERS OF SELECT DEVICES - A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 06-14-2012 |
20120155142 | PHASE INTERPOLATORS AND PUSH-PULL BUFFERS - Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers. | 06-21-2012 |
20120182778 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection. | 07-19-2012 |
20120182779 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a substrate, an interconnect layer, a memory layer, a circuit layer, first and second contact interconnects. The interconnect layer is provided on the substrate and includes first and second interconnects. The memory layer is provided between the substrate and the interconnect layer and includes first and second memory cell array units. The first and second memory cell array units include a plurality of memory cells. The circuit layer is provided between the memory layer and the substrate and includes a first circuit unit. The first contact interconnect is provided between the first and second memory cell array units and electrically connects one end of the first circuit unit to the first interconnect. The second contact interconnect electrically connects a second end of the first circuit unit different from the first end to the second interconnect. | 07-19-2012 |
20120182780 | Memory System with Multi-Level Status Signaling and Method for Operating the Same - A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level. | 07-19-2012 |
20120195089 | SEMICONDUCTOR MEMORY CHIP AND MULTI-CHIP PACKAGE USING THE SAME - A semiconductor memory chip includes a first pad unit configured to receive a first data and a first strobe signal, and a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the first data and the first strobe signal to a second write path circuit in a swap mode. | 08-02-2012 |
20120195090 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips. | 08-02-2012 |
20120201068 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. | 08-09-2012 |
20120206953 | MEMORY EDGE CELL - A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively. | 08-16-2012 |
20120206954 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path. | 08-16-2012 |
20120212990 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip. | 08-23-2012 |
20120218805 | Configurable Memory Array - Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode. | 08-30-2012 |
20120243285 | MULTIPLE WRITE DURING SIMULTANEOUS MEMORY ACCESS OF A MULTI-PORT MEMORY DEVICE - A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously. | 09-27-2012 |
20120250388 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 10-04-2012 |
20120262976 | SEMICONDUCTOR STORAGE DEVICE - When plural diffusion layers are shared in order to save an area of a semiconductor integrated circuit, parasitic capacities of wirings coupled to those diffusion layers are changed. Nonetheless, a semiconductor layout balancing capacitive loads of paired wirings coupled to the diffusion layers with each other is provided. The diffusion layers coupled to the respective paired wirings are alternately arranged or staggered to balance the respective capacitive loads of the paired wirings with each other. | 10-18-2012 |
20120262977 | MEMORY MODULES AND MEMORY DEVICES HAVING MEMORY DEVICE STACKS, AND METHOD OF FORMING SAME - A memory module, system and method of forming the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices. The first and second portions of memory devices are grouped into a plurality of memory device stacks, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of a plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals. | 10-18-2012 |
20120268978 | SEMICONDUCTOR MEMORY DEVICE IN WHICH CAPACITANCE BETWEEN BIT LINES IS REDUCED, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers. | 10-25-2012 |
20120281449 | SEMICONDUCTOR CHIP, MEMORY CHIP, SEMICONDUCTOR PACKAGE AND MEMORY SYSTEM - A semiconductor chip includes a plurality of signal and power pads; and a plurality of chip selection pads, wherein at least one of the plurality of chip selection pads includes a normal pad and an inverse pad. | 11-08-2012 |
20120287694 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower isolation region traversing the cell array region and the contact region, and forming sacrificial films sequentially stacked on the sacrificial film patterns, and forming an opening that penetrates the thin film structure to expose the lower isolation region of the cell array region, the opening being restrictively formed in the cell array region. | 11-15-2012 |
20120287695 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include a second portion, a second lead portion and a second inclined portion. The first and second portions are located in parallel with a same pitch, the first and second lead portions are located with a pitch which is larger than the pitch of the first and second portions, the first and second inclined portions extend the same direction at a predetermined angle. | 11-15-2012 |
20120294059 | STACKED MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - At least one example embodiment discloses a stacked memory device including a plurality of stacked memory chips, each of the memory chips including a memory array, a plurality of through silicon vias (TSVs) operatively connected to the plurality of stacked memory chips, micro channels configured to access the memory arrays and at least one circuit in each memory chip, the at least one circuit configured to vary a number of the micro channels accessing the memory array. | 11-22-2012 |
20120300529 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers. | 11-29-2012 |
20120307543 | SEMICONDUCTOR DEVICE - A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells, and precharge circuits (to charge the bit lines; column select signal lines extending in the column direction for selecting subarray columns; main word lines for selecting subarray rows; and precharge signal lines for supplying precharge signals to the precharge circuits; and at least two of the subarrays formed in the row direction or the column direction are controlled by the same logic according to the precharge signal. | 12-06-2012 |
20120307544 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other. | 12-06-2012 |
20120320652 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit. | 12-20-2012 |
20120320653 | SEMICONDUCTOR SYSTEM - A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 12-20-2012 |
20120320654 | SEMICONDUCTOR SYSTEM - A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 12-20-2012 |
20120327697 | DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS - A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory. | 12-27-2012 |
20130003435 | Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about | 01-03-2013 |
20130010516 | MEMORY CHIP WITH MORE THAN ONE TYPE OF MEMORY CELL - A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines. | 01-10-2013 |
20130010517 | SELF-DISABLING CHIP ENABLE INPUT - A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad. | 01-10-2013 |
20130033916 | SEMICONDUCTOR DEVICE HAVING PLURAL CIRCUIT BLOCKS THAT OPERATE THE SAME TIMING - Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction. | 02-07-2013 |
20130039111 | CONNECTION AND ADDRESSING OF MULTI-PLANE CROSSPOINT DEVICES - A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices. | 02-14-2013 |
20130039112 | SEMICONDUCTOR DEVICE - In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other. | 02-14-2013 |
20130044530 | LAYOUT OF MEMORY CELLS AND INPUT/OUTPUT CIRCUITRY IN A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit. | 02-21-2013 |
20130051110 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core. | 02-28-2013 |
20130058148 | HIGH DENSITY MEMORY MODULES - Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (μP), or application-specific integrated circuit (ASIC). These interconnects can provide for greater module interconnect flexibility, operating speed and operating efficiency. Some memory module embodiments according to the present invention comprises a plurality of solid state memory devices arranged on a first printed circuit board. A second printed circuit board is on and electrically connected to the first printed circuit board, with the second printed circuit board having a pin-out for direct coupling to a host device. | 03-07-2013 |
20130058149 | MEMORY DEVICES, METHODS OF STORING AND READING DATA, SMM JUNCTIONS, AND METHODS OF PREPARING ALUMINA SUBSTRATES - Various aspects of the invention provide memory devices, methods of storing and reading data, and silver/molecular-layer/metal (SMM) junctions. One aspect of the invention provides a memory device including a plurality of SMM junctions and an electrical structure configured to permit application of electricity across one or more of the plurality of SMM junctions. Another aspect of the invention provides a method of storing data on a memory device including a plurality of SMM junctions. The method includes applying electrical energy across a subset of the SMM junctions to switch the junction to a more conductive state. Another aspect of the invention provides an SMM junction including a silver layer, a copper layer, and a molecular layer positioned between the silver layer and the copper layer. | 03-07-2013 |
20130063998 | SYSTEM AND MEMORY MODULE - A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip. | 03-14-2013 |
20130070508 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole. | 03-21-2013 |
20130070509 | MEMORY DEVICE HAVING DATA PATHS - Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus. | 03-21-2013 |
20130077374 | STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION - A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits. | 03-28-2013 |
20130083582 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130083583 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements. | 04-04-2013 |
20130083584 | STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE - A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe. | 04-04-2013 |
20130083585 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems for memory system are provided. In an example, a memory system can include a plurality of memory dice and an interface chip. The memory dice can include a first memory die including a memory array coupled to through wafer interconnects (TWIs) and a second memory die, wherein the first memory die is stacked over the second memory die. In an example, the interface chip can be coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice. In an example, the interface chip can be configured to perform DRAM sequencing. | 04-04-2013 |
20130088907 | TRANSISTOR CIRCUIT LAYOUT STRUCTURE - A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an independent second block, a bit line disposed on the source terminal and on the drain terminal or embedded in the substrate, a word line disposed on the first block, and a back line disposed on the second block. The horizontal level of the back line is different from that of the bit line and the word line. | 04-11-2013 |
20130094271 | CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION - A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation. | 04-18-2013 |
20130094272 | DEVICE - A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit. | 04-18-2013 |
20130094273 | 3D MEMORY AND DECODING TECHNOLOGIES - A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. | 04-18-2013 |
20130114323 | SEMICONDUCTOR DEVICE AND DATA STORAGE APPARATUS - A semiconductor device according to an embodiment includes: a rectangular substrate having a first and a second principal surfaces ; a first semiconductor chip; one or more second semiconductor chips; and one or more third semiconductor chips. The substrate has first connection terminals connected to electrodes of the one or more second semiconductor chips, and third connection terminals electrically connected to the first connection terminals and connected to first electrodes of the first semiconductor chip, on a side of a first edge on the first principal surface. The substrate has second connection terminals connected to second electrodes of the one or more third semiconductor chips, and fourth connection terminals electrically connected to the second connection terminals and connected to electrodes of the first semiconductor chip, on a side of a second edge facing the first edge across the first semiconductor chip on the first principal surface. | 05-09-2013 |
20130121054 | THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches to each of the n nanowire-junction memory elements and the second submicroscale subcomponent coupled through a second set of switches to each of the n nanowire-junction memory elements, the total number of switches in the first and second sets of switches less than 2n, and n greater than or equal to 2. | 05-16-2013 |
20130128648 | LAYOUTS FOR MEMORY AND LOGIC CIRCUITS IN A SYSTEM-ON-CHIP - An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits. | 05-23-2013 |
20130135917 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE - A method and apparatus for organizing memory for a computer system including a plurality of memory devices | 05-30-2013 |
20130148400 | MEMORY DEVICE - According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween. | 06-13-2013 |
20130148401 | SYSTEMS AND METHODS FOR STACKED SEMICONDUCTOR MEMORY DEVICES - Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board. | 06-13-2013 |
20130148402 | CONTROL SCHEME FOR 3D MEMORY IC - The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad. | 06-13-2013 |
20130148403 | MEMORY SYSTEM HAVING IMPROVED SIGNAL INTEGRITY - A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to- | 06-13-2013 |
20130155752 | WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP - Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip. | 06-20-2013 |
20130163303 | SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL WIRING STRUCTURE - Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. | 06-27-2013 |
20130170275 | DUAL PORT SRAM HAVING REDUCED CELL SIZE AND RECTANGULAR SHAPE - A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell. | 07-04-2013 |
20130176764 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a controller, a memory, a normal line, a test line, and a path setting unit. The normal line is provided for communication between the controller and the memory. The test line is provided for a test operation of the memory. The path setting unit connects either the normal line or the test line to the memory according to a type of access mode. | 07-11-2013 |
20130182484 | WORD LINE AND POWER CONDUCTOR WITHIN A METAL LAYER OF A MEMORY CELL - A memory cell | 07-18-2013 |
20130182485 | Data Storage and Stackable Configurations - A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices. | 07-18-2013 |
20130194854 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 08-01-2013 |
20130201744 | DMA ARCHITECTURE FOR NAND-TYPE FLASH MEMORY - A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits. | 08-08-2013 |
20130208524 | MEMORY MODULE FOR HIGH-SPEED OPERATIONS - A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes. | 08-15-2013 |
20130215660 | VARIABLE RESISTANCE MEMORY DEVICE HAVING EQUAL RESISTANCES BETWEEN SIGNAL PATHS REGARDLESS OF LOCATION OF MEMORY CELLS WITHIN THE MEMORY ARRAY - A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells. | 08-22-2013 |
20130223122 | MEMORY AND METHOD OF OPERATING THE SAME - The disclosure discloses a memory and a method of operating the same. The memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation. | 08-29-2013 |
20130223123 | MEMORY MODULE AND ON-DIE TERMINATION SETTING METHOD THEREOF - A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line. | 08-29-2013 |
20130229848 | MULTI-DIE DRAM BANKS ARRANGEMENT AND WIRING - A memory die for use in a multi-die stack having at least one other die. The memory die includes a plurality of contacts arranged in a field and configured to interface to the other dies of the multi-die stack. A first subset of the buffer lines of a number of buffer lines are connected to respective contacts in the field. The memory die also includes a number of buffers and cross-bar lines. The buffers are coupled between respective signal lines and respective buffer lines. The cross-bar lines interconnect respective pairs of buffer lines in a second subset of the buffer lines that is distinct from the first subset of the buffer lines. | 09-05-2013 |
20130235640 | SEMICONDUCTOR MEMORY AND METHOD OF MAKING THE SAME - A semiconductor memory includes a first bit cell within an integrated circuit (IC), and a second bit cell within the same IC. The first bit cell has a first layout, and the second bit cell has a second layout that differs from the first layout. | 09-12-2013 |
20130235641 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring. | 09-12-2013 |
20130250643 | MULTI-CHIP PACKAGE AND MEMORY SYSTEM - A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation. | 09-26-2013 |
20130250644 | CONTROL CIRCUIT BOARD, CONTROL SYSTEM, AND COPYING METHOD - A control circuit board includes a first storage unit configured to store therein predetermined data; a connecting unit configured to be connected to another control circuit board including a second storage unit; a switching unit configured to switch between a first state and a second state, the first state being a state in which data read from the first storage unit is enabled but data read from the second storage unit is disabled, the second state being a state in which data read from the first storage unit is disabled but data read from the second storage unit is enabled; and a storage control unit configured to write or read data to or from the first storage unit in the first state, and perform a copying operation that reads the data from the second storage unit and stores the read data in the first storage unit in the second state. | 09-26-2013 |
20130250645 | SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE - A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines. | 09-26-2013 |
20130258743 | MEMORY ARRAY WITH HIERARCHICAL BIT LINE STRUCTURE - A memory array includes a plurality of word lines extending along a first direction; a plurality of memory cells coupled to a first sub-bit line (SBL) extending along a second direction that is substantially orthogonal to the first direction; a first selector region disposed substantially in the middle of the first SBL thereby dividing the plurality of memory cells into two sub-groups, wherein the first selector region comprises at least one selector transistor that is coupled to the first SBL; and a main bit line (MBL) extending along the second direction and coupled to the selector transistor. | 10-03-2013 |
20130272047 | MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED - A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block. | 10-17-2013 |
20130272048 | SELF-DISABLING CHIP ENABLE INPUT - A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad. | 10-17-2013 |
20130272049 | STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS - Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element. | 10-17-2013 |
20130286707 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 10-31-2013 |
20130294133 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O circuit; and a path provider configured to select one of a direct path to a target internal circuit or an indirect path to the target internal circuit that is longer than the direct path in response to one or more path control signals and use the selected path when the data signal is transmitted between the I/O circuit and the plurality of internal circuits. | 11-07-2013 |
20130294134 | STACKED LAYER TYPE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1. | 11-07-2013 |
20130294135 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers. | 11-07-2013 |
20130308363 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH INTERLEAVED VERTICAL SELECT DEVICES ABOVE AND BELOW VERTICAL BIT LINES - A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines. | 11-21-2013 |
20130322147 | LEAKAGE AND PERFORMANCE GRADED MEMORY - Embodiments of the present invention provide a memory configuration on a chip containing multiple memory segments having different memory grades. In a typical embodiment, a single chip will be provided on which the memory segments are positioned. A memory grade may include low performance (low leakage), medium performance (medium leakage), and high performance (high leakage). Each memory segment or group of memory segments may have a separate power supply and/or controller. In one example, memory segments may be stacked in a through-silicon via configuration. | 12-05-2013 |
20130329480 | SRAM - The SRAM memory cell includes a metal wiring line having a titanium or tantalum film in a bottom layer, and a via having a tungsten plug. The via is arranged on the metal line following a layout rule which permits the misalignment. In arranging the upper-layer via with a tungsten plug on the metal line, one side of the via is disposed to be adjacent to one end of the metal line with a margin smaller than an alignment accuracy, and the lower-layer via is laid out far away from the end of the metal line as possible. The reduction in the yield, caused by the problem of the contact with the lower-layer via being broken or increased in resistance at occurrence of misalignment, can be suppressed. | 12-12-2013 |
20130329481 | SEMICONDUCTOR SYSTEM - A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 12-12-2013 |
20130329482 | HIGH BANDWIDTH MEMORY INTERFACE - A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device. | 12-12-2013 |
20140003114 | COMPACT SOCKET CONNECTION TO CROSS-POINT ARRAY | 01-02-2014 |
20140003115 | MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE | 01-02-2014 |
20140003116 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL STRUCTURED BIT LINES | 01-02-2014 |
20140009992 | ALTERNATIVE 3D STACKING SCHEME FOR DRAMS ATOP GPUS - Embodiments of the invention provide an integrated circuit system, which includes a first supporting substrate and a second supporting substrate, a logic chip disposed between the first supporting substrate and the second supporting substrate, and a plurality of memory stacks disposed adjacent to one another on a surface of the logic chip. The logic chip is separated from the first supporting substrate and the second supporting substrate by a distance such that at least a portion of a first memory stack in the plurality of memory stacks extending outwards past a first side edge of the logic chip is supported by the first supporting substrate, and at least a portion of a second memory stack in the plurality of memory stacks extending outwards past a second side edge of the logic chip that is opposite to the first side edge is supported by the second supporting substrate. | 01-09-2014 |
20140016389 | DRAM MEMORY CELLS RECONFIGURED TO PROVIDE BULK CAPACITANCE - A semiconductor device includes a Dynamic Random Access Memory (DRAM) memory array. The DRAM memory array includes a plurality of DRAM memory cells. Each of the DRAM memory cells includes a capacitor. Switching circuitry within the semiconductor device is configured to be switched to a state in which the switching circuitry connects capacitors of at least two of the DRAM memory cells together to provide a bulk capacitance between a first node and a second node. | 01-16-2014 |
20140016390 | LOGICAL MEMORY ARCHITECTURE, IN PARTICULAR FOR MRAM, PCRAM, OR RRAM - An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current. | 01-16-2014 |
20140036565 | MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY STRUCTURE - An exemplary memory device includes a substrate and two word lines extending on the substrate. The substrate includes an active area. The two word lines are formed on the active area. Each word line includes a recessed portion corresponding to the active area. The recessed portion is defined by a planar top surface. | 02-06-2014 |
20140036566 | Discrete Three-Dimensional Memory Comprising Dice with Different BEOL Structures - The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-M is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures, e.g. different number of BEOL layers, different number of interconnect layers, and/or different interconnect materials. | 02-06-2014 |
20140036567 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole. | 02-06-2014 |
20140043884 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data. | 02-13-2014 |
20140043885 | SEMICONDUCTOR DEVICE - In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other. | 02-13-2014 |
20140050004 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES - Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell. | 02-20-2014 |
20140056049 | MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES - Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described. | 02-27-2014 |
20140063888 | MEMORY ARRAY PLANE SELECT AND METHODS - Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material. | 03-06-2014 |
20140063889 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including first lines, second lines, and memory cells provided at each of intersections of the first lines and the second lines; and a control unit including a row control circuit, a first column control circuit provided on a side of one ends of the second lines, and a second column control circuit provided on a side of the other ends of the second lines, the control unit, during an access operation, controlling a potential of the first lines and the second lines such that a bias, which is lower than that applied to a certain unselected memory cell, is applied to those of unselected memory cells that are located more toward a center of the memory cell array in the column direction than the certain unselected memory cell. | 03-06-2014 |
20140063890 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform. | 03-06-2014 |
20140078804 | Mask Design With Optically Isolated Via and Proximity Correction Features - A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns. | 03-20-2014 |
20140085959 | 3D MEMORY CONFIGURABLE FOR PERFORMANCE AND POWER - A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays. | 03-27-2014 |
20140085960 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC DEVICE - A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines | 03-27-2014 |
20140092665 | SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates. | 04-03-2014 |
20140098589 | REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUIT - A memory interface circuit device comprising a data structure configured to match and substitute an address in a run-time. | 04-10-2014 |
20140098590 | VOLATILE MEMORY ACCESS VIA SHARED BITLINES - A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation. | 04-10-2014 |
20140104918 | INTERCONNECTION FOR MEMORY ELECTRODES - Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. | 04-17-2014 |
20140104919 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat. | 04-17-2014 |
20140112048 | N-BIT ROM CELL - Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a first ROM cell portion adjacent to or substantially contiguous with a second ROM cell portion. The first ROM cell portion is associated with a first data bit value. The second ROM cell portion is associated with a second data bit value distinct from the first data bit value. Because the first ROM cell portion is adjacent to the second ROM cell portion, OD-to-OD spacing between the twin-bit ROM cell and an adjacent twin-bit ROM cell is increased to provide, for example, improved isolation, cell current, ROM speed, and VCCmin performance in comparison with single-bit ROM cells, while maintaining a substantially similar to pitch as the single-bit ROM cells. | 04-24-2014 |
20140133210 | VARIABLE RESISTIVE ELEMENT, STORAGE DEVICE AND DRIVING METHOD THEREOF - An element according to an embodiment can transit between at least two states including a low-resistance state and a high-resistance state. The element comprises a first electrode, a second electrode, a first layer and a second layer. The first electrode includes metal elements. The first layer is located between the first electrode and the second electrode while contacting with the first electrode. The second layer is located between the first layer and the second electrode. At the low-resistance state, a density of the metal elements in the first layer is higher than that of the metal elements in the second layer. The density of the metal elements in the first layer at the low-resistance state is higher than that of the metal elements in the first layer at the high-resistance state. A relative permittivity of the second layer is higher than a relative permittivity of the first layer. | 05-15-2014 |
20140169057 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM HAVING THE SAME - A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address. | 06-19-2014 |
20140185352 | CONFIGURABLE-WIDTH MEMORY CHANNELS FOR STACKED MEMORY STRUCTURES - The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities. | 07-03-2014 |
20140185353 | MEMORY - A memory in accordance with an embodiment of the present invention may include a first page buffer, a second page buffer arranged adjacent to the first page buffer in a first direction, a global pad arranged between the first page buffer and the second page buffer, and a first bit line selection unit arranged adjacent to the first page buffer and the second page buffer in a second direction substantially perpendicular to the first direction, wherein a first bit line pad is formed at a center of the a first bit line selection unit. | 07-03-2014 |
20140185354 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 07-03-2014 |
20140192581 | PROGRAMMABLE AND FLEXIBLE REFERENCE CELL SELECTION METHOD FOR MEMORY DEVICES - Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells. | 07-10-2014 |
20140192582 | MEMORY STRUCTURE WITH REDUCED NUMBER OF REFLECTED SIGNALS - A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories. | 07-10-2014 |
20140192583 | CONFIGURABLE MEMORY CIRCUIT SYSTEM AND METHOD - A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.). | 07-10-2014 |
20140198553 | INTEGRATED CIRCUIT 3D PHASE CHANGE MEMORY ARRAY AND MANUFACTURING METHOD - A 3D phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers. An array of pillars extending through the plurality of conductive layers contact corresponding access devices. The phase memory material is between the pillars and conductive layers. Circuitry is configured to program data in the memory cells using programming pulses having shapes that depend on the resistance range of the cell before programming and the data values to be stored. | 07-17-2014 |
20140218998 | SEMICONDUCTOR PACKAGE - In a semiconductor package, a circuit pattern is arranged in a circuit board and contact pads on the circuit board are connected with the circuit pattern. Contact terminals contact external contact elements on a first surface of the circuit board. An integrated circuit (IC) chip structure is mounted on the circuit board and electrically connected to the inner circuit pattern. An operation controller on the circuit board controls operation of the semiconductor package according to the package users' individual choice. | 08-07-2014 |
20140218999 | SEMICONDUCTOR STORAGE DEVICE - With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines ( | 08-07-2014 |
20140233292 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 08-21-2014 |
20140233293 | PERMUTATIONAL MEMORY CELLS - Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the RCM cells. The memory cell material is capable of forming a conductive pathway between the electrical contacts with at least a portion of the memory cell material arranged to cross-couple a conductive pathway between select ones of the at least two electrical contacts electrically coupled to each of the at least two RCM cells. Additional apparatuses and methods are described. | 08-21-2014 |
20140241023 | Memory Elements and Cross Point Switches and Arrays for Same Using Nonvolatile Nanotube Blocks - Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals. | 08-28-2014 |
20140241024 | MULTI CHANNEL SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided. | 08-28-2014 |
20140241025 | DRAM CELL DESIGN WITH FOLDED DIGITLINE SENSE AMPLIFIER - The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F | 08-28-2014 |
20140247638 | DISTRIBUTED SEMICONDUCTOR DEVICE METHODS, APPARATUS, AND SYSTEMS - Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice. | 09-04-2014 |
20140254231 | 3D Non-Volatile Memory Having Low-Current Cells and Methods - A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described. | 09-11-2014 |
20140268973 | 276-PIN BUFFERED MEMORY CARD WITH ENHANCED MEMORY SYSTEM INTERCONNECT - An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals. | 09-18-2014 |
20140268974 | APPARATUSES AND METHODS FOR IMPROVING RETENTION PERFORMANCE OF HIERARCHICAL DIGIT LINES - Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit line portion and a second digit line portion. The apparatus may further include a first selector configured to selectively couple the first digit line portion to the second digit line portion based, at least in part, on a first control signal. The apparatus may further include a second selector configured to selectively couple the second digit line portion to a voltage based, at least in part, on a second control signal. | 09-18-2014 |
20140268975 | INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF - An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line. | 09-18-2014 |
20140268976 | GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT - A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network. | 09-18-2014 |
20140268977 | ELECTRICAL LINES WITH COUPLING EFFECTS - A circuit includes a first line, a second line, a first sub-circuit, and a second sub-circuit. The first line has a first signal. The second line has a second signal. The first sub-circuit is configured to generate a first output signal. The second sub-circuit is configured to generate a second output signal. The first output signal and the second output signal have coupling effects if the first signal and the second signal have coupling effects based on the first line and the second line. The first output signal and the second output signal do not have coupling effects if the first signal and the second signal do not have coupling effects. | 09-18-2014 |
20140268978 | SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC ACCESS TIME - A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays. | 09-18-2014 |
20140268979 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups. | 09-18-2014 |
20140286073 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line. | 09-25-2014 |
20140286074 | SYSTEM AND MEMORY MODULE - A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip. | 09-25-2014 |
20140293671 | Configurable Width Memory Modules - Describes is a memory system that utilizes motherboard traces in a way that permits maximum utilization of system data lines while accommodating varying numbers of memory modules. It is possible in a system such as this to utilize all individual sets of point-to-point signaling lines, even when less than all of the available memory sockets are occupied. Memory modules with configurable data widths support a relatively wide mode in which one module utilizes all available system data lines, or a relatively narrow mode in which multiple, narrower modules split the available system data lines between them. | 10-02-2014 |
20140301125 | PRINTED CIRCUIT BOARD AND MEMORY MODULE INCLUDING THE SAME - A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved. | 10-09-2014 |
20140301126 | Memory Arrays and Methods of Forming Electrical Contacts - Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays. | 10-09-2014 |
20140307498 | SEMICONDUCTOR MEMORY DEVICE INCLUDING FLAG CELLS - A semiconductor memory device includes a plurality of memory cells arranged in a row direction and a column direction, a plurality of word lines each connected to memory cells in a row among the memory cells, and a majority of bit lines each connected to memory cells in a column among the memory cells. One or more memory cells are distributed as flag cells among memory cells connected to each word line, and flag cells connected to a first word line and flag cells connected to a second word line that is disposed adjacent to the first word line among the word lines are connected to first and second bit lines, respectively. | 10-16-2014 |
20140313809 | SEMICONDUCTOR APPARATUS - A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block. | 10-23-2014 |
20140321188 | MEMORY DEVICES HAVING DATA LINES INCLUDED IN TOP AND BOTTOM CONDUCTIVE LINES - Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described. | 10-30-2014 |
20140321189 | Systems and Methods for Stacked Semiconductor Memory Devices - Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board. | 10-30-2014 |
20140328104 | SEMICONDUCTOR DEVICE - A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled. | 11-06-2014 |
20140328105 | METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING - Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed. | 11-06-2014 |
20140328106 | SEMICONDUCTOR MEMORY DEVICE - The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material. | 11-06-2014 |
20140334216 | General Structure for Computational Random Access Memory (CRAM) - A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements. | 11-13-2014 |
20140334217 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the gate of the first transistor; and a reference driver circuit configured to control the gate voltage of the second transistor. | 11-13-2014 |
20140334218 | SEMICONDUCTOR DEVICE - Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines. | 11-13-2014 |
20140355325 | Packaging of High Performance System Topology for NAND Memory Systems - A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package. | 12-04-2014 |
20140355326 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes: a plurality of first interconnects, and each of the first interconnects extending in a first direction; a plurality of second interconnects, and each of the second interconnects extending in a second direction intersecting with the first direction; a memory cell connected between each of the plurality of first interconnects and each of the plurality of second interconnects, the memory cell including a memory layer and a diode connected to the memory layer; and a control circuit capable of selecting a selection first interconnect among the first interconnects, selecting a selection second interconnect among the second interconnects, and selecting a selection memory cell connected to both the selection first interconnect and the selection second interconnect. | 12-04-2014 |
20140362630 | METHOD FOR IMPROVING BANDWIDTH IN STACKED MEMORY DEVICES - Apparatus and methods of increasing the data rate and bandwidth of system memory including stacked memory device dice. The system memory includes a memory device having a plurality of memory device dice in a stacked configuration, a memory controller coupled to the stacked memory device dice, and a partitioned data bus. The memory device dice each include one, two, or more groups of memory banks. By configuring each memory device die to deliver all of its bandwidth over a different single partition of the data channel, the system memory can achieve an increased data rate and bandwidth without significantly increasing costs over typical system memory configurations that include stacked memory device dice. | 12-11-2014 |
20140369104 | MEMORY DEVICE - According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween. | 12-18-2014 |
20150009740 | LATENCY ADJUSTMENT BASED ON STACK POSITION IDENTIFIER IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 01-08-2015 |
20150009741 | VALID COMMAND DETECTION BASED ON STACK POSITION IDENTIFIERS IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 01-08-2015 |
20150029775 | MEMORY CELL ARRAY STRUCTURES AND METHODS OF FORMING THE SAME - The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure. | 01-29-2015 |
20150036407 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes a memory cell array and a coil provided closely to the memory cell array. The memory cell array includes memory cells provided above an underlying layer, and a first interconnection. The memory cells are aligned in a first direction perpendicular to the underlying layer. The first interconnection extends in a second direction perpendicular to the first direction. The coil includes a winding including a second interconnection extending in the second direction and sharing a central axis with the first interconnection, a first plug extending in the first direction and connected to the second interconnection, a third interconnection electrically connected to another end of the first plug and extending in a direction parallel to the underlying layer, and a second plug having one end electrically connected to the third interconnection, and extending in a direction opposite to the first direction. | 02-05-2015 |
20150036408 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE - A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability. | 02-05-2015 |
20150055391 | DESIGNATED MEMORY SUB-CHANNELS FOR COMPUTING SYSTEMS AND ENVIRONMENTS - A memory channel can be divided into two or more memory sub-channels, wherein each one of the memory sub-channels includes two or more memory components configured to store data made accessible on that memory sub-channel, and wherein the two or more memory components in each one of the memory sub-channels are respectively connected via at least one transmission line and can be individually accessed (addressed) on their associated sub-channel. | 02-26-2015 |
20150055392 | Memory Device Having Sequentially Cascading Dices - A memory device is provided. The memory device is used for data transmission at around 1600 megahertz (MHz). A wire layout is used to sequentially cascade memory dices with greatly shortened distances between the wire layout and the memory dices. At the same time, distances between the wire layout and UA controllers are shortened as well for effectively simplifying the design of wires. | 02-26-2015 |
20150055393 | Semiconductor Device Having Multi-Level Wiring Structure - Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. | 02-26-2015 |
20150062993 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a non-volatile memory device includes a first wiring provided on an underlayer, a first memory cell array provided on the first wiring and including a plurality of memory cells, a first select element including a first control electrode provided between the first wiring and the first memory cell array. The device also includes a second wiring provided at the same level as the first wiring and electrically connected to the first control electrode, and a first plug electrically connecting the first control electrode and the second wiring, one end of the first plug being in contact with the second wiring, and a side surface of the first plug being in contact with the first control electrode. | 03-05-2015 |
20150070959 | MEMORY PACKAGE WITH OPTIMIZED DRIVER LOAD AND METHOD OF OPERATION - An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect. | 03-12-2015 |
20150070960 | INTERCONNECTION FOR MEMORY ELECTRODES - Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. | 03-12-2015 |
20150078057 | HIGH BANDWIDTH MEMORY INTERFACE - A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device. | 03-19-2015 |
20150098261 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step. | 04-09-2015 |
20150109844 | INTEGRATED CIRCUIT AND OPERATING METHOD FOR THE SAME - An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis. | 04-23-2015 |
20150109845 | SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 04-23-2015 |
20150117080 | MULTI-CHIP PACKAGE AND MEMORY SYSTEM - A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation. | 04-30-2015 |
20150124510 | SEMICONDUCTOR DEVICE WITH MORE THAN ONE TYPE OF MEMORY CELL - A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device further comprises a plurality of memory cells. At least one memory cell of the plurality of memory cells is at an intersection of the word line and a bit line of the plurality of bit lines. The at least one memory cell of the plurality of memory cells is a type selected from at least two memory cell types based on a distance of the intersection from an end of the word line. | 05-07-2015 |
20150131357 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; amounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory. | 05-14-2015 |
20150318025 | MEMORY DEVICE WITH REDUCED OPERATING CURRENT - A memory device may including a first local bit line electrically connected with a first memory cell, a first global bit line electrically connected with the first local bit line, a second local bit line electrically connected with a second memory cell, and a second global bit line electrically connected with the second local bit line. The first global bit line is primarily charged with electric charge. The first global bit line and the second global bit line share the primarily charged electric charge. The second global bit line is secondarily charged with the electric charge. | 11-05-2015 |
20150332740 | APPARATUSES AND METHODS FOR ACCESSING MEMORY INCLUDING SENSE AMPLIFIER SECTIONS AND COUPLED SOURCES - Apparatuses and methods for accessing memory are described. An example method includes accessing memory cells of a memory section, and sharing a source of an inactive sense amplifier section with an active sense amplifier section coupled to the memory cells of the memory section during a memory access operation to the memory section coupled to the active sense amplifier section. An example apparatus includes a memory section and a first sense amplifier section associated with the memory section. The first sense amplifier section includes a sense amplifier and includes a read/write circuit coupled to a first source associated with the first sense amplifier section. The source associated with the first sense amplifier section is coupled to a source associated with a second sense amplifier section. The second sense amplifier section is configured to be inactive during a memory access operation to the memory section. | 11-19-2015 |
20150348597 | CIRCUIT, METHOD OF USING THE CIRCUIT AND MEMORY MACRO INCLUDING THE CIRCUIT - A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal. | 12-03-2015 |
20150357034 | INTERCONNECTION ARCHITECTURE FOR MULTILAYER CIRCUITS - A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided. | 12-10-2015 |
20150364186 | RRAM MEMORY DEVICE AND METHOD THEREOF - A resistive random-access memory (RRAM) device and a method thereof are disclosed. The RRAM device is contains a plurality of bit cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. Each bit cell includes a transistor and resistive element, the transistor includes a gate, a source and a drain, and the resistive element is coupled to the drain of the transistor. The plurality of word lines are arranged in parallel to one another, and coupled to respective gates of the transistors. The plurality of bit lines are arranged in parallel to one another and being intersected with the plurality of word lines, and coupled to respective drains of the transistors through the resistive elements. The plurality of source lines are arranged in parallel to one another and the plurality of bit lines. | 12-17-2015 |
20160027479 | SEMICONDUCTOR MEMORY - Semiconductor memories are provided. The Semiconductor memory includes a plurality of sense amplifiers, plurality sets of master data line segments and a plurality of memory segments. The plurality sets of master data line segments are arranged in a column direction. Each memory segment includes a plurality of memory cells, and is coupled to a set of corresponding master data line segments via a corresponding sense amplifier. Adjacent sets of corresponding master data line segments are coupled together. When accessing memory data, the memory data are transferred by the adjacent sets of corresponding master data line segments which are coupled together. | 01-28-2016 |
20160027509 | MEMOIRE NON VOLATILE A RESISTANCE PROGRAMMABLE - A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell. | 01-28-2016 |
20160035402 | UNIT ARRAY OF A MEMORY DEVICE, MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a memory array including a plurality of sections, each including a plurality of memory cells and at least one reference cell. The memory device may also include a plurality of sense amplifier circuits respectively corresponding to the plurality of sections, and a plurality of switch circuits, each switch circuit connected between a respective section and sense amplifier circuit. Each switch circuit may be configured to select between communicatively connecting a first column of memory cells or a reference cell to a corresponding sense amplifier. | 02-04-2016 |
20160049195 | RESISTIVE CROSS-POINT ARCHITECTURE FOR ROBUST DATA REPRESENTATION WITH ARBITRARY PRECISION - This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network. | 02-18-2016 |
20160078931 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a first wiring line extending in a first direction, a second wiring line extending in a first direction, the first wiring line and the second wiring line being separated from each other, a third wiring line separated from the first wiring line and the second wiring line, at least one portion of the third wiring line extending in a second direction crossing the first direction, a fourth wiring line separated from the first wiring line and the second wiring line, at least one portion of the fourth wiring line extending in the second direction, a first interconnect connected between a side surface of the first wiring line and a side surface of the third wiring line, and a second interconnect connected between a side surface of the second wiring line and a side surface of fourth wiring line. | 03-17-2016 |
20160093341 | MEMORY DEVICE WITH SHARED AMPLIFIER CIRCUITRY - In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry. | 03-31-2016 |
20160099034 | I/O PIN CAPACITANCE REDUCTION USING TSVS - Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance. | 04-07-2016 |
20160118116 | FAST READ SPEED MEMORY DEVICE - A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations. | 04-28-2016 |
20160125961 | Semiconductor Device Having Hierarchically Structured Bit Lines - Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell. | 05-05-2016 |
20160133603 | STACK MEMORY - A semiconductor memory is formed by stacking a plurality of substrates and memory cells on each substrate are connected by data dump lines. A switch may intervene between the memory cell and the data dump line. When data of each substrate is dumped by the data dump line, a problem of decrease in a speed and an increase in power consumption due to a parasitic component can be minimized. Further, a core circuit including the memory cell may be disposed on one substrate and a peripheral circuit unit may be disposed on the remaining substrates. | 05-12-2016 |
20160148686 | MEMORY CELL ARRAY OF RESISTIVE RANDOM-ACCESS MEMORIES - A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line. | 05-26-2016 |
20160172021 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING MEMORY DEVICE | 06-16-2016 |
20160180929 | Variable Resistance Memory Device | 06-23-2016 |
20160196875 | DEVICE AND METHOD FOR FORMING RESISTIVE RANDOM ACCESS MEMORY CELL | 07-07-2016 |
20160196876 | RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME | 07-07-2016 |
20160203847 | MEMORY CIRCUIT AND LAYOUT STRUCTURE OF A MEMORY CIRCUIT | 07-14-2016 |
20160203852 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE | 07-14-2016 |
20160203866 | SEMICONDUCTOR INTEGRATED CIRCUIT | 07-14-2016 |
20160379707 | CROSS POINT MEMORY DEVICE - Provided is a cross-point memory device including multiple word lines arranged in parallel with each other, multiple bit lines arranged to be orthogonal to the word lines and parallel with each other, and multiple cross-point memory cells electrically connected between the word lines and the bit lines, respectively. Herein, a cross-sectional area of a cross-section perpendicular to a longitudinal direction of the bit lines is formed to be increased as being farther from a first end of the bit lines. | 12-29-2016 |
20170236564 | DATA GATHERING IN MEMORY | 08-17-2017 |