Entries |
Document | Title | Date |
20080219053 | PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY - A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations. | 09-11-2008 |
20080225592 | Nonvolatile semiconductor memory device - With this flash memory, because a plurality of memory blocks are formed on a surface of a single P-type well, a layout area can be made small. Further, when erasing data for a memory block to be erased, a voltage of the P-type well is applied to all word lines of a memory block to be not erased. Consequently, the voltage of the P-type well and the voltage of all word lines of the memory block to be not erased change at the same time. With this, it is possible to prevent a threshold voltage for the memory block to be not erased from changing. | 09-18-2008 |
20080239810 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line. | 10-02-2008 |
20080239811 | METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR STORAGE SYSTEM - A semiconductor storage system includes a first memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing n bits data, the block is a minimum unit which is capable of being independently erased, a second memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing m (m>n: m is integer) bits data, the block is a minimum unit which is capable of being independently erased, and a controller which controls a number of rewrites for the block in the first memory region not to be more than a first predetermined number of times, and controls a number of rewrites for the block in the second memory region not to be more than a second predetermined number of times. | 10-02-2008 |
20080247233 | NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE - A nonvolatile memory device which can reduce consumption current and shorten access time and a control method thereof is provided. The nonvolatile memory device | 10-09-2008 |
20080253184 | NON VOLATILE MEMORY - An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation. | 10-16-2008 |
20080266958 | FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells. | 10-30-2008 |
20080266959 | MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS - A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells. | 10-30-2008 |
20080279005 | MANAGING FLASH MEMORY PROGRAM AND ERASE CYCLES IN THE TIME DOMAIN - A memory management component can track the amount of time between erase cycles for a particular memory region, and can manage memory region such that the regions are given sufficient time to rest and recover, or are given at least as much rest time as is practical, before being subject to an erase cycle. A reclamation management component can reclaim memory region that have invalid data stored therein, and can reclaim regions on a just-in-time basis when practical, and can determine which regions to reclaim based on various factors, such as the amount of time since a region was last erased, and the number of programming errors associated with a region. The memory management component can thereby optimize the useful life, minimize or reduce loss of margin in memory regions, and minimize or reduce programming errors of memory regions, of non-volatile (e.g., flash) memory. | 11-13-2008 |
20080279006 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRIC POWER SUPPLY METHOD - A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word and bit lines connected to the memory cells; a data program and read control section including a plurality of decoders for, when performing data programming, read or erasure with respect to a corresponding memory cell, selecting, and applying a voltage to corresponding word and bit lines; and a power supply circuit for supplying power to the data program and read control section; wherein when the power supply circuit is to supply power to the second memory cell array, an output terminal of the power supply circuit is electrically connected to at least one of the decoders connected to the first memory cell array. | 11-13-2008 |
20080291730 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial V | 11-27-2008 |
20080310229 | SEMICONDUCTOR MEMORY DEVICE IN WHICH WORD LINES ARE DRIVEN FROM EITHER SIDE OF MEMORY CELL ARRAY - A semiconductor memory device includes a memory cell array, a first row decoder which drives the memory cell array, and a second row decoder which drives the memory cell array. The first and second row decoders simultaneously drive the memory cell array. | 12-18-2008 |
20080310230 | Flash Memory Devices Having Three Dimensional Stack Structures and Methods of Driving Same - Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled. | 12-18-2008 |
20080316823 | STORAGE DEVICE AND CIRCUIT ELEMENT SWITCHING METHOD THEREOF - The present invention discloses a storage device and a circuit element switching method thereof. The storage device includes: a plurality of memory modules, wherein each of the plurality of memory modules includes a plurality of chip enable terminals; a memory control unit that includes a plurality of bank selection terminals; and a switch module that is coupled between the plurality of memory modules and the memory control unit, and utilized for dispersedly coupling the plurality of bank selection terminals to the plurality of chip enable terminals of each of the plurality of memory modules. The circuit element switching method applied to the storage device includes: providing a memory control unit including a plurality of bank selection terminals; and dispersedly coupling the plurality of bank selection terminals to a plurality of chip enable terminals of each of the plurality of memory modules. | 12-25-2008 |
20080316824 | Non-volatile memory device and method of operating the same - Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell. | 12-25-2008 |
20080316825 | SEMICONDUCTOR MEMORY DEVICE - An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal. | 12-25-2008 |
20090003065 | Flash cell with improved program disturb - Memory cells, memory arrays, memory devices and methods are disclosed, such as those involving a memory cell comprising a floating gate comprising lightly doped polysilicon, wherein the lightly doped polysilicon has a substantially uniform doping concentration. One such memory cell further comprises a control gate and dielectric disposed between the floating gate and the control gate. | 01-01-2009 |
20090034333 | Method for Managing a Non-Volatile Memory In a Smart Card - The invention concerns a method for managing access to a non-volatile memory (VNVM), characterized in that said non-volatile memory (VNVM) results from the association of a non-volatile memory of a first type (NVMA) comprising first characteristics of capacity and granularity, with a non-volatile memory of a second type (NVMB) comprising second characteristics of capacity and granularity, such that said non-volatile memory (VNVM) resulting from said association has the characteristics of capacity of said non-volatile memory of the first type and the characteristics of granularity of said non-volatile memory of the second type. | 02-05-2009 |
20090034334 | NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS - A nonvolatile memory device | 02-05-2009 |
20090040828 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second memory cell blocks, a block decoder, and first and second block switches. The first and second memory cell blocks have a plurality of memory cells connected in a string structure and are respectively disposed in neighboring planes. The block decoder outputs first and second block select signals in response to pre-decoded address signals and first and second plane select signals, which are respectively enabled according to an enable state of the planes. The first and second block switches connect global word lines to word lines of the first and second memory cell blocks in response to the first and second block select signals, respectively. | 02-12-2009 |
20090046513 | Enhanced erase for flash storage device - A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used subsequent to the erase. A flash controller interface receives a command for erasing the flash storage device and provides an erase command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides an erase command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other and the erase operations overlap. Subsequent to the erase, certain control data is reconstructed to allow subsequent use of the flash storage device. | 02-19-2009 |
20090059666 | MEMORY CELL ARRAY AND NON-VOLATILE MEMORY DEVICE - A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell arrays, and each of the sub-memory banks includes multiple physical sectors. The sense amplifiers are dedicated to the sub-memory banks, respectively. | 03-05-2009 |
20090059667 | MEMORY CELL ARRAY AND NON-VOLATILE MEMORY DEVICE - A memory cell array is disclosed which includes a plurality of memory banks, each memory bank including a plurality of logical sectors. The memory cell array includes a plurality of sub-memory banks, wherein each one of the plurality of sub-memory banks includes a plurality of physical sectors, and each one of the plurality of physical sectors is part of one of the plurality of logical sectors, and a plurality of sense amplifiers respectively associated with the plurality of sub-memory banks. | 03-05-2009 |
20090067242 | PROGRAMMING METHOD OF FLASH MEMORY DEVICE - A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines. | 03-12-2009 |
20090067243 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to respectively correspond to the bit lines and reading data stored in the memory cells; and bit line drivers provided to the bit lines and operating the bit lines when data is written to the memory cells, wherein the bit line drivers access the memory cells adjacent to a first memory cell diagonally with respect to the form of the lattice for writing the data to the adjacent memory cells during a data write operation without changing data stored in the memory cells adjacent to the first memory cell in the first and the second directions. | 03-12-2009 |
20090073768 | MEMORY WITH OUTPUT CONTROL - An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. | 03-19-2009 |
20090080256 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD - Provided are a flash memory device and method of controlling certain program operation voltages. The flash memory device includes a high voltage generation circuit providing a high voltage to a block selection circuit and a program voltage to a row decoder. The high voltage generation circuit includes a charge pump, a high voltage control circuit controlling the charge pump to provide the high voltage, and a program voltage control circuit providing the program voltage in relation to the high voltage, wherein the high voltage control circuit and the program voltage control circuit operate in response to the same control code. | 03-26-2009 |
20090091980 | SEMICONDUCTOR INTEGRATED CIRCUIT - In the semiconductor integrated circuit incorporating non-volatile memory that is not electrically rewritable, updating stored data and reusing the non-volatile memory are made possible. The data stored in the non-volatile memory can be updated and the non-volatile memory can be reused by dividing the non-volatile memory into a plurality of blocks and replacing a used block with an unused block. When data “1” is set in the first flag of a certain block, a block selection circuit judges that data is already written in the block and rewriting new data into the block is not possible. To update the stored data, the updated data is written into a block that is selected by the block selection circuit out of the rest of the blocks. At that time, the first flag of the block is set to data “1”. Stored data is updated one after another as described above. When data of final update is written into a certain block, the second flag of the block is set to data “1”. | 04-09-2009 |
20090109754 | NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES - In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines. | 04-30-2009 |
20090109755 | Neighbor block refresh for non-volatile memory - Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation are disclosed. The effects of word line disturb (gate disturb) may thereby be reduced. | 04-30-2009 |
20090116285 | NONVOLATILE MEMORY DEVICE AND READING METHOD THEREOF - A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including first and second select transistors and a plurality of memory cells, a plurality of sub bit lines commonly connected to the respective cell strings in same group, the cell blocks being grouped into a plurality of groups whose number is identical to or smaller than the number of the cell blocks, a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group, and a plurality of page buffers configured to sense data of the memory cells through the main bit lines. | 05-07-2009 |
20090122611 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines. | 05-14-2009 |
20090147582 | Adjusting program and erase voltages in a memory device - There is provided a method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string. | 06-11-2009 |
20090154243 | NAND-TYPE FLASH MEMORY AND SEMICONDUCTOR MEMORY DEVICE - A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit. | 06-18-2009 |
20090154244 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line for programming data; a word line selection circuit which selects a word line among the plurality of word lines which is connected to a memory cell to be programmed with data; a voltage application circuit which applies a programming voltage to the selected word line according to the parameter; a verify circuit which performs verification of programmed data; a control part which outputs a signal for selecting a word line and repeats the operations of the voltage application circuit until the verification is successful; a calculation circuit which calculates an average value of the number of times the control part repeats the operations of the voltage application circuit per each word line; and a parameter setting circuit which sets the parameter using the average value calculated. | 06-18-2009 |
20090154245 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes: a memory cell array in which electrically rewritable nonvolatile memory cells are arranged; and a register that holds good/bad information on a specific area that requires high reliability in a user accessible area of the memory cell array. An address conversion circuit internally accesses, when the specific area is bad and is accessed, a backup area in the user accessible area based on the good/bad information in the register. When the specific area is bad and the backup area is accessed, on the other hand, the address conversion circuit internally accesses the specific area based on the good/bad information in the register. | 06-18-2009 |
20090161432 | FLASH MEMORY DEVICE AND OPERATING METHOD THEREOF - A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor. The control unit generates a block select signal in response to an address signal and generates an operation control signal in response to a command signal. The program speed calculation unit decides a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells. The voltage generator generates operating voltages including the initial program voltage of the level according to the operation control signal. The block select unit transfers the operating voltages to a memory cell block corresponding to the block select signal. | 06-25-2009 |
20090168525 | Flash memory controller having reduced pinout - Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller. | 07-02-2009 |
20090168526 | FLASH MEMORY DEVICE HAVING DUMMY CELL - A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells. | 07-02-2009 |
20090175081 | NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES - A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost. | 07-09-2009 |
20090175082 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 07-09-2009 |
20090185422 | Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods - A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit. | 07-23-2009 |
20090190403 | Flash Memory Devices and Erasing Methods Thereof - Disclosed is an erasing method for a flash memory device that includes erasing memory cells of a selected memory block and post-programming the erased memory cells to have a threshold voltage distribution with the lowest level that is at or near 0V. The post-programming includes first post-programming the memory block in the unit of memory block and second post-programming the memory block in the unit of word line. | 07-30-2009 |
20090196102 | FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES - A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. | 08-06-2009 |
20090201733 | FLASH MEMORY DEVICE - A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and define memory block pairs. The flash memory device can further include a row selection circuit that is configured to drive the word lines responsive to memory operations associated with a memory address, where the row selection circuit can include respective shield lines that are located between the memory blocks included in each pair and each of the memory blocks in the pair has a common source line therebetween. | 08-13-2009 |
20090201734 | Verified purge for flash storage device - A flash storage device includes flash storage units that are purged in response to a condition or command wherein, during or subsequent to the purge, the purge is verified. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command such that the flash storage units are erased substantially in parallel with each other. The purge of the flash storage device is subsequently verified. | 08-13-2009 |
20090231918 | INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM - An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank. | 09-17-2009 |
20090244975 | FLASH MEMORY DEVICE AND BLOCK SELECTION CIRCUIT THEREOF - The present invention relates to a block selection circuit of a flash memory device. The block selection circuit includes a control signal output unit, switching means, and an operation controller. The control signal output unit outputs a control signal for enabling or disabling memory blocks connected thereto by employing block address signals. The block address signals are decoded according to an input address and provided. The switching means switches the control signal so that the control signal is input as a block selection control signal. The operation controller turns off drain and source select transistors of a memory block connected thereto according to a logic level of a first control signal. | 10-01-2009 |
20090244976 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time. | 10-01-2009 |
20090257278 | FLASH MEMORY DEVICE HAVING SHARED ROW DECODER - A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage. | 10-15-2009 |
20090268521 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded. | 10-29-2009 |
20090268522 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 10-29-2009 |
20090268523 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 10-29-2009 |
20090268524 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit. | 10-29-2009 |
20090273977 | MULTILAYERED NONVOLATILE MEMORY WITH ADAPTIVE CONTROL - A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix, and the control parameters for each group are responsive to the stored characteristics for that group; the method including organizing memory cells into groups, storing characteristics for each group in a look-up matrix, providing control parameters for each of the groups, where the control parameters for each group are responsive to its stored characteristics, and driving each memory cell in accordance with its provided control parameters. | 11-05-2009 |
20090279358 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor device includes: a first sector ( | 11-12-2009 |
20090290419 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 11-26-2009 |
20090296471 | MEMORY CELL OPERATION - Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells. | 12-03-2009 |
20090296472 | FLASH MEMORY DEVICES AND METHODS OF PROGRAMMING THE SAME BY OVERLAPPING PROGRAMMING OPERATIONS FOR MULTIPLE MATS - A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat. | 12-03-2009 |
20090310411 | Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS - An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices. | 12-17-2009 |
20090310412 | METHODS OF DATA MANAGEMENT IN NON-VOLATILE MEMORY DEVICES AND RELATED NON-VOLATILE MEMORY SYSTEMS - A data management method includes assigning data buffered in a first memory device into at least two different groups for transfer to a second memory device. At least one of the different groups has at least two units of the data assigned thereto. The data is transferred from the first memory device to the second memory device in a sequence according to a respective priority associated with each of the different groups and in group-by-group manner such that units of the data assigned to a group having a higher priority are transferred to the second memory device prior to units of the data assigned to a group having a lower priority. Related systems and methods are also discussed. | 12-17-2009 |
20090323419 | READ-TIME WEAR-LEVELING METHOD IN STORAGE SYSTEM USING FLASH MEMORY DEVICE - Disclosed is a read-time wear-leveling method in a storage system using a flash memory device, in which the abrasion of the flash memory device generated by repeated read operations is dispersed over the entire region so that the abrasion of memory blocks can be equalized to prolong the life of the flash memory device, to minimize errors in the memory blocks, and to secure the reliability of the storage system. | 12-31-2009 |
20100020614 | Non-Volatile Memory With Linear Estimation of Initial Programming Voltage - In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be used to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages. | 01-28-2010 |
20100027337 | Nonvolatile memory device extracting parameters and nonvolatile memory system including the same - The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one the memory block, and configured to store the varied parameter into the memory cell array in accordance with a result of the detection, wherein the control logic circuit is configured to utilize the varied parameter, which is stored in the memory cell array, while accessing the at least one memory block. | 02-04-2010 |
20100027338 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block. | 02-04-2010 |
20100034021 | METHOD OF CONTROLLING OPERATION OF FLASH MEMORY DEVICE - According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference block. In order to check an operating characteristic of the reference block, a threshold voltage level of the programmed memory cell is read. Parameters for performing an operation of the flash memory device are determined based on the operating characteristic of the reference block. The parameters are stored in the reference block. | 02-11-2010 |
20100039860 | MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE - Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells. | 02-18-2010 |
20100039861 | NONVOLATILE MEMORY DEVICE AND READ METHOD - Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines. | 02-18-2010 |
20100046293 | MEMORY CELL BLOCK OF NONVOLATILE MEMORY DEVICE AND METHOD OF MANAGING SUPPLEMENTARY INFORMATION - A nonvolatile memory device of a nonvolatile memory device includes a memory cell unit comprising sets of memory cells, a first supplementary information repository comprising source-side dummy cells respectively connected between source select transistors and first memory cells of the sets of the memory cells, and a second supplementary information repository comprising drain-side dummy cells respectively connected between drain select transistors and second memory cells of the sets of the memory cells. | 02-25-2010 |
20100067297 | BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE - A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit. | 03-18-2010 |
20100067298 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 03-18-2010 |
20100085810 | METHOD OF CONTROLLING MEMORY SYSTEM - A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the second block in the first block. The control unit is configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block. | 04-08-2010 |
20100091569 | METHODS OF FORMING FLASH DEVICE WITH SHARED WORD LINES - Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates. | 04-15-2010 |
20100091570 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 04-15-2010 |
20100097860 | NAND FLASH MEMORY - A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage. | 04-22-2010 |
20100103738 | MEMORY AND OPERATING METHOD THEREOF - A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined whether there is an empty manufacture-defined block among a number of user-defined blocks in the memory. If so, an information block in the memory is programmed to store the programming address and a replacing address pointing to the empty manufacture-defined block. The empty manufacture-defined block is programmed to store the programming data. | 04-29-2010 |
20100103739 | MEMORY CONFIGURATION OF A COMPOSITE MEMORY DEVICE - The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access. | 04-29-2010 |
20100118608 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME - A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit. | 05-13-2010 |
20100124115 | PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache is comprised of dual SDC, PDC, DDC | 05-20-2010 |
20100124116 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings. | 05-20-2010 |
20100124117 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell. | 05-20-2010 |
20100128532 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - A nonvolatile memory device includes; a memory cell array configured into a plurality of memory blocks, a decoder connected to the plurality of memory blocks via a word line, a page buffer connected to the plurality of memory blocks via a bit line, and control logic configured to define a control voltage applied to at least one of the word line and the bit line during a program/verify operation in accordance with a location of each one of the plurality of memory blocks within the memory cell array. | 05-27-2010 |
20100142276 | NONVOLATILE MEMORY - A nonvolatile memory includes a memory cell allay including a plurality of memory cells, each of the memory cells capable of storing electric charges nonvolatilly, a first sense amplifier for comparing a voltage produced by one of the selected memory cells to be read out with a first threshold value for distinguishing between a write state and an erase state of the selected memory cell, a second sense amplifier for comparing the voltage produced by one of the selected memory cell with a second threshold value having a greater voltage than the first threshold voltage, and a write unit for rewriting data of the selected memory cell when the first and the second sense amplifiers produce different sense outputs from each other. | 06-10-2010 |
20100149875 | Nonvolatile Semiconductor Memory Device - The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines. | 06-17-2010 |
20100157676 | NAND FLASH MEMORY - A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state. | 06-24-2010 |
20100165732 | FLASH MEMORY APPARATUS AND READ OPERATION CONTROL METHOD THEREFOR - A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each block of the plurality of blocks. | 07-01-2010 |
20100182834 | TWISTED DATA LINES TO AVOID OVER-ERASE CELL RESULT COUPLING TO NORMAL CELL RESULT - Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers. | 07-22-2010 |
20100182835 | BLOCK DECODER OF FLASH MEMORY DEVICE - A block decoder of a flash memory device includes a discharge control unit configured to output a discharge signal in response to a program precharge signal and one or more of a number of address signals, and a selection line control unit configured to apply a ground voltage to source and drain selection lines of memory blocks in response to the discharge signal. | 07-22-2010 |
20100182836 | Nonvolatile memory having plurality of memory blocks each including data storage area and discrimination area - A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing. | 07-22-2010 |
20100214838 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer. | 08-26-2010 |
20100226179 | NAND FLASH ARCHITECTURE WITH MULTI-LEVEL ROW DECODING - A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector. | 09-09-2010 |
20100238729 | NON-VOLATILE MEMORY WITH REDUCED LEAKAGE CURRENT FOR UNSELECTED BLOCKS AND METHOD FOR OPERATING SAME - A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block. | 09-23-2010 |
20100246265 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 09-30-2010 |
20100246266 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block. | 09-30-2010 |
20100284223 | NONVOLATILE SEMICONDUCTOR MEMORY - The invention decreases the number of writing processes of EEPROM. When a mode change signal is L level, a EEPROM is set to a bank mode. In this case, first and second memory banks are independently accessed by a control signal of a first port and a control signal of a second port, respectively. When the mode change signal is H level, the EEPROM is set to a combine mode. In this case, the first and second memory banks are combined into a 4k-bit memory bank, and accessed by the control signal of the first port. | 11-11-2010 |
20100284224 | FLASH MEMORY DEVICE AND ERASE METHOD USING THE SAME - A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated in response to the block control signals. | 11-11-2010 |
20100290287 | METHOD CIRCUIT AND SYSTEM FOR OPERATING AN ARRAY OF NON-VOLATILE MEMORY ("NVM") CELLS AND A CORRESPONDING NVM DEVICE - Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset values, and to maintain a read error count. | 11-18-2010 |
20100309724 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 12-09-2010 |
20100315874 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 12-16-2010 |
20100322003 | INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM - An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank. | 12-23-2010 |
20110002171 | MEMORY WITH OUTPUT CONTROL - An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. | 01-06-2011 |
20110013454 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line. | 01-20-2011 |
20110019475 | INTERLEAVED FLASH STORAGE SYSTEM AND METHOD - A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer. | 01-27-2011 |
20110019476 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile memory device is provided which includes a plurality of memory blocks, a bias block and a control logic block. The memory blocks are formed in wells, respectively. The bias block biases a well of a selected memory block. The control logic block controls the bias block to pre-charge doping regions of the selected memory block to a junction voltage before word line voltages are applied to the selected memory block in a programming operation. | 01-27-2011 |
20110019477 | NAND TYPE FLASH MEMORY - According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block. | 01-27-2011 |
20110051515 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 03-03-2011 |
20110058421 | Systems and Methods for Peak Power and/or EMI Reduction - Various embodiments of the present invention provide systems, methods and circuits for power management and/or EMI reduction. As one example, a method for memory system access is disclosed that includes providing a first bank of memory; providing a second bank of memory; receiving a memory access request that includes assertion of a reference memory clock; accessing the first bank of memory using a first sub memory clock asserted relative to the reference memory clock; delaying a phase offset; and accessing the second bank of memory using a second sub memory clock asserted the phase offset after assertion of the first sub memory clock. | 03-10-2011 |
20110058422 | Systems and Methods for Circular Buffering Control in a Memory Device - circuits for memories and utilization thereof. As one example, memory devices are disclosed that include a plurality of non-volatile memory blocks, and a memory write circuit. The memory write circuit is operable to write subsets of the plurality of non-volatile memory blocks at locations identified by a pointer, and to update the pointer to implement a circular buffer in the plurality of non-volatile memory blocks. In some cases, the non-volatile memory blocks are flash memory blocks. | 03-10-2011 |
20110063910 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 03-17-2011 |
20110063911 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 03-17-2011 |
20110063912 | METHODS AND STRUCTURES FOR READING OUT NON-VOLATILE MEMORY USING NVM CELLS AS A LOAD ELEMENT - A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array. | 03-17-2011 |
20110063913 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit. | 03-17-2011 |
20110069550 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 03-24-2011 |
20110075482 | MAINTAINING INTEGRITY OF PRELOADED CONTENT IN NON-VOLATILE MEMORY DURING SURFACE MOUNTING - A non-volatile memory chip package is prepared for surface mounting to a substrate in a solder reflow process by programming erased blocks to higher threshold voltage levels, to improve data retention for blocks which are preloaded with content, such as by an electronic device manufacturer. Following the surface mounting, the previously-erased blocks are returned to the erased state. The threshold voltage of storage elements of the preloaded blocks can change during the surface mounting process due to a global charge effect phenomenon. The effect is most prominent for higher state storage elements which are surrounded by erased blocks, in a chip for which the wafer backside was thinned and polished. The erased blocks can be programmed using a single program pulse without performing a verify operation, as a wide threshold voltage distribution is acceptable. | 03-31-2011 |
20110075483 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a non-volatile semiconductor storage device includes a control circuit. When performing a read operation, the control circuit is configured to: apply a first voltage to a selected word line that is connected to a selected memory cell, the first voltage being a voltage between a plurality of threshold voltage distributions; apply a second voltage to a first unselected word line adjacent to the selected word line, the second voltage being not more than the first voltage; apply a third voltage to a second unselected word line adjacent to the first unselected word line, the third voltage being not less than a read pass voltage at which non-volatile memory cells become conductive; and apply the read pass voltage to a third unselected word line, the third unselected word line being an unselected word line other than the first unselected word line and the second unselected word line. | 03-31-2011 |
20110090737 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING AND FABRICATING THE SAME - A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line. | 04-21-2011 |
20110096602 | NONVOLATILE MEMORY DEVICES OPERABLE USING NEGATIVE BIAS VOLTAGES AND RELATED METHODS OF OPERATION - A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first well. The first and second address decoders are associated with first and second memory blocks, respectively. A switch circuit is configured to provide a negative voltage to one of the first address decoder and the second address decoder on the basis of block address information that specifies an address included in one of the first memory block and the second memory block. Related methods of operation are also discussed. | 04-28-2011 |
20110122696 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time. | 05-26-2011 |
20110128788 | NAND FLASH MEMORY - A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line. The NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line. The NAND flash memory has a first block; a second block; and a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the third and fourth drain side selection MOS transistors and turns off the other. | 06-02-2011 |
20110128789 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells. | 06-02-2011 |
20110134696 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 06-09-2011 |
20110141813 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 06-16-2011 |
20110149652 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group. | 06-23-2011 |
20110149653 | NAND FLASH MEMORY - A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage. | 06-23-2011 |
20110157988 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes memory blocks each comprising a plurality of memory cells formed over a semiconductor substrate having a P well, a first voltage generator supplying operating voltages to an selected block of the memory blocks, and a second voltage generator generating a negative voltage to the P well during a program operation. | 06-30-2011 |
20110170350 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 07-14-2011 |
20110188310 | NONVOLATILE MEMORY DEVICES WITH COMMON SOURCE LINE VOLTAGE COMPENSATION AND METHODS OF OPERATING THE SAME - A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided. | 08-04-2011 |
20110199824 | STORING OPERATIONAL INFORMATION IN AN ARRAY OF MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a column scramble to shift the order of the data units. The method includes storing the data units in memory cells of at least one row of a second block of memory cells, wherein an order of the data units stored in the at least one row of the second block is different than an order of the data units stored in memory cells of the at least one row of the first block. | 08-18-2011 |
20110199825 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased. | 08-18-2011 |
20110199826 | CHARGE LOSS COMPENSATION METHODS AND APPARATUS - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 08-18-2011 |
20110205797 | METHOD AND APPARATUS FOR PERFORMING MULTI-BLOCK ACCESS OPERATION IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address. | 08-25-2011 |
20110205798 | High speed operation method for Twin MONOS metal bit array - The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell. | 08-25-2011 |
20110216592 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines. | 09-08-2011 |
20110216593 | NAND FLASH MEMORY - A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group. | 09-08-2011 |
20110216594 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 09-08-2011 |
20110228606 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a first block, a second block, a storage circuit, a controller. A first block comprises a first select gate and a first word line. A second block comprises a second select gate and a second word line. A storage circuit configures to store first data concerning a voltage to be applied to the first select gate, and second data concerning a voltage to be applied to the second select gate. A controller configures to control the voltages to be applied to the first select gate and the second select gate. The controller applies, in a write operation, a first voltage to the first select gate based on the first data, and a second voltage different from the first voltage to the second select gate based on the second data. | 09-22-2011 |
20110228607 | ADJUSTING PROGRAM AND ERASE VOLTAGES IN A MEMORY DEVICE - A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string. | 09-22-2011 |
20110235416 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device for raising operating speed is provided. The nonvolatile semiconductor memory device includes plural bit lines extending in a first direction, and a memory cell that includes plural blocks each having plural NAND strings each of which includes a group of memory cells connected in series with one another and selecting transistors connected to the respective ends of the memory cell group. One ends of current paths in ones of the selecting transistors are connected to the bit lines, while one ends of current paths in the other selecting transistors are connected to a source line. The nonvolatile semiconductor memory device further includes a memory cell array and a voltage control circuit that is disposed in the memory cell array in a manner of bisecting the memory cell array and that charges or discharges the bit lines. | 09-29-2011 |
20110235417 | NAND FLASH MEMORY - A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state. | 09-29-2011 |
20110249501 | DYNAMIC POLARIZATION FOR REDUCING STRESS INDUCED LEAKAGE CURRENT - Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current. | 10-13-2011 |
20110255339 | METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE - An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links. | 10-20-2011 |
20110267885 | NON-VOLATILE MEMORY AND METHOD WITH EVEN/ODD COMBINED BLOCK DECODING - A nonvolatile memory array is organized into a plurality of interleaving even and odd blocks. When a block is selected for operation, a set of word line voltages are delivered to the block of word lines by space-efficient decoding circuits and scheme. The plurality of blocks is organized into an array of pairs of adjacent odd and even blocks. A first voltage bus allows all even blocks access to the set of word line voltages. A second voltage bus allows all odd blocks access to the set of word line voltages. A decoder for selection is provided for each pair of adjacent even and odd blocks. Selecting a block is effected by selecting the pair of adjacent even and odd blocks containing the selected block, and supplying the set of word line voltages only to the selected block, which is one of the even or odd block in the selected pair. | 11-03-2011 |
20110267886 | Nonvolatile Semiconductor Memory Device - A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed. | 11-03-2011 |
20110280074 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of the flash memory. A target pair page is then selected from a plurality of pair pages of the target block according to a pair page record table, wherein the pair page comprises a strong page and a weak page. The flash memory is then directed to write a data page of the write data to the strong page of the target pair page. The flash memory is then also directed to write first predetermined data to the weak page of the target pair page, wherein the weak page storing the first predetermined data extends the data duration of the strong page of the target pair page. Selecting of the target pair page, writing of the data page, and writing of the first predetermined data are repeated until all of the write data are written to the target block. | 11-17-2011 |
20110286272 | MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size. | 11-24-2011 |
20110292729 | Method of Controlling Non-Volatile Memory Device - A method of controlling a non-volatile memory device includes comparing the number of banks that are in operating states with a threshold value. If the number of the banks is smaller than the threshold value, data stored in a standby bank is read. If there is no bank having data to be read, a standby bank is programmed. If the number of the banks is equal to or greater than the threshold value or if the reading or the programming is performed, it is determined whether there is a reading or programming command to be performed. If there is the reading or programming command to be performed, the process is repeated from the comparing step. The programming may include programming of a most significant bit (MSB) page or a least significant bit (LSB) page. | 12-01-2011 |
20110310666 | PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS IN CHANNELS - In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described. | 12-22-2011 |
20110310667 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 12-22-2011 |
20110310668 | Flash Memory Device and Program Method Thereof - A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area is provided. | 12-22-2011 |
20120002473 | BACKGROUND POWER CONSUMPTION REDUCTION OF ELECTRONIC DEVICES - An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition. | 01-05-2012 |
20120002474 | INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM - An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank. | 01-05-2012 |
20120002475 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded. | 01-05-2012 |
20120002476 | Semiconductor Memory With Improved Block Switching - A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system. | 01-05-2012 |
20120008392 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes a plurality of memory blocks, a plurality of erasure detection units provided at the plurality of memory blocks, respectively, and configured to each detect erasure of the respective memory blocks, and a control unit configured to determine that a memory block is a bad memory block when a number of erasure operations performed on the memory block as detected by the respective erasure detection unit is greater than a reference value. | 01-12-2012 |
20120008393 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF - An operation method of a nonvolatile memory device includes reading information of an erase target block, and performing an erase operation by using a starting erase bias corresponding to the information. | 01-12-2012 |
20120008394 | NONVOLATILE MEMORY SYSTEM AND REFRESH METHOD - A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence. | 01-12-2012 |
20120008395 | Nonvolatile Memory Device and Method of Operating the Same - A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage. | 01-12-2012 |
20120008396 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING THE SAME - A semiconductor memory device includes memory cell blocks having physical pages coupled to memory cells, peripheral circuits configured to program the memory cells or read data stored in the memory cells, and a controller configured to control the peripheral circuits so that a pre-program is performed to make memory cells in the memory cell blocks have threshold voltages higher than a set voltage by programming memory cells of the selected memory cell block, having threshold voltages lower than the set voltage, in response to an erase command. The set voltage is an intermediate threshold voltage obtained from the threshold voltages of the memory cells of the selected memory cell block. | 01-12-2012 |
20120008397 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program operation and a most significant bit (MSB) program operation have been performed and a memory controller configured to check which of the first and second memory block groups a memory block selected for an LSB data read operation belongs to and set a level of a read voltage for the LSB data read operation of the selected memory block. | 01-12-2012 |
20120014181 | Nonvolatile Semiconductor Memory - A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher. | 01-19-2012 |
20120020160 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF - A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution. While the control circuit executes a voltage applying operation in memory cells to be maintained in an erased state, thereby moving a first threshold voltage distribution to a positive direction to obtain a third threshold voltage distribution representing the erased state. | 01-26-2012 |
20120033497 | NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE - A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted. | 02-09-2012 |
20120039127 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state. | 02-16-2012 |
20120039128 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 02-16-2012 |
20120044764 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command. | 02-23-2012 |
20120057405 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target. | 03-08-2012 |
20120063228 | DATA SENSING ARRANGEMENT USING FIRST AND SECOND BIT LINES - Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers. | 03-15-2012 |
20120063229 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding. | 03-15-2012 |
20120069660 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 03-22-2012 |
20120069661 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit during an erase operation sets a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage, sets a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage which differs from the first voltage, applies in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and applies a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 03-22-2012 |
20120069662 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cell units including serially-connected memory cells, which includes a semiconductor pillar and conductive and insulation films surrounding the semiconductor pillar. The memory cell units constitute blocks each of which is the minimum unit of data erasure. A pipe layer in at least one pair of adjacent first and second memory cell units of the memory cell units includes a semiconductor layer connected to the semiconductor pillars in the first and second memory cell units, and are connected to first ends of the first and second memory cell units. A conductive plate between the first ends of the first and second memory cell units and the semiconductor substrate contain the pipe layers of at least two blocks and controls conduction of the pipe layers. A supply path structure is connected to the plate and transmitting a potential the plate. | 03-22-2012 |
20120069663 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 03-22-2012 |
20120069664 | FLASH MEMORY SYSTEM AND WORD LINE INTERLEAVING METHOD THEREOF - Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array. | 03-22-2012 |
20120069665 | Memory Device With Vertically Embedded Non Flash Non Volatile Memory For Emulation Of Nand Flash Memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 03-22-2012 |
20120081960 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell data holding transistors provided in each block; a row decoder including transfer transistors, a voltage controller and a block selector in each block, the transfer transistors electrically connected to respective of the memory cell transistors, the voltage controller connected to gates of the respective transfer transistors and transferring a desired voltage to the gates of the respective transfer transistors, the block selector electrically connected to gates of the respective transfer transistors and configured to select blocks. A voltage generator generates the voltage to be supplied to the transfer transistors; and a controller controls the row decoder and the voltage generator circuit. When data is written, the gates of the respective transfer transistors are connected to the voltage controller in each non-selected block, and the gates of the respective transfer transistors are disconnected from the voltage controller in each selected block. | 04-05-2012 |
20120092928 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory-cell array provided between a first region and a second region, and including a plurality of memory cells; a first row decoder and a second row decoder; a first power line provided in the first region; a second power line provided in the first region; a first power-supply circuit configured to supply the first voltage to the first power line and to the second power line; a first switching circuit; and a second switching circuit. In a write operation, the first switching circuit connects the first power line and the first power-supply circuit to each other whereas the second switching circuit disconnects the second power line and the first power-supply circuit from each other. | 04-19-2012 |
20120092929 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 04-19-2012 |
20120092930 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM - A semiconductor memory device includes a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register. | 04-19-2012 |
20120099375 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a nonvolatile memory device includes performing a first program loop, including a first program operation and a first program verification operation, for memory cells of a first page, counting a number of times that the first program loop is performed and storing the counted number when a memory cell having a threshold voltage higher than a first verification voltage, among the memory cells of the first page, is detected, and performing a second program loop, including a second program operation and a second program verification operation, for memory cells of a second page in response to the stored number for the first program loop. | 04-26-2012 |
20120099376 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 04-26-2012 |
20120099377 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit. | 04-26-2012 |
20120113720 | SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD THEREOF - A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed. | 05-10-2012 |
20120134210 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 05-31-2012 |
20120134211 | MEMORY SYSTEM - A memory system includes: a plurality of banks each including a memory cell array and a sense amplifier; a buffer circuit electrically connected to the plurality of banks; a switch circuit configured to switch on and off an electrical connection between the buffer circuit and each of the plurality of banks an interface electrically connected to the buffer circuit; and a controller configured to control the plurality of banks, the buffer circuit, the switch circuit and the interface, wherein for reading data held in the memory cell array by outputting the data to the interface in 5 clock cycles, the controller is configured to control the switch circuit in order that the switch circuit electrically connects a selected one of the banks to the buffer circuit upon the lapse of 1.5 clock cycles after a clock is inputted into the selected bank. | 05-31-2012 |
20120155175 | FLASH MEMORY DEVICE AND OPERATION METHOD THEREOF - A method for operating a flash memory device includes storing a first command and a first address corresponding to a first plane, storing a second command and a second address corresponding to a second plane, and performing a first command operation for the first plane based on the first command and the first address and performing a second command operation for the second plane based on the second command and the second address, wherein the first address includes a first block address for selecting a block in the first plane, and the second address includes a second block address for selecting a block in the second plane. | 06-21-2012 |
20120163081 | Nonvolatile Memory Devices - Nonvolatile memory devices including a memory cell array with a plurality of memory blocks and a plurality of bit lines arranged at the memory cell array. Each of the plurality of memory blocks may include a plurality of strings arranged in rows and columns and formed to be vertical to a substrate. Strings of each row of each memory block are connected with the bit lines, respectively, and strings of each column of each memory block are connected in common with a corresponding one of the bit lines. One memory block of the plurality of memory blocks includes a first region for storing ROM data and a second region for storing replica ROM data for repairing the ROM data. | 06-28-2012 |
20120163082 | MEMORY WITH SUB-BLOCKS - The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block. | 06-28-2012 |
20120182802 | Memory Architecture of 3D Array With Improved Uniformity of Bit Line Capacitances - A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions. | 07-19-2012 |
20120182803 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING FAILURE-RELIEF EFFICIENCY - According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong. | 07-19-2012 |
20120201080 | Nonvolatile Memory Devices And Driving Methods Thereof - Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. | 08-09-2012 |
20120206965 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, an erase verification execution unit that makes an erase verify operation of a memory cell, on which an erase operation is performed, to be performed, a number-of-erase-verifications counting unit that counts the number of erase verifications of a memory cell on which the erase operation is performed, and a number-of-erase-verifications setting unit that sets a minimum number of erase verifications from the next time based on the current number of erase verifications counted by the number-of-erase-verifications counting unit are included. | 08-16-2012 |
20120206966 | METHOD FOR MODIFYING DATA MORE THAN ONCE IN A MULTI-LEVEL CELL MEMORY LOCATION WITHIN A MEMORY ARRAY - A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function. | 08-16-2012 |
20120213004 | NON-VOLATILE MEMORY DEVICE AND RELATED READ METHOD - A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor. | 08-23-2012 |
20120213005 | NON-VOLATILE MEMORY DEVICE, MEMORY CONTROLLER, AND METHODS THEREOF - The method includes receiving a block address and an erase command output from a controller, and changing, until an erase operation performed according to the erase command on a block corresponding to the block address is completed, a parameter value related to the erase operation. The method further includes storing information corresponding to a finally changed parameter value, and transmitting the information to the controller according to a command output from the controller. | 08-23-2012 |
20120218819 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 08-30-2012 |
20120218820 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that of the at least two conductive layers in the first and second blocks are disposed on the driver, and select gate lines in the first and second blocks are connected to the driver through the at least two conductive layers on the driver. | 08-30-2012 |
20120218821 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current. | 08-30-2012 |
20120224426 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected one of the plurality of vertical strings, selecting a sensing manner corresponding to the judged channel length, and performing a sensing operation according to the selected sensing manner. The plurality of vertical strings may extend in a direction perpendicular to a substrate of the nonvolatile memory device. | 09-06-2012 |
20120224427 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a block dividing unit groups l word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying unit has an erasing verifying operation performed on memory cells subjected to the erasing operation, on a divisional block basis. | 09-06-2012 |
20120230106 | SEMICONDUCTOR MEMORY DEVICES, READING PROGRAM AND METHOD FOR MEMORY DEVICES - A semiconductor memory device, having a memory array which has two memory banks which can be accessed simultaneously is provided. A word line selection circuit selects the word line according to the row address information, and a controller controls the word line selection circuit according to the received instruction. The controller performs the first read operation of the word line selection circuit in response to a first read command, and performs the second read operation of the word line selection circuit in response to a second read command. The first read operation selects the n-th word line of one of the memory banks and selects the (n+1)-th or (n−1)-th word line of the other memory bank, and the second read operation selects the n-th word line of one of the memory banks and selects the n-th word line of the other memory bank. | 09-13-2012 |
20120230107 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad. | 09-13-2012 |
20120236643 | INTERLEAVED FLASH STORAGE SYSTEM AND METHOD - A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer. | 09-20-2012 |
20120236644 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to an embodiment includes: a memory cell array including plural word lines, plural bit lines, and plural memory cells each of which is selected by the word line and the bit line, the memory cell array being divided into plural blocks, some of the word lines being set to a specific word line, at least some of or all the memory cells in each block being set to specific memory cells, the memory cell being accessed by the specific word line, the specific data except user data being stored in the specific memory cell; and an erasing circuit that erases the memory cell of the memory cell array, the erasing circuit referring to the specific data stored in the specific memory cell belonging to the certain block during an erasing operation of the memory cell belonging to the certain block. | 09-20-2012 |
20120236645 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a shape of a matrix along a plurality of parallel bit lines and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line and decides the read data from each of the memory cells; a clamping transistor connected between the sense amplifier and the bit lines to determine a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer. | 09-20-2012 |
20120243316 | MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size. | 09-27-2012 |
20120250412 | FLASH MEMORY APPARATUS AND METHOD FOR GENERATING READ VOLTAGE THEREOF - A flash memory apparatus includes: a cell array including a plurality of main blocks, a code addressable memory (CAM) block, and a security block; a control unit configured to detect a threshold voltage change data of a main block to which a program operation has been performed among the plurality of main blocks, and set a trimming value corresponding to the detected threshold voltage change data; and a read voltage generation unit configured to generate a read voltage according to the set trimming value. | 10-04-2012 |
20120257452 | NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources. | 10-11-2012 |
20120262987 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 10-18-2012 |
20120262988 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block. | 10-18-2012 |
20120262989 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells. | 10-18-2012 |
20120268991 | DATA STORAGE DEVICE AND BLOCK SELECTION METHOD FOR A FLASH MEMORY - The invention provides a block selection method for a flash memory. First, a flash memory is divided into a plurality of great block groups. Each of the great block groups is then divided into a plurality of block groups. Scores corresponding to the blocks of the flash memory are then recorded in a score table. When the score of a target block selected from the blocks of the flash memory has been amended, the amended score of the target block is compared with a first extreme value and a second extreme value corresponding to the block group and the great block group comprising the target block and the total extreme value. A victim block is then determined from the blocks of the flash memory according to an extreme value table. | 10-25-2012 |
20120268992 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array configured to include a plurality of memory blocks, a voltage generator configured to output operating voltages for data input and output to global lines, and a row decoder configured to transfer the operating voltages to local lines of a memory block, selected from among the plurality of memory blocks, and supply a ground voltage to local lines of unselected memory blocks in response to address signals. | 10-25-2012 |
20120268993 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second memory planes that each include a plurality of memory blocks, a first page buffer group coupled to the memory blocks of the first memory plane through first bit lines and configured to perform a read operation and a program operation, a second page buffer group coupled to the memory blocks of the second memory plane through second bit lines and configured to perform the read operation and the program operation, a coupling circuit configured to couple the first bit lines of the first memory planes and the second bit lines of the second memory planes, respectively, in response to a coupling signal, and a control circuit configured to generate the coupling signal for controlling the coupling circuit in a copyback operation of data, read from a source page of the first memory plane, in a target page of the second memory plane. | 10-25-2012 |
20120268994 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time. | 10-25-2012 |
20120268995 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC APPARATUS - A memory cell array including non-volatile memory cells is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data. A word line select circuit and a bit line select circuit select a first word line and a first bit line connected to the second block to access the non-volatile memory cell for storing data of the second block, and selects a second word line or a second bit line connected to the first block to apply a stress voltage to the non-volatile memory cell for accumulating the degradation over time of the first block, thereby automatically detecting ambient temperature and storing accumulated stress. | 10-25-2012 |
20120275223 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - There is disclosed an operating method of a semiconductor device including programming a memory cell by supplying a program voltage to a control gate of the memory cell and a detrap voltage to a well which is formed in a semiconductor substrate, and subsequently removing electrons trapped in a tunnel insulating layer of the memory cell by supplying a voltage lower than the detrap voltage to the control gate while also supplying the detrap voltage to the well before the programmed memory cell is verified. | 11-01-2012 |
20120275224 | OPERATING METHOD OF SEMICONDUCTOR DEVICE - An operating method of a semiconductor device that includes a plurality of memory cell blocks, comprising selecting one of the memory cell blocks in response to a program command, performing a pre-program operation and a pre-erase operation so that threshold voltages of memory cells included in the selected memory cell block are distributed between a first positive voltage and a first negative voltage, supplying a program permission voltage to a first group of bit lines and supplying a program inhibition voltage to a second group of bit lines, wherein the first group and the second group are mutually exclusive, and supplying a positive program voltage to a selected word line coupled to memory cells. | 11-01-2012 |
20120287713 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes a plurality of memory blocks and a high voltage application unit configured to apply a high voltage to a word line of a memory block unselected from among the plurality of memory blocks and float the word line, during the erase operation. | 11-15-2012 |
20120287714 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output. | 11-15-2012 |
20120294084 | Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 11-22-2012 |
20120294085 | MULTI-PARTITION ARCHITECTURE FOR MEMORY - A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory. | 11-22-2012 |
20120294086 | ADAPTIVE PROGRAMMING FOR FLASH MEMORIES - A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles. | 11-22-2012 |
20120314499 | INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE - A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage. | 12-13-2012 |
20120320677 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line. | 12-20-2012 |
20120320678 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block. | 12-20-2012 |
20120327712 | METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells. | 12-27-2012 |
20130003460 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 01-03-2013 |
20130010539 | NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE - Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals. | 01-10-2013 |
20130016560 | SEMICONDUCTOR MEMORY DEVICESAANM YANO; MasaruAACI TokyoAACO JPAAGP YANO; Masaru Tokyo JPAANM CHIANG; Lu-PingAACI Hsinchu CityAACO TWAAGP CHIANG; Lu-Ping Hsinchu City TW - A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well. | 01-17-2013 |
20130016561 | ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICEAANM NAM; Sang-WanAACI Hwaseong-siAACO KRAAGP NAM; Sang-Wan Hwaseong-si KR - An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage. | 01-17-2013 |
20130028020 | NAND FLASH MEMORY - A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage. | 01-31-2013 |
20130051144 | SEMICONDUCTOR STORAGE DEVICE COMPRISING ELECTRICALLY REWRITABLE NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor storage apparatus stores management information comprising, for each block of a nonvolatile semiconductor memory, information denoting at least one of a recent programming time, which is a time at which data is recently programmed to a block, and a recent erase time, which is a time at which an erase process is recently carried out with respect to a block. The semiconductor storage apparatus (b1) controls a timing at which data is programmed to a block based on at least one of the recent programming time and the recent erase time of this block, and/or (b2) controls a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block. | 02-28-2013 |
20130051145 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes memory blocks that each include memory cells coupled to bit lines, a column masking circuit configured to output data change signals in response to an address signal indicating bit lines of selected columns among a plurality of columns, and an operation circuit configured to store data of the memory cells transferred through the bit lines and simultaneously change data transferred through the bit lines of the selected columns into operation pass data in response to the data change signals. | 02-28-2013 |
20130051146 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation. | 02-28-2013 |
20130058165 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block. | 03-07-2013 |
20130070527 | SYSTEM AND METHOD FOR MANAGING ERASE OPERATIONS IN A NON-VOLATILE MEMORY - Embodiments of the invention are directed to managing a memory component. A method may include performing a first erase operation according to a first set of erase parameters, determining a result of the first erase operation, modifying the first set erase parameters based on the result to produce a second set of erase parameters and performing a second erase operation according to a second set of erase parameters. A condition parameter may be maintained based on the erased parameters and/or based on a result of an erase procedure. | 03-21-2013 |
20130070528 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a bit line, a source line, and a sense circuit. The memory cell array includes memory strings which include memory cells connected in series and stacked above a semiconductor substrate. The bit line is coupled to one of the memory strings and is capable of transferring data. The source line is coupled to one of the memory strings. When data is read, a read current flows from a bit line into the source line. The sense circuit is coupled to the bit line and senses read data. An operation timing of the sense circuit is determined on the basis of a current flowing through the source line. | 03-21-2013 |
20130070529 | Semiconductor device and operating method thereof - A method of operating a semiconductor device includes programming one of a drain dummy cell and a source dummy cell which are included in a cell string; and coupling a bit line to the cell string in response to program states of the drain dummy cell and the source dummy cell and a voltage level applied to a drain dummy line coupled to a gate of the drain dummy cell and a source dummy line coupled to a gate of the source dummy cell. | 03-21-2013 |
20130070530 | HIGH ENDURANCE NON-VOLATILE STORAGE - A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells. | 03-21-2013 |
20130083599 | NONVOLATILE MEMORY AND ERASING METHOD THEREOF - An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block. | 04-04-2013 |
20130088918 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor layer, the wells being arranged in a first direction. A memory block is arranged in each well. A plurality of word lines are provided, each word line being commonly connected to a plurality of NAND cell units in one memory block. A plurality of bit lines extend in a first direction, the bit lines being connected to first ends of the | 04-11-2013 |
20130094296 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 04-18-2013 |
20130100737 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory comprises a memory block having memory cells stacked in a three dimensional structure. The nonvolatile memory device performs an erase operation to erase a selected sub block among sub blocks of the memory block, a verification operation to determine whether program states of memory cells of an unselected sub block of the memory block have changed as a consequence of the erase operation, and a reprogramming operation to reprogram at least a portion of the unselected sub block upon determining that at least one of the program states have changed as a consequence of the erase operation. | 04-25-2013 |
20130100738 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES - A three-dimensional (3-D) nonvolatile memory device includes channel layers protruded from a substrate, word line structures configured to include word lines stacked over the substrate, first junctions and second junctions formed in the substrate between the word line structures adjacent to each other, source lines coupled to the first junctions, respectively, and well pickup lines coupled to the second junctions, respectively. | 04-25-2013 |
20130100739 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data. | 04-25-2013 |
20130107627 | BACK-BIASING WORD LINE SWITCH TRANSISTORS | 05-02-2013 |
20130114340 | SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA - A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase. | 05-09-2013 |
20130121075 | SYSTEMS AND METHODS FOR OPERATING MULTI-BANK NONVOLATILE MEMORY - A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time, then identifies frequently-written data (“hot-data”) assigned to a memory bank that is heavily worn over that period of time and reassigns it to a less worn memory bank. | 05-16-2013 |
20130121076 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 05-16-2013 |
20130121077 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit. | 05-16-2013 |
20130128666 | Scrub Techniques for Use with Dynamic Read - The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected. | 05-23-2013 |
20130128667 | Low-Voltage Page Buffer to be Used in NVM Design - A low-current FN channel for Erase, Program, Program-Inhibit and Read operations is disclosed for any non-volatile memory using FN-tunneling scheme for program and erase operation, regardless NAND, NOR, and EEPROM and regardless PMOS or NMOS non-volatile cell type. As a result, all above NMV memories can use the disclosed LV, compact PGM buffer to replace the traditional HV PGM buffer for saving in the silicon area and power consumption. The page buffer is used to store new loaded data for new writing and to convert the stored data into the required BL HV voltage for either Erase or Program operations according to the stored data. In addition, the simpler on-chip State-machine design can be achieved with the superior quality of NVMs of this disclosure. | 05-23-2013 |
20130128668 | NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE - A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted. | 05-23-2013 |
20130135931 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory cell array including a first block that includes memory cells, a second memory cell array including a second block that includes memory cells, word lines arranged in the first and second memory cell arrays, and a row decoder including transfer gates that respectively transfer voltages to the word lines. Word lines arranged in the first block include first and second groups, word lines arranged in the second block include third and fourth groups, and the first and third groups commonly use the transfer gates. | 05-30-2013 |
20130141976 | Semiconductor Memory Apparatus - A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal. | 06-06-2013 |
20130155772 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - In a semiconductor memory device and a method of operating the same, a memory block including memory cells is divided into memory groups. A level of bit line voltage applied to a bit line coupled to the memory cells included in each of the memory groups varies according to a distance between a row decoder and each memory groups during a program operation. Characteristics of the threshold voltage distribution of the memory cells in the semiconductor memory device may be improved without deteriorating performance of the program. | 06-20-2013 |
20130163331 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device and a method of operating the same results in reduced programming time. The semiconductor memory device includes advanced circuitry that enables reductions in programming and verification times, leading to a substantial reduction in the total time required to program the device. | 06-27-2013 |
20130170298 | SCALABLE MEMORY SYSTEM - A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance. | 07-04-2013 |
20130176784 | ADJUSTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION - Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters. | 07-11-2013 |
20130188422 | METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE - An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links. | 07-25-2013 |
20130194868 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A limiter circuit compares a voltage of a control gate line and a set voltage, thereby switching the logic of a flag signal. A booster circuit starts or stops its operation according to the logic of the flag signal. A leak reference circuit has a function of leaking a leak reference current from the control gate line. A counter generates a first count value by counting the number of times the flag signal logic changes in a condition that a word-line transfer transistor is rendered non-conductive and a leak reference circuit is driven, while the counter generates a second count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered conductive and the leak reference circuit is undriven. A comparator compares the first count value and the second count value. | 08-01-2013 |
20130194869 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N−1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string. | 08-01-2013 |
20130194870 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory block including memory strings coupled to and disposed between bit lines and a common source line, and a peripheral circuit configured to perform a read operation of memory cells included in selected memory strings of the memory strings and increase channel potential of unselected memory strings in the read operation. | 08-01-2013 |
20130223147 | NONVOLATILE MEMORY DEVICE AND MEMORY MANAGEMENT METHOD THEREOF - Embodiments include a memory managing method of a nonvolatile memory device, which includes detecting whether sub-blocks of memory blocks are programmed, and programming write data at a memory block having a programmed sub-block from among the memory blocks, prior to programming a memory block having no programmed sub-blocks from among the memory blocks, according to the detection result. Embodiments also include programming the write data at a sub-block, closest to a common source line, from among unprogrammed sub-blocks of the memory block. Embodiments also include erasing at least one sub-block that is farthest from the common source line, prior to erasing other sub-blocks from among the programmed sub-blocks in the memory block. Embodiments also include selectively programming or erasing sub-blocks according to read merge times. | 08-29-2013 |
20130223148 | NONVOLATILE MEMORY DEVICE AND EMBEDDED MEMORY SYSTEM INCLUDING THE SAME - Integrated circuit memory devices include an array of nonvolatile memory cells having a plurality of pairs of nonvolatile memory cells therein. The plurality of pairs of nonvolatile memory cells include a first pair of nonvolatile memory cells, which share an erase gate electrode. Each of the nonvolatile memory cells in the first pair of nonvolatile memory cells includes a respective control gate electrode and the shared erase gate electrode extends between the control gate electrodes within the first pair of nonvolatile memory cells. Each of the first pair of nonvolatile memory cells may include a data storage transistor, which has a floating gate electrode therein, and a selection transistor. These transistors may be electrically connected in series and the shared erase gate electrode may extend between the floating gate electrodes. | 08-29-2013 |
20130229871 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - Plural memory-strings are arranged in each memory-blocks, the memory-strings extending perpendicular to a substrate. Each memory-string includes plural memory-transistors and dummy-transistors connected in series. The drain-side select gate line and source-side select gate line are supplied with a voltage from the control circuit through the transfer-transistors when corresponding one of the memory blocks is selected. The drain-side select gate line and source-side select gate line are set in a floating state by the transfer-transistors that are rendered non-conductive when corresponding one of the memory-blocks is not selected. The dummy word-line is supplied with a voltage from the control circuit through a first transfer-transistor that are rendered conductive when corresponding memory block is selected. The dummy word-line is supplied with a voltage through a second transfer transistor different from the first transfer-transistor when corresponding memory-block is not selected. | 09-05-2013 |
20130229872 | ERASING METHOD OF NON-VOLATILE MEMORY DEVICE - A method for erasing a first sub-block of a plurality of sub-blocks included in a block of a non-volatile memory device, wherein the first sub-block includes at least one word line, includes applying an erase voltage to a substrate, applying a third voltage lower than the erase voltage to the word line of the first sub-block, applying a first voltage at least one word line adjacent to the word line of the first sub-block, and applying a second voltage that is the same as or similar to the erase voltage to the other word lines, where the first voltage has a level between the third voltage and the second voltage. | 09-05-2013 |
20130242658 | SYSTEM AND METHOD FOR ACCESSING AND STORING INTERLEAVED DATA - A flash storage system includes a data buffer configured to receive and store a data block having data portions. The system further includes flash storage devices having storage blocks interleaved among the flash storage devices and a controller coupled to the data buffer and the flash storage devices. The controller is configured to initiate data transfers for writing the data portions of the data block asynchronously into the storage blocks, where the data transfers for writing the data portions of the data block asynchronously into the storage blocks include reading the data portions of the data block from the data buffer serially and writing the data portions of the data block into the storage blocks in parallel. | 09-19-2013 |
20130258775 | Adaptively Programming or Erasing Flash Memory Blocks - Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block. | 10-03-2013 |
20130258776 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA THEREFROM - A non-volatile semiconductor memory device according to an aspect includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory cells, and stores initial setting data in each of a plurality of storage areas. The control circuit reads the initial setting data from the storage areas. The control circuit is configured to read, when it detects an error in the initial setting data read from one of the storage areas, initial setting data from another storage area. | 10-03-2013 |
20130258777 | TIMIMG CONTROL IN SYNCHRONOUS MEMORY DATA TRANSFER - A solid-state memory device has a memory interface that includes a timing signal port for receiving a timing signal, a data transfer port, a data transfer module for transferring blocks of data signals between the data transfer port and the memory module, and a selectable delay module for providing a selected delay between transitions in the data signals DQ and transitions in the timing signals DQS. The memory interface also has a delay controller for setting the selected delay, for detecting a variation in a delay produced by the selectable delay module relative to a reference delay, for controlling a pause in transfer of a block of the data signals DQ, and for adjusting the selected delay during the pause. | 10-03-2013 |
20130258778 | READ VOLTAGE GENERATION CIRCUIT, MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A read voltage generation circuit includes a register unit configured to store an initial read voltage code, a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and a voltage generation circuit configured to generate a read voltage corresponding to a read voltage code produced by the counter circuit. | 10-03-2013 |
20130258779 | NAND MEMORY ARRAY WITH MISMATCHED CELL AND BITLINE PITCH - Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mis-matched cell and bitline pitch. Other embodiments may be described and claimed. | 10-03-2013 |
20130265825 | SYSTEM AND METHOD FOR MICRO-TIERING IN NON-VOLATILE MEMORY - In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP. | 10-10-2013 |
20130272067 | NON-BOOSTING PROGRAM INHIBIT SCHEME IN NAND DESIGN - A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page program algorithm to achieve less error rate of NAND cell threshold voltage level. Thus, the error correction code capability requirement can be reduced, thus the program yield can be increased to reduce the overall NAND die cost at advanced nodes below 20 nm. As a result, this NAND array can still use the LV, compact PGM buffer for saving in the silicon area and power consumption. In addition, the simpler on-chip state-machine design can be achieved with the superior quality of less program errors. | 10-17-2013 |
20130279255 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line. | 10-24-2013 |
20130286737 | NAND FLASH MEMORY HAVING C/A PIN AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time. | 10-31-2013 |
20130294163 | FLASH-BASED MEMORY SYSTEM WITH ROBUST BACKUP AND RESTART FEATURES AND REMOVABLE MODULES - A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit. | 11-07-2013 |
20130294164 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line. | 11-07-2013 |
20130301354 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells and a voltage generating circuit for generating a voltage for memory cells. The first voltage generating circuit includes a first diode connected between first and second nodes, a first transistor connected between the output terminal and a third node and having a gate connected to the second node, a second transistor connected between the third node and a fourth node and having a gate connected to the second node, a third transistor connected between the output terminal and the first node and having a gate connected to the fourth node, a second diode connected between the first and fourth nodes, and a charge pump circuit configured to supply a voltage to the fourth node. The first voltage generating circuit functions to adjust the generated voltage when it overshoots a desired value which may be caused by capacitive coupling with adjacent wirings. | 11-14-2013 |
20130308384 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING FAILURE-RELIEF EFFICIENCY - According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong. | 11-21-2013 |
20130314994 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 11-28-2013 |
20130322175 | METHOD OF REPROGRAMMING NONVOLATILE MEMORY COMPRISING MARKING SOME CELLS AS BLANKS - A method of operating a memory device comprises programming a first data signal to a first memory cell, attempting to program a second data signal to the first memory cell in a state where the first memory cell is not erased, and marking the first memory cell as blank upon failing to program the second data signal to the first memory cell. | 12-05-2013 |
20130322176 | ON-CHIP MEMORY TESTING - An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array. | 12-05-2013 |
20130329496 | NONVOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF - A method of erasing a nonvolatile memory device, which includes a plurality of memory blocks each formed of a plurality of strings, includes applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block including at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells. | 12-12-2013 |
20130329497 | METHOD AND APPARATUS FOR MANAGING OPEN BLOCKS IN NONVOLATILE MEMORY DEVICE - A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy. | 12-12-2013 |
20130336061 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the latch, performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation on memory cells associated with the selected first WL. | 12-19-2013 |
20130336062 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block. | 12-19-2013 |
20130343126 | FLASH MEMORY APPARATUS WITH REFERENCE WORD LINES - The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result. | 12-26-2013 |
20130343127 | METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells. | 12-26-2013 |
20140003147 | Optimized Erase Operation For Non-Volatile Memory With Partially Programmed Block | 01-02-2014 |
20140010014 | Managing Data Writing to Memories - Systems and processes may use a first memory, a second memory, and a memory controller. The second memory is at least as large as a block of the first memory. Data is received and stored in the second memory for further writing to the second memory. | 01-09-2014 |
20140010015 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command. | 01-09-2014 |
20140016412 | SEMICONDUCTOR MEMORY APPARATUS, DATA TRANSMISSION DEVICE, AND RECORDING METHOD - According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value. | 01-16-2014 |
20140016413 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased. | 01-16-2014 |
20140022845 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND READOUT METHOD THEREOF - A non-volatile semiconductor device includes: memory strings formed by series connection of memory cells respectively connected to word lines, wherein each memory string is connected between a bit line and a source line via first and second select gate transistors; and a control circuit controlling the first and second select gate transistors, such that when voltage of the word line is raised to a predetermined value for data readout from the memory cell, a first status where the first select gate transistor is turned on and the second select gate transistor is turned off and second status where the first select gate transistor is turned off and the second select gate transistor is turned on are generated alternately. | 01-23-2014 |
20140036590 | PARTIAL BLOCK MEMORY OPERATIONS - Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets. | 02-06-2014 |
20140043905 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell block formed over a first memory cell region and a second memory cell region defined on a semiconductor substrate, and a voltage supply circuit configured to apply an operating voltage to gate lines of a plurality of memory cells included in the memory cell block, wherein a first air gap disposed between the gate lines in the first memory cell region has a smaller size than a second air gap disposed between the gate lines in the second memory cell region. | 02-13-2014 |
20140043906 | SEMICONDUCTOR MEMORY DEVICES - A flash memory capable of writing or deleting a split block is provided. A flash memory includes a memory array comprising a plurality of blocks, and a word line selection circuit, wherein each of the plurality of blocks is formed by a plurality of cell units in a well. The cell unit comprises N memory cells, a selection transistor coupled to one terminal of the memory cells, a selection transistor coupled to the other terminal of the memory cells, and a dummy selection transistor coupled between the memory cells. The word line selection circuit splits the block into a first block and a second block to use according to the operation of data writing or data deleting. | 02-13-2014 |
20140043907 | NONVOLATILE MEMORY DEVICE AND METHOD FOR VOLTAGE TRIMMING THEREOF - A non-volatile semiconductor storage device includes memory blocks that each includes multiple memory strings. A bit line connects to an end of each string in the memory blocks and to a sense amplifier circuit which includes a first transistor. The device includes first and second discharge transistors for discharging the bit line. The first discharge transistor is located further, in the bit line direction, from the sense amplifier circuit than the second discharge transistor. The sense amplifier provides a sensing voltage to the bit line for reading data in the memory strings. A control circuit controls the level of the sensing voltage by supplying a trimming voltage to a gate of the first transistor in the sense amplifier to thereby adjust the level of the sensing voltage according to the distance of a selected memory block from sense amplifier to compensate for changes in the bit line resistance. | 02-13-2014 |
20140050026 | Method of Executing Wear Leveling in a Flash Memory Device According to Ambient Temperature Information and Related Flash Memory Device - A method of executing wear leveling in a flash memory device includes determining whether a current temperature is in a normal operating temperature range of the flash memory device, and reprogramming data associated with data blocks to another location in a flash memory array when the current temperature is in the normal operating temperature range of the flash memory device, wherein the data is programmed in a temperature out of the normal operating temperature range of the flash memory device. | 02-20-2014 |
20140056070 | APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS - Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described. | 02-27-2014 |
20140056071 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first memory block configured to include first active areas extended parallel in a first direction, a second memory block adjacent to the first memory block and configured to include second active areas extended parallel in the first direction, the second active areas being staggered from the first active areas, first bit lines disposed on the first active areas, and second bit lines disposed on the second active areas. | 02-27-2014 |
20140056072 | 3D MEMORY ARRAY WITH READ BIT LINE SHIELDING - A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines. | 02-27-2014 |
20140063946 | NON-VOLATILE MEMORY (NVM) THAT USES SOFT PROGRAMMING - A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached. When the first charge trapping threshold has been reached, a second soft program operation is performed using second soft program voltages and a second soft program verify level. | 03-06-2014 |
20140063947 | ERASABLE BLOCK SEGMENTATION FOR MEMORY - Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described. | 03-06-2014 |
20140063948 | NONVOLATILE MEMORY DEVICE AND DATA STORAGE DEVICE INCLUDING THE SAME - A nonvolatile memory device includes: a plurality of memory cells arranged in a region where word lines and bit lines intersect, a data read/write circuit including a plurality of latches configured to temporarily store data inputted from an external device, and configured to perform a program operation on the memory cells based on data stored in the latches, and a skip data control unit configured to determine whether data to be programmed into the memory cells are available, and to store program-inhibit data in a latch corresponding to a memory cell which is determined to not contain any data. | 03-06-2014 |
20140063949 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines. | 03-06-2014 |
20140063950 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and configured to sense current flow through the even bit line in response to an even bit line control signal and an even discharge signal. The semiconductor device further includes a second sensing circuit coupled to an odd bit line and configured to sense current flow through the odd bit lines in response to an odd bit line control signal and an odd discharge signal. The first sensing circuit and second sensing circuit are configured to supply a ground voltage to the odd bit line when sensing the current flow through the even bit line, and to supply the ground voltage to the even bit line when sensing the current flow through the odd bit line. | 03-06-2014 |
20140063951 | SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - An operating method of a semiconductor memory device is provided. The method includes supplying a first voltage to a selected bit line where a selected memory cell among memory cells is connected and a second voltage, which is higher than the first voltage, to an unselected bit line, supplying a third voltage to a selected drain select line where the selected memory cell is connected, and a fourth voltage lower than the third voltage to an unselected drain select line; and supplying a fifth voltage to a selected word line where the selected memory cell is connected, and a sixth voltage, which is lower than the fifth voltage, to an unselected word lines for a program operation. | 03-06-2014 |
20140063952 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group. | 03-06-2014 |
20140063953 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises: a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewritable memory cells and a select transistor connected in series; and a row decoder configured to select anyone of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations. The row decoder comprises: a plurality of first transfer transistors each disposed in a first region and connected to any one of the memory cells; and a plurality of second transfer transistors each disposed in a second region and connected to the select transistor, the second region being a residual region of the first region. | 03-06-2014 |
20140063954 | METHOD OF STORING DATA ON A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure. | 03-06-2014 |
20140071756 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER - According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect. | 03-13-2014 |
20140071757 | FLASH DUAL INLINE MEMORY MODULES WITH MULTIPLEXING SUPPORT CIRCUITS - In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC. | 03-13-2014 |
20140071758 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 03-13-2014 |
20140078825 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - Storage space allocation and a wear leveling technique for a FLASH memory module are disclosed. The FLASH memory module includes a plurality of FLASH chips. A controller for the FLASH memory module divides the storage space of the FLASH memory module into Xblocks for management of the FLASH memory module. The controller erases at least one Xblock for space release and moves data on Xblocks for wear leveling. | 03-20-2014 |
20140085979 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell array according to an embodiment includes a plurality of NAND strings with a plurality of memory cells stacked, and a bit line is connected to the NAND string. A word line is connected to a gate of the memory cell. A column system circuit is disposed directly under the memory cell array. When viewed from the top side, a global signal supply unit is disposed outside the memory cell array to supply a global signal to the column system circuit. When viewed from the top side, an upper interconnection is disposed over the bit line outside the memory cell array to transmit the global signal. A lower interconnection is disposed under the memory cell array to transmit the global signal to the column system circuit. A contact plug is configured to connect the upper interconnection and the lower interconnection. | 03-27-2014 |
20140085980 | MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria. | 03-27-2014 |
20140098608 | APPARATUS AND METHODS TO PERFORM READ-WHILE WRITE (RWW) OPERATIONS - Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed. | 04-10-2014 |
20140098609 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS - According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells. | 04-10-2014 |
20140104948 | SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE - A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks. | 04-17-2014 |
20140104949 | Reducing Erase Cycles In An Electronic Storage Device That Uses At Least One Erase-Limited Memory Device - A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed. | 04-17-2014 |
20140112073 | SIGNAL TRANSMISSION SYSTEM AND STORAGE SYSTEM - A signal transmission system is provided which connects a memory controller and a plurality of semiconductor memories. The signal transmission system comprises a semiconductor device arranged between the memory controller and the plurality of memories, in which: the semi-conductor device comprises a control circuit; and the control circuit receives a signal from the semiconductor memory and outputs a control signal to the memory controller in response to the signal from the semiconductor memory. | 04-24-2014 |
20140112074 | INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES - A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block. | 04-24-2014 |
20140119121 | ADJUSTING PROGRAM AND ERASE VOLTAGES IN A MEMORY DEVICE - A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string. | 05-01-2014 |
20140133229 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells. | 05-15-2014 |
20140133230 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning. | 05-15-2014 |
20140133231 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified. | 05-15-2014 |
20140133232 | Compensation for Sub-Block Erase - A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme. | 05-15-2014 |
20140133233 | CAM NAND with OR Function and Full Chip Search Capability - Various techniques for extending the capabilities of CAM NAND type memories are discussed. Multi-block or even full chip search operations can be performed. In addition to the inherent AND property of NAND strings, the memory array has an inherent OR property between NAND string from different blocks along the same bit line that can be exploited through multi-block CAM-type operations. To reduce data-dependent word line to word line effects, in multiple data dependent sensing operations, the sensing can be broken up into sub-operations that avoid data dependent values on adjacent word lines. To improve data protection, subsequent to writing a memory block with indices, the word lines are read back and compared bit-by-bit with their intended values and the results are accumulated to determine whether any of indices include error. A bloom filter can also be used as an initial check during data search operations in order to provide increased data protection. | 05-15-2014 |
20140133234 | FLASH EEPROM SYSTEM WITH SIMULTANEOUS MULTIPLE DATA SECTOR PROGRAMMING AND STORAGE OF PHYSICAL BLOCK CHARACTERISTICS IN OTHER DESIGNATED BLOCKS - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 05-15-2014 |
20140146608 | Oscillator Circuit With Location-Based Charge Pump Enable And Semiconductor Memory Including The Same - A semiconductor memory includes a plurality of memory blocks each comprising a plurality of memory cells, and a plurality of charge pumps each located near one of the plurality of memory blocks. In an access to the semiconductor memory, depending on the selected memory block, a subset or all of the plurality of charge pumps are activated in one of a predetermined number of sequences. | 05-29-2014 |
20140153333 | Systems and Methods to Avoid False Verify and False Read - In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells. | 06-05-2014 |
20140160846 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block. | 06-12-2014 |
20140160847 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A nonvolatile memory device comprises a 3D memory cell array comprising multiple mats corresponding to different bit lines, each of the mats comprising multiple memory blocks, each of the memory blocks comprising multiple cell strings disposed perpendicular to a substrate and multiple string selection lines configured to select or unselect the cell strings, and each of the cell strings comprising at least one ground selection transistor, multiple memory cells, and at least one string selection transistor stacked in a direction perpendicular to the substrate. The nonvolatile memory device further comprises a string selection controller electrically connected to the mats through the string selection lines and configured to provide multiple string selection signals respectively corresponding to the string selection lines. Each of the string selection lines is connected with only one of the mats and the string selection signals are controlled independent from one another to independently select or unselect cell strings of different mats. | 06-12-2014 |
20140169093 | ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH - Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify | 06-19-2014 |
20140177337 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 06-26-2014 |
20140185381 | SEMICONDUCTOR APPARATUS AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor device includes: performing a program operation of selected memory cells of a memory block; setting a level of a program verification voltage according to the number of times program/erase operation is performed on the selected memory cells; and performing a program verification operation by applying the program verification voltage of the set level to the selected memory cells, in which the level of the program verification voltage is increased in proportion to the number of times a program/erase operation is performed. | 07-03-2014 |
20140192594 | P-CHANNEL 3D MEMORY ARRAY - A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce −FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce −FN hole tunneling in selected blocks of cells. | 07-10-2014 |
20140192595 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 07-10-2014 |
20140219024 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and a second NAND cell unit are connected to one of the bit lines. A bit-line-side select transistor in the first NAND cell unit and a source-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. The source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. | 08-07-2014 |
20140219025 | PROGRAM AND READ METHODS OF MEMORY DEVICES USING BIT LINE SHARING - A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal. | 08-07-2014 |
20140219026 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 08-07-2014 |
20140233315 | 3D STACKED NAND FLASH MEMORY ARRAY HAVING SSL STATUS CHECK BUILDINGS FOR MONITORING THRESHOLD VOLTAGES OF STRING SELECTION TRANSISTORS AND METHODS FOR MONITORING AND OPERATING THE SAME - Disclosed is a 3D stacked NAND flash memory array having SSL status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the SSL status check buildings, and an operating method thereof. | 08-21-2014 |
20140241060 | SUB-BLOCK DECODING IN 3D MEMORY - Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described. | 08-28-2014 |
20140247658 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected to a gate electrode of the selection transistor, a driver, or a node that supplies an unselected voltage, or is set to be in a floating state. | 09-04-2014 |
20140247659 | REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NON-VOLATILE MEMORY - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling. | 09-04-2014 |
20140247660 | Compensation for Sub-Block Erase - A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme. | 09-04-2014 |
20140247661 | Erase For 3D Non-Volatile Memory With Sequential Selection Of Word Lines - An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved. | 09-04-2014 |
20140254267 | MEMORY DEVICES WITH DIFFERENT SIZED BLOCKS OF MEMORY CELLS AND METHODS - In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes N block sizes, where N may be an integer greater than or equal to three. N−1 blocks of one block size of the N block sizes collectively include a first number of second select lines. A group of blocks consisting of a respective block of each remaining block size of the N block sizes collectively include a second number of second select lines that is equal to the first number of select lines or that is less than the first number of second select lines. | 09-11-2014 |
20140254268 | HYBRID NON-VOLATILE MEMORY CELLS FOR SHARED BIT LINE - A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements. | 09-11-2014 |
20140254269 | NON-VOLATILE STORAGE WITH SHARED BIT LINES AND FLAT MEMORY CELLS - A non-volatile storage system is disclosed that includes pairs (or another number) of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. By sharing bit lines, less bit lines are needed in the storage system. Using less bit lines reduces the space needed to implement the storage system. Each NAND string will have two drain side select gates. The non-volatile storage system will have two drain side selection lines each connected to one of the two drain side select gates so that the NAND strings sharing a bit line can be individually selected. To allow proper selection of a NAND string using the select gates, the select gates will be subjected to non-volatile programming in order to set the threshold voltage of the select gates to an appropriate level. | 09-11-2014 |
20140254270 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD OF THE SAME - A semiconductor memory device includes memory cells which are laminated on a semiconductor substrate and include charge storage layers and control gates, a plurality of word lines each of which is commonly connected to the control gates of a plurality of the memory cells, and a control unit which performs programming and verification of data in units of a page of memory cells. The control unit consecutively performs programming of data in two or more pages of memory cells connected to the same word line, and then consecutively performs verification of the data programmed in the two or more pages of memory cells connected to the same word line. | 09-11-2014 |
20140254271 | Nonvolatile Memory Device and Read Method Thereof - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 09-11-2014 |
20140269067 | TRACKING ERASE OPERATIONS TO REGIONS OF NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory. | 09-18-2014 |
20140269068 | TRACKING ERASE PULSES FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response to the count of erase pulse satisfying the erase pulse threshold, initiating a remedial action with respect to the particular region of the non-volatile memory. | 09-18-2014 |
20140269069 | TRACKING CELL ERASE COUNTS OF NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter. | 09-18-2014 |
20140269070 | Compensation For Temperature Dependence Of Bit Line Resistance - Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is in a group of blocks. A portion of the bit line extends between the group of blocks and a sense component and has a resistance which is based on the length/distance and the temperature. Various parameters can be varied with temperature and the group of blocks to provide the compensation, including bit line voltage, selected word line voltage, source line voltage, sense time and/or sense current or voltage. | 09-18-2014 |
20140269071 | PRESERVING DATA FROM ADJACENT WORD LINES WHILE PROGRAMMING BINARY NON-VOLATILE STORAGE ELEMENTS - A system and methods for programming non-volatile memory elements by using latches to transfer data. Upon discovering errors in previously programmed non-volatile memory elements, the system recovers the corresponding data from the latches and programming the recovered data to other non-volatile memory elements. | 09-18-2014 |
20140269072 | STORAGE DEVICE - According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks which store data. Each of the blocks is an erase unit. The controller controls an operation of the nonvolatile memory. The controller executes writes and erases with respect to a first block of the blocks in the nonvolatile memory for the first number of times during a first period. The controller executes writes and erases with respect to other blocks for the second number of times smaller than the first number of times during the first period. | 09-18-2014 |
20140269073 | SEMICONDUCTOR MEMORY DEVICE - An aspect of the present embodiment, there is provided a semiconductor memory device including memory cell arrays, each of the memory cell arrays including memory cells, including a clock generator configured to generate clock, an input-output circuit configured to input and output data, buses, a portion of each of the buses crossing the memory cell arrays, switches, each of the switches being placed in the bus, control circuit configured to control the switches to generate a path which transfers clock and data without overlapping with an activated memory cell as viewed from above. | 09-18-2014 |
20140286098 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory string having a plurality of electrically rewritable memory transistors connected in series therein. The memory string includes a first semiconductor layer including a columnar portion extending in a perpendicular direction to a substrate; a tunnel insulating film formed surrounding a side surface of the columnar portion; a charge storage film formed surrounding the tunnel insulating film; a block insulating film formed surrounding the charge storage film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed with a certain spacing along the perpendicular direction. The charge storage film includes a first charge storage film having a conducting property and located in contact with the tunnel insulating film; and a second charge storage film having an insulating property and formed between the first charge storage film and the block insulating film. | 09-25-2014 |
20140293692 | Memory System, Control System and Method of Predicting Lifetime - A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell, which has binary or multivalued being the binary or more is written/erased. The integration unit may records an integration value of the detected substrate current into a storage. The prediction unit may predict a lifetime of the non-volatile memory based on the integration value which is recorded on the storage. | 10-02-2014 |
20140293693 | MEMORY SYSTEM AND DRIVING METHOD THEREOF - A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape. | 10-02-2014 |
20140293694 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENTTOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line. | 10-02-2014 |
20140293695 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit. | 10-02-2014 |
20140301144 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block. | 10-09-2014 |
20140307507 | EXTENDED SELECT GATE LIFETIME - A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range. | 10-16-2014 |
20140313828 | SHARING SUPPORT CIRCUITRY IN A MEMORY - A memory device, system, and method for operation of a memory device are disclosed. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select devices are coupled to each string of memory cells. An upper drain select device shares common support circuitry (e.g., selecting/deselecting transistors) with one or more upper drain select devices of other strings of memory cells. The support circuitry (e.g., selecting/deselecting transistors) for lower drain select devices can also be shared between a plurality of strings of memory cells. | 10-23-2014 |
20140313829 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 10-23-2014 |
20140328125 | METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure. | 11-06-2014 |
20140334230 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING THE SAME - A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds the vertical channel layer, and main cell transistors coupled between the first and second select transistors. | 11-13-2014 |
20140334231 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FORERASING DATA THEREOF - A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation. | 11-13-2014 |
20140347927 | NONVOLATILE MEMORY DEVICE HAVING SPLIT GROUND SELECTION LINE STRUCTURES - A nonvolatile memory device comprises a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal. | 11-27-2014 |
20140347928 | LOW DISTURBANCE, POWER-CONSUMPTION, AND LATENCY IN NAND READ AND PROGRAM-VERIFY OPERATIONS - A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower word line disturbance for a reliable DRAM-like latch sensing. A reduced precharge voltage can be increased by M-fold (M≧2) using a Multiplier between each bitline and each Latch sense amplifier (SA). Between each Multiplier and each Latch SA, there is a Connector with two optional designs for either fully passing a sense voltage to the Latch SA with a same-polarity and value or reversing the polarity the sensing voltage with additional amplification. The Latch SA is configured to transfer stored threshold states of a memory cell into a bit of a page buffer. | 11-27-2014 |
20140347929 | APPARATUSES AND METHODS FOR TRANSPOSING SELECT GATES - Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates. | 11-27-2014 |
20140347930 | NON-VOLATIVE ELECTRONIC MEMORY DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR - A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line. | 11-27-2014 |
20140355346 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes first to N-th memory blocks, wherein N is an integer and N≧3. Each memory block, of the first to N-th memory blocks comprises first to (M−1)-th strings, wherein each string, of the first to (M−1)-th strings, includes drain-side memory cells, source-side memory cells, and a pipe transistor connecting the drain-side memory cells and the source-side memory cells, where M is an integer and M≧2, and an M-th string, including drain-side memory cells formed adjacent to the first string, of a first to (M−1)-th strings, and including source-side memory cells formed adjacent to an (M−1)-th string of the first to (M−1)-th strings. | 12-04-2014 |
20140355347 | MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION - A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells. | 12-04-2014 |
20140355348 | FLASH MEMORY SYSTEM AND WORD LINE INTERLEAVING METHOD THEREOF - Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array. | 12-04-2014 |
20140355349 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block. | 12-04-2014 |
20140355350 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 12-04-2014 |
20140369121 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area. | 12-18-2014 |
20140369122 | PSEUDO BLOCK OPERATION MODE IN 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 12-18-2014 |
20140369123 | PSEUDO BLOCK OPERATION MODE IN 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 12-18-2014 |
20140369124 | MEMORY SYSTEMS INCLUDING NONVOLATILE MEMORY DEVICES AND DYNAMIC ACCESS METHODS THEREOF - A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode. | 12-18-2014 |
20140376311 | METHOD AND APPRATUS FOR SHORTENED ERASE OPTION - A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures. | 12-25-2014 |
20150016189 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell block including a plurality of memory cells, a voltage providing unit suitable for providing a pass voltage or a read voltage to word lines coupled with the memory cells and a control circuit suitable for controlling the voltage providing unit to adjust a pass voltage applied to the memory cells disposed at one side of a selected memory cell and a pass voltage applied to the memory cells disposed at the other side of the selected memory cell based on an address of a word line of the selected memory cell among the memory cells during a read operation or a verification operation. | 01-15-2015 |
20150023101 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a low power direction received from a host device is delayed for a first predetermined time and is output as a first signal, and an internal state is caused to transition to a low power consumption mode that corresponds to the low power direction when a second predetermined time has elapsed after the first signal is asserted. | 01-22-2015 |
20150023102 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line. | 01-22-2015 |
20150029790 | NONVOLATILE MEMORY AND ERASING METHOD THEREOF - An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block. | 01-29-2015 |
20150029791 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 01-29-2015 |
20150036430 | SEMICONDUCTOR MEMORY DEVICE - A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong. | 02-05-2015 |
20150043277 | Data Storage System with Dynamic Erase Block Grouping Mechanism and Method of Operation Thereof - Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block. | 02-12-2015 |
20150049548 | Read Methods for Non-Volatile Memory Devices and Related Non-Volatile Memory Devices - Read methods for a non-volatile memory device are provided. The read method includes sensing memory cells in an Nth program state using original read voltages of an Nth level, where N is a natural number greater than 2, counting the number of memory cells in the Nth program state according to the sensing result, and when the number of memory cells in the Nth program state is greater than a reference number, sensing memory cells in first to Nth program states using adjusted read voltages of first to Nth levels. The adjusted read voltages are obtained by adding offset voltages to the original read voltages. | 02-19-2015 |
20150063026 | CONTINUOUS ADJUSTING OF SENSING VOLTAGES - The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense operations performed on a group of memory cells, and continuously adjusting a sensing voltage used to determine a state of the memory cells of the group based, at least partially, on the error rate. | 03-05-2015 |
20150063027 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor device includes a memory array including a plurality of memory cell transistors electrically connected between bit lines and source lines, wherein the memory array is partitioned into a plurality of memory blocks, and a source line driver configured to set a voltage level of the source lines to a reference voltage level. First and second wirings are respectively connected to a first monitoring position of the source lines and a second monitoring position of the source lines different from the first monitoring position. A selection circuit selects between the first and second monitoring positions. A source line voltage control circuit compares a source line voltage at a selected monitoring position, and outputs a result to the source line driver. | 03-05-2015 |
20150063028 | Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors. | 03-05-2015 |
20150070994 | SEMICONDUCTOR MEMORY DEVICE - A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks. | 03-12-2015 |
20150070995 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes an I/O circuit suitable for inputting and outputting data signals, and a control logic suitable for controlling the I/O circuit. The control logic includes a flip-flop suitable for operating in response to a dock signal, which is irrelevant to the data signals, and feed a first output signal back, a first pulse generation circuit suitable for generating a data output control pulse in response to a second output signal of the flip-flop which is an inverted signal of the first output signal, and a second circuit suitable for generating a strobe signal in response to the second output signal. | 03-12-2015 |
20150078086 | MULTI-TASK CONCURRENT/PIPELINE NAND OPERATIONS ON ALL PLANES - This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements. | 03-19-2015 |
20150078087 | CONTROL METHOD OF NONVOLATILE MEMORY DEVICE - According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block. | 03-19-2015 |
20150078088 | EXTENDED SELECT GATE LIFETIME - A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range. | 03-19-2015 |
20150085574 | Back Gate Operation with Elevated Threshold Voltage - In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming. | 03-26-2015 |
20150085575 | Multi-Word Line Erratic Programming Detection - Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members. | 03-26-2015 |
20150085576 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state. | 03-26-2015 |
20150092491 | SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD - A reliable semiconductor memory device and an erasing method for erasing data in a reliable manner are provided. The erasing method is applied to erase a semiconductor memory device having a memory array, and the memory array has an NAND string. A predetermined voltage is applied to a gate of a select transistor of the NAND string, and the predetermined voltage is applied to a word line of a memory cell of the NAND string. An erasing voltage is applied to a substrate region at a first timing, and the substrate region has the NAND string. The gate of the select transistor is floated at a second timing. Here, there is a fixed time interval between the first timing and the second timing, and the second timing is later than the first timing. | 04-02-2015 |
20150092492 | SEMICONDUCTOR DEVICE AND METHOD OF SEARCHING FOR ERASURE COUNT IN SEMICONDUCTOR MEMORY - In response to a search start instruction, a read address signal including address sequences for blocks is generated and the read address signal is provided to a block management memory to successively read sequences of erasure count data pieces corresponding to the blocks from the block management memory. Thereafter, when the erasure count data piece read from the block management memory represents an erasure count smaller than a minimum erasure count data piece, the erasure count data piece is imported and retained and outputted as the minimum erasure count data piece. Also, the read address signal is imported and retained and an address indicated by the read address signal is outputted as a minimum erasure count address. | 04-02-2015 |
20150092493 | Pseudo Block Operation Mode In 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 04-02-2015 |
20150098271 | SYSTEM AND METHOD OF STORING DATA IN A DATA STORAGE DEVICE - A method that may be performed in a data storage device includes selecting a writing order for data to be written to a set of word lines of a block of a non-volatile memory. The data is organized in pages that are ordered according to a logical page address order. The writing order is selected from at least a first order or a second order that is distinct from the first order. Stored data in the non-volatile memory written according to the first order has logical page addresses that decrease with increasing values of word line physical addresses. The method also includes writing the data to the set of word lines according to the selected writing order and storing a flag value that indicates the selected writing order. | 04-09-2015 |
20150098272 | PROGRAMMABLE PEAK-CURRENT CONTROL IN NON-VOLATILE MEMORY DEVICES - A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption. | 04-09-2015 |
20150098273 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING FAILURE-RELIEF EFFICIENCY - According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong. | 04-09-2015 |
20150109861 | SECURE MEMORY WHICH REDUCES DEGRADATION OF DATA - A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase. | 04-23-2015 |
20150117102 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS - According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells. | 04-30-2015 |
20150117103 | SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE - A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks. | 04-30-2015 |
20150124527 | Detecting Programmed Word Lines Based On NAND String Current - A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block. | 05-07-2015 |
20150124528 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor. | 05-07-2015 |
20150131378 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected to a gate electrode of the selection transistor, a driver, or a node that supplies an unselected voltage, or is set to be in a floating state. | 05-14-2015 |
20150138886 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE, AND MEMORY SYSTEM - A non-volatile semiconductor storage device includes an memory cell array including first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, and a optionally a peripheral circuit for controlling the memory cell array. In this non-volatile semiconductor storage device, n signal lines are arranged in the first block, and m (n>m, m: natural number) signal lines are arranged in the second block, such that the second block size is smaller than the first block size. | 05-21-2015 |
20150138887 | METHOD AND SYSTEM FOR IMPROVING THE RADIATION TOLERANCE OF FLOATING GATE MEMORIES - A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention. | 05-21-2015 |
20150138888 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time. | 05-21-2015 |
20150138889 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES FOR PERFORMING THE METHOD - A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation. | 05-21-2015 |
20150138890 | NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF - Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. | 05-21-2015 |
20150146487 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR ERASING THE SAME - Provided are a non-volatile memory device and a method for erasing the non-volatile memory device having vertical channel layers formed with different widths varying by height and a plurality of memory cells stacked along the vertical channel layers, the method including increasing potentials of the vertical channel layers, and when potentials of word lines connected to the memory cells are increased, erasing the memory cells while lowering the potentials of the word lines beginning from a word line positioned in an area in which a width of the vertical channel layer is wide to a word line positioned in an area in which the width of the vertical channel layer is narrow. | 05-28-2015 |
20150146488 | SEMICONDUCTOR DEVICE AND PROGRAM FAIL CELLS - A semiconductor device includes a memory block including even memory cells configured to form an even page and odd memory cells configured to form an odd page. The semiconductor device may also include an operation circuit configured to perform a program operation on the even memory cells and the odd memory cells. A first verify operation may separately verify the even memory cells and the odd memory cells, and a second verify operation may simultaneously verify the even memory cells and the odd memory cells. Further, the operation circuit may be configured to selectively perform the first verify operation and the second verify operation depending on a number of adjacent program fail cells in response to a verify result value. | 05-28-2015 |
20150294722 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group. | 10-15-2015 |
20150294724 | MEMORY DEVICES AND METHODS OF OPERATING THE SAME - According to example embodiments, a memory device includes a memory cell array, a controller including a normal program controller and a dummy program controller, and a driver. The memory cell array includes a first memory block on a substrate. The first memory block includes a plurality of cell strings on the substrate extending in a vertical direction. The normal program controller is configured to generate a first control signal for programming normal cells of a selected cell string that is selected based on an address received by the controller. The dummy program controller is configured to generate a second control signal for programming at least one dummy cell included in each of the plurality of cell strings before generation of the first control signal. The driver is configured to apply a first operation voltage set for programming the normal cells of the selected cell string to the first memory block in response to the first controller signal. The driver is configured to apply a second operation voltage set for programming the at least one dummy cell to the first memory block in response to the second control signal. | 10-15-2015 |
20150294727 | SENSING MEMORY CELLS COUPLED TO DIFFERENT ACCESS LINES IN DIFFERENT BLOCKS OF MEMORY CELLS - In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells. | 10-15-2015 |
20150302927 | NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings. | 10-22-2015 |
20150302929 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. | 10-22-2015 |
20150310923 | OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY - An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation. | 10-29-2015 |
20150325301 | NONVOLATILE MEMORY DEVICE AND ERASING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation. | 11-12-2015 |
20150325303 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes adjacent first and second blocks of memory cells, wherein all the memory cells in each block are erased collectively and each of the blocks includes a plurality of stacks of memory cells above a semiconductor substrate, a dummy cell region including a plurality of stacks of dummy cells above the semiconductor substrate, a source line contact electrically connected to an upper wiring layer and through which a voltage is applied to a source line of the memory cells, and a substrate contact electrically connected to the upper wiring layer and through which a voltage is applied to the semiconductor substrate. The source line contact is disposed between the first and second blocks, and the substrate contact is separated from any of the stacks of memory cells by at least one stack of dummy cells. | 11-12-2015 |
20150325304 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 11-12-2015 |
20150325308 | METHOD AND APPARATUS FOR CONCURRENT TEST OF FLASH MEMORY CORES - An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access. | 11-12-2015 |
20150332771 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a CSL driver, and control logic. The memory cell array includes a plurality of memory blocks each having a plurality of strings that are formed in a direction perpendicular to a substrate and are connected between bit lines and a common source line. The CSL driver sets up the common source line with a predetermined voltage and supplies or drains charge to or from the common source line using a voltage level of the common source line as a feedback signal. | 11-19-2015 |
20150332773 | THREE-DIMENSIONAL MEMORY DEVICE AND OPERATING METHOD OF A STORAGE DEVICE INCLUDING THE SAME - A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a pipe-shaped bit cost scalable (PBiCS) structure. Each of the memory blocks penetrates word lines stacked on a substrate in the form of plates and includes a first pillar, a second pillar, and a back-gate. The second pillar includes a semiconductor layer, an insulating layer, and a charge storage layer. The back-gate includes a pillar connection portion to connect the first and second pillars to each other and is disposed between the substrate and the word lines. The memory controller includes an adjacent cell management unit configured to control the at least one nonvolatile memory device such that a program operation, an erase operation or a read operation is performed on memory cells adjacent to the back-gate, unlike the other memory cells. | 11-19-2015 |
20150332783 | METHOD OF OPERATING SEMICONDUCTOR DEVICE - A method of operating a semiconductor device includes programming a first cell, verifying a second cell adjacent to the first cell, and repeating the programming of the first cell and the verifying of the second cell until the verifying of the second cell passes. | 11-19-2015 |
20150340095 | INTERCONNECTIONS FOR 3D MEMORY - Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step. | 11-26-2015 |
20150348631 | NONVOLATILE MEMORY, NONVOLATILE PROGRAMMABLE LOGIC SWITCH INCLUDING NONVOLATILE MEMORY, AND NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected. | 12-03-2015 |
20150357042 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter. | 12-10-2015 |
20150357043 | NONVOLATILE MEMORY SYSTEM AND OPERATING METHOD OF MEMORY CONTROLLER - An operating method of a memory controller configured to control a nonvolatile memory device including a plurality of memory cells is provided. The operating method includes: programming evaluation data into desired memory cells among the plurality of memory cells; performing initial verify shift (IVS) charge loss evaluation on the desired memory cells after a time elapses from a time point when the evaluation data is programmed, the IVScharge loss evaluation including an operation of detecting threshold voltage variation of the desired memory cells over a period based on the time elapsed from the time point when the evaluation data is programmed; and storing a result of the IVScharge loss evaluation; and adjusting levels of a plurality of read voltages used in the nonvolatile memory device based on the stored result of the charge loss evaluation. | 12-10-2015 |
20150357049 | SHORT-CHECKING METHODS - In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage. | 12-10-2015 |
20150364196 | ARRAY FANOUT PASS TRANSISTOR STRUCTURE - A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array. | 12-17-2015 |
20150364198 | PARTIAL BLOCK ERASE FOR A THREE DIMENSIONAL (3D) MEMORY - A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string. | 12-17-2015 |
20150364200 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines. | 12-17-2015 |
20150371710 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 12-24-2015 |
20150371713 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block. | 12-24-2015 |
20150380089 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH LINE SHARING SCHEME - A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are coupled to each other and a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines. | 12-31-2015 |
20150380093 | NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. | 12-31-2015 |
20150380096 | DYNAMIC ADJUSTMENT OF READ VOLTAGE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read. | 12-31-2015 |
20150380098 | CONTINUOUS ADJUSTING OF SENSING VOLTAGES - The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense operations performed on a group of memory cells, and continuously adjusting a sensing voltage used to determine a state of the memory cells of the group based, at least partially, on the error rate. | 12-31-2015 |
20150380101 | ERASE ALGORITHM FOR FLASH MEMORY - A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level. | 12-31-2015 |
20160005466 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a semiconductor substrate and a plurality of first dummy memory cells connected between the first main memory cells and a common source line. The second memory string includes a plurality of second main memory cells formed on the pipe transistor and a plurality of second dummy memory cells connected between the second main memory cells and a bit line. The number of the second dummy memory cells is greater than the number of the first dummy memory cells. | 01-07-2016 |
20160005468 | Reduced Size Semiconductor Device And Method For Manufacture Thereof - A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided. | 01-07-2016 |
20160005470 | SEMICONDUCTOR MEMORY DEVICE - A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks. | 01-07-2016 |
20160005472 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory block including memory cells connected to a word line, and an operation circuit suitable for consecutively applying a main program pulse and a sub program pulse to the word line to perform a program operation of the memory cells, and suitable for performing a program verification operation of the memory cells, wherein the sub program pulse has a lower voltage level than the main program pulse. | 01-07-2016 |
20160005475 | MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS - A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described. | 01-07-2016 |
20160005478 | MEMORY SYSTEM AND METHOD OF DRIVING MEMORY SYSTEM USING ZONE VOLTAGES - A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation. | 01-07-2016 |
20160005480 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level. | 01-07-2016 |
20160005755 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film. | 01-07-2016 |
20160012901 | THREE DIMENSIONAL MEMORY DEVICE AND DATA ERASE METHOD THEREOF | 01-14-2016 |
20160012903 | Segmentation of Blocks for Faster Bit Line Settling/Recovery in Non-Volatile Memory Devices | 01-14-2016 |
20160012914 | Determination of Word Line to Local Source Line Shorts | 01-14-2016 |
20160012915 | Determination of Bit Line to Low Voltage Signal Shorts | 01-14-2016 |
20160035423 | NONVOLATILE MEMORY DEVICE AND WORLDLINE DRIVING METHOD THEREOF - According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines. | 02-04-2016 |
20160035428 | NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A method for driving a nonvolatile memory device includes performing an erase operation with respect to a plurality of memory cells, stopping the erase operation by a suspend command, calculating a residual time of the erase operation that has not yet been performed, performing a first operation, comparing a first vacant time between a completion time point of the first operation and a start time point of a second operation with the residual time, performing the erase operation that has not yet been performed if the residual time is equal to or shorter than the first vacant time, and performing the second operation if the residual time is longer than the first vacant time. | 02-04-2016 |
20160035429 | MEMORY DEVICE AND READ METHOD OF MEMORY DEVICE - In a method of reading a memory device, difference information is generated based on a distance difference between a position of a read word-line and a position of a boundary word-line. The read word-line corresponds to a read address. The boundary word-line corresponds to a last programmed word-line in a memory block included in a memory cell array. A read word-line voltage and an adjacent word-line voltage are determined based on the difference information. The read word-line voltage is applied to the read word-line. The adjacent word-line voltage is applied to an adjacent word-line that is adjacent to the read word-line. A read data corresponding to the read address is outputted based on the read word-line voltage and the adjacent word-line voltage. The read method of the memory device according to example embodiments may be capable of increasing the performance by controlling the voltages applied to the adjacent word-line and the read word-line according to the difference information determined based on the read word-line and the boundary word-line. | 02-04-2016 |
20160042792 | NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF - Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. | 02-11-2016 |
20160042796 | LOW LATENCY MEMORY ERASE SUSPEND OPERATION - A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array comprises a plurality of blocks of memory cells, each block comprising a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells. | 02-11-2016 |
20160049201 | SUB-BLOCK ERASE - A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines. | 02-18-2016 |
20160049205 | RANK DETERMINATION - Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information. | 02-18-2016 |
20160054361 | ELECTRONIC APPARATUS - An electronic apparatus includes a first voltage detection circuit which detects when a voltage, becomes higher than a first level after the voltage starts to be supplied to a peripheral circuit, and detects when the voltage becomes lower than a second level after a supply of the voltage to the peripheral circuit starts to be interrupted, and a second voltage detection circuit which detects when the voltage becomes lower than a reference level while the peripheral circuit operates. The second level is lower than the reference level. | 02-25-2016 |
20160055917 | STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES - A method of operating a storage device may include receiving a read command and a read address, performing a read operation on selected memory cells corresponding to a selected string selection line and a selected word line based on the read address and performing a reliability verification read on unselected memory cells. Data read by the read operation may be output to an external device, and data read by the reliability verification read may be not output to the external device. | 02-25-2016 |
20160055918 | Zoned Erase Verify in Three Dimensional Nonvolatile Memory - In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data. | 02-25-2016 |
20160064083 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device of the inventive concept includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line. | 03-03-2016 |
20160071594 | Non-Volatile Memory with Multi-Word Line Select for Defect Detection Operations - A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks. | 03-10-2016 |
20160071612 | MEMORY SYSTEM AND MANAGEMENT METHOD THEREOF - According to one embodiment, a memory system comprises a first nonvolatile semiconductor memory, a temperature sensor and a controller. The first nonvolatile semiconductor memory includes the first and second semiconductor chips. The temperature sensor detects a temperature of the first nonvolatile semiconductor memory. The controller acquires the wear level per block of the first and second semiconductor chips based on the temperature of the first nonvolatile semiconductor memory and the frequency of use of the first nonvolatile semiconductor memory, and sets, based on the wear level, an examination frequency for defining a cycle of examination of quality of data per block of the first and second semiconductor chips. | 03-10-2016 |
20160078939 | APPOINTING SEMICONDUCTOR DICE TO ENABLE HIGH STACKING CAPABILITY - Briefly, in accordance with one or more embodiments, a memory array comprises two or more volumes, the volumes comprising two or more dice, respectively. The volumes are connected in a daisy chain configuration such that an output of a first volume is coupled to an input of a next volume, and the dice are connected in a daisy chain configuration such that an output of a first die is coupled to an input of a next die within the volume. In such a configuration, a first die in a first volume is capable of being appointed as part of a second volume. | 03-17-2016 |
20160078940 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes first word lines equipped with flag-like portions on one side of the block in the row direction and equipped with no flag-like portions on the other side of the block in the row direction, and second word lines equipped with no flag-like portions on the one side of the block in the row direction and equipped with flag-like portions on the other side of the block in the row direction. | 03-17-2016 |
20160078942 | OPERATING CHARACTERISTICS OF A SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes memory blocks including select transistors electrically coupled to local select lines and memory cells electrically coupled to local word lines, a first connection circuit configured to electrically couple the local select lines of a selected memory block and global select lines according to a block select signal, and formed in a first well region of a substrate, and a second connection circuit configured to electrically couple the local word lines of the selected memory block and global word lines according to the block selection signal, and formed in a second well region of the substrate. | 03-17-2016 |
20160078954 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell. When data is read from the first memory cell, a first voltage and a second voltage is applied to the first word line. A voltage of the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage changes a second number of times different from the first number of times while the second voltage is applied to the first word line. | 03-17-2016 |
20160078955 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 03-17-2016 |
20160078958 | Single Ended Word Line and Bit Line Time Constant Measurement - In non-volatile memories, bit lines and word lines commonly to driving and decoding circuitry on a single end. Techniques are presented for determining the time constant associated with charging the far end of such lines from the near end, at which the circuitry is connected. While driving a discharged line from the near end, the number of clock cycles for the current to drop from a first level to a second level can be used to estimate the time constant for the far end. Alternately, the line can be initially charged up, after which the current is monitored at the near end. The differences in time constants for different word lines can be used to vary the time used when accessing a selected word line. | 03-17-2016 |
20160086669 | NONVOLATILE MEMORY DEVICE WITH IMPROVED VOLTAGE DROP AND METHOD OF DRIVING THE SAME - A nonvolatile memory device includes a block switching unit which transmits an operation signal to a memory cell array, and a voltage sustaining block which provides a voltage to sustain the operation signal to an arbitrary interconnection overlapping the block switching unit. | 03-24-2016 |
20160086671 | Utilizing NAND Strings in Dummy Blocks for Faster Bit Line Precharge - In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current. | 03-24-2016 |
20160093386 | MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION - A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells. | 03-31-2016 |
20160093387 | METHOD OF OPERATING A MEMORY SYSTEM HAVING AN ERASE CONTROL UNIT - A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition. | 03-31-2016 |
20160099055 | EPROM CELL ARRAY, METHOD OF OPERATING THE SAME, AND MEMORY DEVICE INCLUDING THE SAME - A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a Q | 04-07-2016 |
20160099060 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A DUMMY MEMORY CELL AND METHOD OF PROGRAMMING THE SAME - A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell. The semiconductor memory device may include a voltage generator configured for generating a program voltage applied to a normal memory cell selected among the plurality of normal memory cells, and for generating a dummy word line voltage applied to the dummy memory cell in a program operation. The semiconductor memory device may include a control logic configured for controlling the voltage generator to adjust the dummy word line voltage based on the program voltage. | 04-07-2016 |
20160099061 | FAST SECURE ERASE IN A FLASH SYSTEM - A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse. | 04-07-2016 |
20160104533 | APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES - Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations. | 04-14-2016 |
20160111160 | APPARATUSES AND METHODS FOR SEGMENTED SGS LINES - Apparatuses and methods for segmented SGS lines are described. An example apparatus ma include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memos subblocks. | 04-21-2016 |
20160111164 | Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory - Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized. | 04-21-2016 |
20160111165 | METHODS OF OPERATING A NONVOLATILE MEMORY DEVICE - An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed. | 04-21-2016 |
20160111167 | APPARATUSES AND METHODS FOR REDUCING READ DISTURB - Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion. | 04-21-2016 |
20160118123 | NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, OPERATING METHOD THEREOF - An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the selected block, determining whether the memory block shares a block word line with the selected block. The method further includes applying an unselected block word line voltage to word lines of the memory block when the memory block shares the block word line with the selected block, and floating the word lines of the memory block when the memory block does not share the block word line with the selected block. | 04-28-2016 |
20160118125 | COMPACTION PROCESS FOR A DATA STORAGE DEVICE - A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process. | 04-28-2016 |
20160125945 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 05-05-2016 |
20160125946 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value. | 05-05-2016 |
20160125949 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device includes applying a read voltage to a selected word line of a selected memory block, among a plurality of memory blocks including cell strings coupled between bit lines and a source line, detecting a voltage of the source line by forming a channel in cell strings of the selected memory block, comparing the voltage of the source line with a reference voltage corresponding to the selected memory block, and performing a least significant bit (LSB) read operation on memory cells coupled to the selected word line when the voltage of the source line is greater than the reference voltage, as a result of the comparing, and performing a most significant bit (MSB) read operation on the memory cells when the voltage of the source line is less than the reference voltage, as the result of the comparing. | 05-05-2016 |
20160133326 | APPARATUSES AND METHODS FOR NON-VOLATILE MEMORY PROGRAMMING SCHEMES - Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. The control unit may be configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks during the program operation responsive to programming the first access line group of each of the plurality of subblocks. | 05-12-2016 |
20160133329 | OPERATING METHOD FOR NONVOLATILE MEMORY AND OPERATING METHOD FOR STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY - An operation method of a storage device including a nonvolatile memory and a memory controller controlling the nonvolatile memory, includes transmitting a multi-program command to the nonvolatile memory by the memory controller; and programming memory cells connected to two or more word lines by the nonvolatile memory in response to the multi-program command. | 05-12-2016 |
20160141034 | Transistor Design For Use In Advanced Nanometer Flash Memory Devices - Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed. | 05-19-2016 |
20160141035 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed. | 05-19-2016 |
20160141041 | Partial Erase of Nonvolatile Memory Blocks - Erasing blocks of a nonvolatile memory may include two erase steps. A first erase step brings the memory cells of a block to an intermediate state between their programmed states and an erased state. The block is then maintained with the memory cells in the intermediate state for a period of time. Subsequently, a second erase step on the block brings the memory cells from the intermediate state to the erased state | 05-19-2016 |
20160141042 | CONFIGURATION PARAMETER MANAGEMENT FOR NON-VOLATILE DATA STORAGE - Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage differences in one or more storage characteristics for blocks of a non-volatile memory medium within one or more established limits. A block classification module is configured to group blocks of a non-volatile memory medium based on one or more other storage characteristics. A configuration parameter module is configured to use a configuration parameter for at least one group of blocks based on a grouping. A configuration parameter update module is configured to update a configuration parameter for at least one group in response to a change in one or more managed storage characteristics. | 05-19-2016 |
20160141043 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. The semiconductor device may include an operation circuit configured to perform an operation on memory cells included in the memory strings. The bit lines may be classified into a plurality of groups. The operation circuit may be configured to apply a voltage to bit lines of a selected group and set the common source line to a voltage level for the operation. | 05-19-2016 |
20160141044 | CONFIGURATION PARAMETER MANAGEMENT USING A CONFIGURATION TOOL - Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. An initialization module is configured to initialize a value for a configuration parameter for a set of cells of a non-volatile memory medium. The initialization module may initialize the configuration parameter value based on a predetermined model for the set of cells. An update module is configured to adjust the configuration parameter using an existing function of the non-volatile memory medium. The existing function may use the initialized value to adjust the configuration parameter. The update module may adjust the configuration parameter in response to a trigger. An access module is configured to access the set of storage cells using the adjusted configuration parameter. | 05-19-2016 |
20160141045 | NONVOLATILE MEMORY DEVICE, ERASE METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - An erase method of a nonvolatile memory device including a plurality of cell strings on a substrate is provided. Each string includes a plurality of memory cells stacked in a direction perpendicular to the substrate, a ground select transistor between the memory cells and the substrate, and string select transistors between the memory cells and a bit line. The erase method includes applying a precharge voltage during a first time to a first string select line, floating the first string select line during a second time after the first time, and applying an erase voltage to the substrate after the first time. The first string select line is connected to the string select transistors at a first height in the cell strings of a same row | 05-19-2016 |
20160148690 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - The present invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device may include at least two memory blocks sharing a row decoder, and a peripheral circuit performing a read operation on a selected memory block, between the at least two memory blocks, wherein the peripheral circuit applies a discharge voltage to an unselected memory block, between the at least two memory blocks, for a preset time after a period in which a read voltage is applied to the selected memory block is terminated. | 05-26-2016 |
20160148693 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device may include a memory block including memory cells, the memory cells connected to a word line. The semiconductor device may include an operation circuit configured to apply a preprogram pulse to the word line, and to perform a main program loop including a main program operation and a program verification operation to store data in the memory cells connected to the word line. The preprogram pulse may have a higher voltage level than a first main program pulse applied to the word line when the main program operation is first performed. | 05-26-2016 |
20160148697 | Compact Non-Volatile Memory Device - A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells. | 05-26-2016 |
20160148699 | AUTOMATIC PROGRAM OF NON-VOLATILE MEMORY AND AUTOMATIC CYCLING METHOD THEREOF - Disclosed is a memory test method including receiving a memory test command, receiving pattern information for generating a data pattern to be written in a memory cell, and programming the memory cell according to the pattern information. According to this method, it is not required to receive external data to be programmed in a cell array. | 05-26-2016 |
20160148703 | OPERATION METHOD OF NONVOLATILE MEMORY SYSTEM - An operation method of a nonvolatile memory system in accordance with example embodiments of inventive concepts includes detecting an on-cell count of the memory cells using a sampling start voltage, comparing the detected on-cell count with a reference value, setting a plurality of sampling voltages based on the comparison result, performing a sampling operation with respect to the memory cells using the sampling voltages, and detecting an optimum read voltage for distinguishing any one program state among the program states based on a result of the sampling operation. | 05-26-2016 |
20160155508 | Reduced Size Semiconductor Device And Method For Manufacture Thereof | 06-02-2016 |
20160163390 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. The semiconductor device further includes an operation circuit configured to apply an operating voltage to a memory block selected to perform program and read operations, and a gate control circuit configured to control a gate of the pipe transistor included in an unselected memory block. | 06-09-2016 |
20160163394 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR READING DATA FROM THE SAME - A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state. | 06-09-2016 |
20160172042 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME | 06-16-2016 |
20160172044 | Method To Recover Cycling Damage And Improve Long Term Data Retention | 06-16-2016 |
20160172046 | STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES | 06-16-2016 |
20160172047 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF | 06-16-2016 |
20160180934 | APPARATUS, SYSTEMS, AND METHODS TO OPERATE A MEMORY | 06-23-2016 |
20160180935 | VOLTAGE SWITCHING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | 06-23-2016 |
20160180940 | SEMICONDUCTOR DEVICE | 06-23-2016 |
20160180942 | STORAGE DEVICE, NONVOLATILE MEMORY AND METHOD OPERATING SAME | 06-23-2016 |
20160180946 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME | 06-23-2016 |
20160180951 | MEASURING MEMORY WEAR AND DATA RETENTION INDIVIDUALLY BASED ON CELL VOLTAGE DISTRIBUTIONS | 06-23-2016 |
20160180953 | PREDICTING MEMORY DATA LOSS BASED ON TEMPERATURE ACCELERATED STRESS TIME | 06-23-2016 |
20160180955 | SEMICONDUCTOR DEVICE AND SEARCH CIRCUIT FOR AND METHOD OF SEARCHING FOR ERASURE COUNT IN SEMICONDUCTOR MEMORY | 06-23-2016 |
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