Class / Patent application number | Description | Number of patent applications / Date published |
345552000 | Texture memory | 23 |
20080204466 | DYNAMIC CONFIGURABLE TEXTURE CACHE FOR MULTI-TEXTURING - Techniques for dynamically configuring a texture cache are disclosed. During a texture mapping process of a three-dimensional (3D) graphics pipeline, if the batch is for single texture mapping, the texture cache is configured as a n-way set-associative texture cache. However, if the batch is for multi-texture mapping the n-way set-associated texture cache is divided into at n/M-way set-associative sub-caches where n and M are integers greater than 1 and n is divisible by M. | 08-28-2008 |
20080211823 | Three-dimensional graphic accelerator and method of reading texture data - A three-dimensional (3D) graphic accelerator accessing an external memory storing a plurality of texture data is provided. The 3D graphic accelerator may include a texture cache storing the texture data, a geometry processing unit generating texture status information, and a texture processing unit generating a texture address to access the texture cache and outputting one or more texels from the texture data of the texture cache. The texture cache receives the texture address from the texture processing unit and generates a control signal for reading a part or all of a series of texture data from the external memory in accordance with the texture status information when a cache miss occurs. | 09-04-2008 |
20080211824 | Portable communication terminal - There is provided a portable communication terminal capable of switching between icon display and non-display. Processes executed by a control unit of a portable phone which is an aspect of the portable communication terminal comprises the steps of detecting, during the execution of an icon-bar displaying process, a press of an operation key, terminating outputting icon data if the operation key is associated with the icon-bar non-display function and if there is already no icon bar being displayed, detecting a press of the operation key, and executing the icon-bar displaying process if the operation key is associated with the icon-bar display function and if there is no icon bar being displayed. | 09-04-2008 |
20090128575 | Systems and Methods for Managing Texture Descriptors in a Shared Texture Engine - Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values. | 05-21-2009 |
20090284538 | VIDEO STREAMING DATA PROCESSING METHOD - A video streaming data processing method is used in a video streaming data processing system including a central processing unit, a system memory, a graphic processing unit and a video random-access memory. After video streaming data are received, a video decoding operation is performed on the video streaming data by the central processing unit to produce image data and the image data are then stored into the system memory. Next, the image data are stored from the system memory to a texture buffer of the video random-access memory. Next, the image data that are stored in the texture buffer are read out and subject to a specific image processing algorithm by the graphic processing unit, and then stored back to the texture buffer. Afterwards, the image data are stored from the texture buffer to a video buffer of the video random-access memory. | 11-19-2009 |
20090295815 | GRAPHICS DISPLAY SYSTEM WITH WINDOW DESCRIPTORS - A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided. | 12-03-2009 |
20100110091 | Apparatus and method of reading texture data for texture mapping - An apparatus and method of reading texture data for texture mapping. Each of a plurality of blocks included in a cache memory may have any one of an even numbered index or odd numbered index. In this instance, the cache memory may be embodied with an odd numbered index cache memory including odd numbered index blocks and an even numbered index cache memory including even numbered index blocks. Also, address indexes of requested texture data may be analyzed to appropriately access to at least one of the odd numbered index cache memory and even numbered index cache memory, thereby improving an accessing speed. | 05-06-2010 |
20110063318 | Image Loads, Stores and Atomic Operations - One embodiment of the present invention sets forth a method for accessing texture objects stored within a texture memory. The method comprises the steps of receiving a texture bind request from an application program, wherein the texture bind request includes an object identifier that identifies a first texture object stored in the texture memory and an image identifier that identifies a first image unit, binding the first texture object to the first image unit based on the texture bind request, receiving, within a shader engine, a first shading program command from the application program for performing a first memory access operation on the first texture object, wherein the memory access operation is a store operation or atomic operation to an arbitrary location in the image, and performing, within the shader engine, the first memory access operation on the first texture object via the first image unit. | 03-17-2011 |
20110069076 | REGISTER INDEXED SAMPLER FOR TEXTURE OPCODES - One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler. | 03-24-2011 |
20110148894 | DEMAND-PAGED TEXTURES - A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image. | 06-23-2011 |
20110169850 | BLOCK LINEAR MEMORY ORDERING OF TEXTURE DATA - A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob. | 07-14-2011 |
20130033513 | TEXTURE COMPRESSION AND DECOMPRESSION - Embodiments relate to compression and decompression of textures. A texel block ( | 02-07-2013 |
20130194288 | METHOD AND APPARATUS FOR STORING INFORMATION OF A PICTURE - Disclosed are method and apparatus for storing information of a picture. The method includes presenting a picture file to be edited, which at least includes original picture data; editing the picture file with an interface engine; integrating rendering information of the edited picture file according to a preset picture file format; and storing the original picture data and the rendering information. According to the invention, the interface engine is improved, and thus may directly edit a picture in use, and integrate the rendering information of the edited picture file according to a preset picture format. Therefore, during development, it is not required to store rendering information of a picture into codes, so that no programmer is required to intervene in rendering and setting of the picture. An art-designer may directly operate on the interface engine to change rendering effects, meanwhile, final rendering effects may be observed without running a program. | 08-01-2013 |
20130342553 | TEXTURE MAPPING TECHNIQUES - Improved techniques for texture mapping are described. In one embodiment, for example, a host may include a processor circuit and a graphics management module, and the graphics management module may be operable by the processor circuit to determine that a texture value corresponding to a texture coordinate is unavailable, determine a marginal texture coordinate corresponding to the texture coordinate, determine a marginal texture value corresponding to the marginal texture coordinate, and store the marginal texture value in a memory unit. Other embodiments are described and claimed. | 12-26-2013 |
20140092114 | SYSTEM AND METHOD FOR DEADLOCK-FREE PIPELINING - A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance. | 04-03-2014 |
20140327688 | GRAPHICS PROCESSING SYSTEMS - A tile-based graphics processing pipeline comprising a rasteriser | 11-06-2014 |
20140368521 | GRAPHICS PROCESSING SYSTEMS - A tile-based graphics processing pipeline comprising a rasteriser | 12-18-2014 |
20150049104 | RENDERING TO MULTI-RESOLUTION HIERARCHIES - One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques. | 02-19-2015 |
20150070371 | TECHNIQUES FOR REDUCING ACCESSES FOR RETRIEVING TEXTURE IMAGES - Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed. | 03-12-2015 |
20150084975 | LOAD/STORE OPERATIONS IN TEXTURE HARDWARE - Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption. | 03-26-2015 |
20150097851 | APPROACH TO CACHING DECODED TEXTURE DATA WITH VARIABLE DIMENSIONS - A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map. | 04-09-2015 |
20150109315 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MAPPING TILES TO PHYSICAL MEMORY LOCATIONS - A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table. | 04-23-2015 |
20150130826 | LAND GRID ARRAY SOCKET FOR ELECTRO-OPTICAL MODULES - For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory. | 05-14-2015 |