Class / Patent application number | Description | Number of patent applications / Date published |
327544000 | Power conservation or pulse type | 83 |
20080197915 | SEMICONDUCTOR DEVICE CHIP, SEMICONDUCTOR DEVICE SYSTEM, AND METHOD - A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode. | 08-21-2008 |
20080204124 | Fine-Grained Power Management of Synchronous and Asynchronous Datapath Circuits - A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a first logic state and a second logic state. The detector generates a control signal indicative of whether or not a transition of the first input signal has occurred. The power management circuit further includes a controller operative to receive the first control signal generated by the detector and to selectively disconnect the first combinational logic circuit from a power supply to the first combinational logic circuit when no logic transition of the first input signal is detected between a preceding computational cycle and a present computational cycle of the first combinational logic circuit, and to connect the first combinational logic circuit to the power supply when a logic transition of the first input signal is detected. | 08-28-2008 |
20080204125 | Internal voltage generator - An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage node to apply the internal voltage to the internal voltage node in response to a voltage level of the first node, and/or a leakage current interrupting portion to apply an external voltage to the first node to deactivate the internal voltage driving portion and to interrupt the external voltage applied to the driving node to interrupt a leakage current. | 08-28-2008 |
20080231352 | Adjusting PLL/analog supply to track CPU core supply through a voltage regulator - A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core. | 09-25-2008 |
20080272834 | Absolute Multi-Revolution Encoder - To reduce the consumption current of the backup power supply of an absolute multi-revolution encoder thereby to elongate the life time of the backup power supply. | 11-06-2008 |
20080272835 | Interrupt/Wake-Up of an Electronic Device in a Low Power Sleep Mode When Detecting a Sensor or Frequency Source Activated Frequency Change - Activation of an external sensor coupled to an electronic device will change the frequency of a low power oscillator in the electronic device that runs during a low power sleep mode of the electronic device. When a change in frequency of the low power oscillator is detected, the electronic device will wake-up from the low power sleep mode. In addition, when a change in frequency from an external frequency source is detected, the electronic device will wake-up from the low power sleep mode. | 11-06-2008 |
20080272836 | Interrupt/Wake-Up of an Electronic Device in a Low Power Sleep Mode When Detecting a Sensor or Frequency Source Activated Frequency Change - Activation of an external sensor coupled to an electronic device will change the frequency of a low power oscillator in the electronic device that runs during a low power sleep mode of the electronic device. When a change in frequency of the low power oscillator is detected, the electronic device will wake-up from the low power sleep mode. In addition, when a change in frequency from an external frequency source is detected, the electronic device will wake-up from the low power sleep mode. | 11-06-2008 |
20080278226 | METHOD AND APPARATUS FOR POWERING DOWN ANALOG INTEGRATED CIRCUITS - A method and an apparatus powers down an analog integrated circuit. A power down circuit is electrically coupled to the analog circuit and is adapted to power down the analog circuit in response to receiving a power down signal. A node protection circuit is electrically coupled to the analog circuit and is adapted to provide a predetermined voltage potential to at least one predetermined node in the analog circuit in response to receiving the power down signal when a voltage potential at the at least one predetermined node is not determined by the power down circuit. | 11-13-2008 |
20080284504 | SEMICONDUCTOR INTEGRATED CIRCUIT - This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET. | 11-20-2008 |
20080290935 | APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLTAGE DOMAIN IS POWERED DOWN - An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down. | 11-27-2008 |
20090009238 | Semiconductor integrated circuit - Disclosed herein is a semiconductor integrated circuit including a stoppable circuit unit configured to be alternately switched between a stopped state and an operating state; a first voltage line configured to apply a first voltage to the stoppable circuit unit when the stoppable circuit unit is in the operating state; a second voltage line configured to apply the first voltage to the stoppable circuit unit when the stoppable circuit unit is in a transient state of switching from the stopped state to the operating state; and a third voltage line configured to apply a second voltage to the stoppable circuit unit. | 01-08-2009 |
20090015321 | Circuit having a Local Power Block for Leakage Reduction - A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion. | 01-15-2009 |
20090027114 | Semiconductor integrated circuit and activation method of the same - Disclosed herein is a semiconductor integrated circuit including, a circuit section, a first voltage line, a second voltage line, a third voltage line, a switch section, and a control section. | 01-29-2009 |
20090039952 | System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 02-12-2009 |
20090058515 | SEMICONDUCTOR DEVICE, INFORMATION PROCESSING APPARATUS AND POWER SUPPLY VOLTAGE VARIATION SUPPRESSING METHOD - According to one embodiment, a semiconductor device includes an internal circuit which is driven by a power supply voltage and is set in one of a first state and a second state in which an amount of current consumed by the internal circuit is greater than in the first state, and a wait control module. The wait control module detects that a state of the internal circuit has transitioned from the first state to the second state, and executes a wait control process of outputting an operation start instruction signal to the internal circuit after passing of a predetermined wait time from the detection of the transition of the state of the internal circuit from the first start to the second state. | 03-05-2009 |
20090058516 | SENSOR APPARATUS HAVING SENSOR ELEMENT - A sensor apparatus is disclosed. A sense circuit is provided to convert inputted physical quantity to electrical signal. An amplifier amplifies an analog signal outputted from the sense circuit. An AID converter converts the output signal of the amplifier to digital data. A sensing interval setup unit sets a sensing interval for the sense circuit. A power supply unit supplies electric power to the sense circuit, the amplifier and the A/D converter. The amplifier and the A/D converter constitute an analog signal processing unit. A power supply control unit is provided to control the power supply unit. A storage unit stores the digital data outputted from the A/D converter every sensing interval of the sensing interval. A data value change judgment unit changes the setup of the sensing interval by the sensing interval setup unit. The data value change judgment unit also changes the control mode of the power supply control unit in response to judgment of value change between a plural number of digital data which are designated from the digital data being stored in the storage unit. | 03-05-2009 |
20090072894 | Semiconductor integrated circuit and method of controlling the same - In related arts, a body voltage needs to be controlled by separately detecting external environment such as temperature. In the related art, variation such as a process parameter for each individual product has not been considered. A semiconductor integrated circuit according to the present invention includes a comparator comparing a leak current of a first conductive type transistor with a leak current of a second conductive type transistor to output a comparing result, and a conduction control signal generator outputting a signal determining a conduction state of the first conductive type transistor and a conduction state of the second conductive type transistor in a power saving control target circuit in a power saving mode based on the comparing result. | 03-19-2009 |
20090085655 | Power supply circuit with stand-by control circuit and energy storage circuit - An exemplary power supply circuit configured for supply power for a load includes: a main power supply configured for converting received voltages into required direct current voltages; a microprocessor configured for providing control signals; a stand-by control circuit configured for controlling the main power supply; an energy storage circuit configured for supplying the stand-by control circuit. When the load stops operating, the microprocessor outputs a control signal to the stand-by control circuit, the stand-by control circuit outputs a corresponding control signal to turn off the main power supply. In response to when the load starts operating, the stand-by control circuit outputs a corresponding control signal to turn on the main power supply, and the main power supply charges the energy storage circuit. | 04-02-2009 |
20090096512 | Standby modes for integrated circuit devices - An integrated circuit device comprises an internal pull up current source Ipup and a pull up resistor Rpup connected in parallel between a voltage supply pin Vs and an output node OUT. A standby switch SBY is connected in series with the pull up resistor Rpup. The standby switch SBY is controlled by a standby detect means SBY Detect, which is also connected to the output node OUT. If it is desired to switch the device to standby mode, the output node OUT is externally drawn to ground by microprocessor | 04-16-2009 |
20090096513 | Multiple circuit blocks with interblock control and power coservation - A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off. | 04-16-2009 |
20090108920 | ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS COMPLEMENTARY NODES - An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states. | 04-30-2009 |
20090108921 | Timing Control circuit with power-saving function and method thereof - A timing control circuit with a power-saving function includes a receiving circuit, a processor, and a first switch. The receiving circuit receives a first set of differential signals for generating a set of command signals. The processor is coupled to the receiving circuit and generates a first control signal according to the set of command signals. The switch is coupled between the receiving circuit and the processor for selectively decoupling the receiving circuit from a first power supply according to the first control signal. | 04-30-2009 |
20090121784 | POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME - A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal. | 05-14-2009 |
20090146734 | Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits - In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground node between the second circuit block and the second sleep transistor, and a transmission gate (TG) or a pass transistor connecting the first virtual ground node to the second virtual ground node to enable charge recycling between the first circuit block and the second circuit block during transitions by the first circuit block from active mode to sleep mode and the second circuit block from sleep mode to active mode or vice versa. | 06-11-2009 |
20090153236 | POWER CONTROL CIRCUIT WITH LOW POWER CONSUMPTION - The available battery power on autonomously powered mobile electronic devices, in particular smartcards, is very small but requires a very long shelf life. Thus, even very small rest currents are a big power issue. The invention discloses a power save circuit and method, where a single power switch, e.g. a FET or a MEM switch, can be used to detach the power supply (?) from the whole system and allow the lowest current possible. Further, a combination with a double action button and integration of the power switch provides a solution with a minimum number of components and interconnects. An option for “system wake-up at any button” enables additional power saving during use, without inconvenience to the user. | 06-18-2009 |
20090160541 | Digital Photo Frame with Power Saving Function and Related Power Saving Method - A digital photo frame having power saving functions includes a display panel, a power generation unit for switching a system power according to a power control signal, a user detection unit installed on the display panel for detecting whether a user exists within a specific range to generate a user detection signal, a central processing unit for adjusting backlight intensity of the display panel when the system power is provided by the power generation unit according to the user detection signal and for generating a power switch-off signal when the backlight intensity of the display panel is turned off according to the user detection signal, and a power control unit for generating the power control signal to switch off the system power when the backlight intensity of the display panel is adjusted to be switched off according to the power switch-off signal. | 06-25-2009 |
20090174469 | Sizing and Placement of Charge Recycling (CR) Transistors in Multithreshold Complementary Metal-Oxide-Semiconductor (MTCMOS) Circuits - In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both. | 07-09-2009 |
20090184758 | Semiconductor integrated circuit and switch arranging and wiring method apparatus - A semiconductor integrated circuit includes: a circuit block having a first power supply line to which one of a power supply voltage and a reference voltage is applied, an internal voltage line, and a circuit cell connected between the first power supply line and the internal voltage line; and a plurality of switch cells each including two voltage cell lines each connected electrically to the internal voltage line, two power cell lines each connected electrically to a second power supply line to which another of the power supply voltage and the reference voltage is applied, a control cell line electrically connected to a switch control line, and a transistor electrically connected between the internal voltage line and the second power supply line. | 07-23-2009 |
20090189685 | Leakage Control - In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node. | 07-30-2009 |
20090189686 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER CONTROL METHOD - Each of computing units on a semiconductor integrated circuit includes a first signal output unit that outputs a first status signal indicating a state of a input/output control unit with regard to an access to a storage unit, a second signal output unit that outputs a second status signal indicating a state of a process control unit with regard to an access to a processing unit, and a power control unit that control ON and OFF of power of the storage unit and the processing unit based on states of the first status signal and the second status signal. | 07-30-2009 |
20090201082 | INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION - A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands. | 08-13-2009 |
20090219084 | Device for Optimising the Energy Consumption of an Electric Circuit Component - An apparatus for optimizing power consumption of an electrical circuit component in an operating- and evaluating-circuit of a two-conductor field device, wherein a control unit is provided, which switches the electrical circuit component with a clock signal. An energy supply unit is provided for supplying the circuit component with energy, and wherein at least one energy-storing component is connected to at least one output, at least one input and/or a supply input of the electrical circuit component. The apparatus provides for a field device, a suitable electronics for enabling improvement of the energy budget of the evaluating- and operating-circuit, especially its circuit component. | 09-03-2009 |
20090251205 | Power supply circuit having standby detection circuit - A power supply circuit includes a voltage output controller configured for outputting voltages, a standby controller configured for directing the voltage output controller to provide voltage to a load, and a microprocessor configured for controlling the standby controller according to a mode of the load. The voltage output controller is applied with a direct current voltage. When the load enters active mode from a powered off mode, the standby controller sends a control signal to the voltage output controller to output direct current voltage to the load and the microprocessor. When the load enters standby mode from the active mode, the microprocessor directs the standby controller to prevent the voltage output controller from outputting direct current voltage to the load and the microprocessor. | 10-08-2009 |
20090267686 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block. | 10-29-2009 |
20090289698 | ULTRA LOW POWER WAKE-UP CIRCUIT - An apparatus for selectively enabling power including a power supply, and a device having a controller and an input activated by a user. The controller is selectively powered by the power supply. While the device is in a sleep state, a sensing circuit senses activation of the input by the user and enables the power supply to provide power to the controller in response to the sensed activation of the input by the user. A latch circuit causes the power supply to continue to provide power to the controller. The controller is responsive to the sensed activation of the input by the user for enabling the latch circuit and for disabling the latch circuit, thereby reentering the device into a sleep state. | 11-26-2009 |
20090295467 | CIRCUITRY AND METHOD FOR BUFFERING A POWER MODE CONTROL SIGNAL - A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal. | 12-03-2009 |
20090295468 | System for minimizing the power consumption of a device in a power down mode - A system is disclosed for reducing power drain of a component when the component is in a powered down state. The system comprises a power input configured to receive power, a power output to the component, monitor logic configured to monitor a level of power moving between the input and output, and control logic configured to control power transfer between the input and output. The control logic may be in communication with the monitor logic and configured to selectively restrict power flow between the input and output when the monitor logic senses that power flow between the input and output falls below a threshold level. A method comprises checking a power level between the input and output, and if the power level exceeds a threshold, then permitting substantially unrestricted power flow. If the power level is less than the threshold, then restricting the power level between the input and output. | 12-03-2009 |
20090295469 | PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION - A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10 | 12-03-2009 |
20100013551 | Systems and Methods for Controlling Power Consumption in Electronic Devices - A method of controlling power consumption in an electronic device may include selecting between an on mode of the electronic device in which first circuitry of the electronic device is configured to perform a first operation, an off/standby mode in which second circuitry of the electronic device is configured to perform a second operation, and a sleep/vacation mode in which the second circuitry is controlled to at least one of reduce a frequency of and suspend performance of the second operation. An electronic device may include: first circuitry configured to perform a first operation when the electronic device is in an on mode; second circuitry configured to perform a second operation when in an off/standby mode; and a circuitry controller configured to control the second circuitry to at least one of reduce a frequency of and suspend performance of the second operation when in a sleep/vacation mode. | 01-21-2010 |
20100019836 | INTEGRATED CIRCUIT AND A METHOD FOR RECOVERING FROM A LOW-POWER PERIOD - An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period. The first portion of the power grid is characterized by intrinsic capacitance that is larger that the intrinsic capacitance of the second portion of the power grid. | 01-28-2010 |
20100019837 | SYSTEM AND METHOD FOR POWER MANAGEMENT - A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state. | 01-28-2010 |
20100026380 | Reference Generating Apparatus and Sampling Apparatus Thereof - A reference generating apparatus and a sampling apparatus thereof are provided. The coding module is configured to code and decode a first reference signal to retrieve a second reference signal with less power than generating the first reference signal. The second reference signal is identical to the first reference signal in amplitude. | 02-04-2010 |
20100026381 | POWER SAVING CIRCUIT FOR PWM CIRCUIT - The present invention provides a power saving circuit for PWM circuit. The power saving circuit is utilized to control at least one internal circuit. The power saving circuit comprises a switching circuit which generates a switching signal. The power saving circuit controls the internal circuit in response to the switching. The power saving circuit disables the internal circuit for power saving when the switching signal is disabled. | 02-04-2010 |
20100026382 | External accessory to be attached to electronic apparatus and system - An external accessory that can be attached to and detached from an electronic apparatus equipped with a power source unit includes: a first power receiving unit that receives power from the power source unit of the electronic apparatus; a second power receiving unit that receives power from the power source unit of the electronic apparatus; a decision-making unit that makes a decision as to whether or not the first power receiving unit is receiving power; a function execution unit that executes a predetermined function by using power received at one of the first power receiving unit and the second power receiving unit; and a control unit that engages the function execution unit in operation continuously when an affirmative decision is made by the decision-making unit, and engages the function execution unit in operation intermittently when a negative decision is made by the decision-making unit. | 02-04-2010 |
20100079201 | Automated sleep sequence - An analog baseband, a computer readable medium, and a method for powering on and off a set of regulators in the analog baseband, where each regulator is configured to provide a predefined voltage. The method includes storing in a register of the analog baseband at least n bits, where n is an integer larger than 2, assigning in the analog baseband, to each regulator, a number of m bits of the n bits, where m times a number of the regulators is smaller than or equal to n, programming in the analog baseband the at least n bits in a sequence of m bits that describes a time when each regulator is powered on or off and an order in which each regulator is powered on or off upon reception of a sleep signal, receiving in the analog baseband the sleep signal that indicates whether the set of regulators are powered on or off, and instructing, based on sequence of m bits stored in the registers of the analog baseband, the set of regulators to power on or off based on the received sleep signal. | 04-01-2010 |
20100079202 | A/D CONVERTER - An A/D converter provides one or more operational amplifiers as components. The A/D converter includes a current controlling unit that is activated before an actual operation of the A/D converter to control a current of at least one of the operational amplifiers based on a settling characteristic of the operational amplifier. | 04-01-2010 |
20100097130 | DEVICE HAVING CIRCUIT CAPABLE OF INTERMITTENT OPERATION - A circuit unit is provided. The circuit unit has an intermittent operation circuit. The intermittent operation circuit is set in an operation state and in a stand-by state periodically. An operation mode control unit generates a test mode control signal to designate either an operation test mode or an intermittent operation test mode of the intermittent operation circuit. The operation test mode corresponds to one of a continuous operation or a predetermined time period operation of the intermittent operation circuit. An operation timing generation unit receives the test mode control signal. The operation timing generation unit produces an operation control signal based on the test mode control signal. The operation control signal is outputted to the intermittent operation circuit to operate or wait the intermittent operation circuit. | 04-22-2010 |
20100109764 | CIRCUIT, AN ADJUSTING METHOD, AND USE OF A CONTROL LOOP - A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored. | 05-06-2010 |
20100109765 | REDUCING CURRENT LEAKAGE AND IMPROVING SHELF LIFE TIME OF BATTERY-BASED-DEVICES - An electronic device includes a rechargeable battery, an electrical circuit, a battery safety circuit, and a power down mode circuit. The electrical circuit is configured to generate a power mode control signal. The power down mode circuit receives the power mode control signal. If the power mode control signal has a first value, the power down mode circuit is configured to force a voltage at a first port of the battery safety circuit to a voltage value that is less than an under voltage lock out (UVLO) threshold value of the battery safety circuit to transition the electronic device from a normal operating mode to a low current power down mode. The electronic device may further include a wake up mode circuit. | 05-06-2010 |
20100156522 | Semiconductor integrated circuit device - A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication. | 06-24-2010 |
20100164610 | Multiple circuit blocks with interblock control and power conservation - A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off. | 07-01-2010 |
20100188142 | CIRCUIT FOR AND METHOD OF REDUCING POWER CONSUMPTION IN INPUT PORTS OF AN INTEGRATED CIRCUIT - A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed. | 07-29-2010 |
20100244942 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy. | 09-30-2010 |
20100321102 | Leakage Reduction in Electronic Circuits - In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode. | 12-23-2010 |
20110025409 | Semiconductor integrated circuit device - A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication. | 02-03-2011 |
20110037513 | Controlling Bias Current for an Analog to Digital Converter - A converter includes an analog to digital converter having a bias current input, a control input, and an analog input to provide a digital output as a function of the analog input. A bias module is coupled to the bias current input to provide bias current to the analog to digital converter. A controller is coupled to the bias module and to the control input of the analog to digital converter. The controller controls the analog to digital converter to sample an analog input and controls the bias module to provide an operating bias current during sampling of the analog input and an idle bias current when not sampling the analog input. | 02-17-2011 |
20110063022 | OPTIMIZING POWER CONSUMPTION OF A DIGITAL CIRCUIT - A method is provided for optimizing power consumption of a digital circuit which provides operational functionality based upon operating demands. The digital circuit is subject to a supply voltage level and a clock frequency. The method includes determining an acceptable delay value, from a plurality of predetermined acceptable delay values, for the digital circuit based upon current operating demands and the clock frequency. The supply voltage level and the clock frequency are applied to a delay monitor circuit. The delay experienced by the delay monitoring circuit is measured. The measured delay is compared with the determined acceptable delay value. Based on the outcome of the comparing step, the supply voltage level applied to the digital circuit is selectively adjusted. An arrangement for implementing the method is also provided. | 03-17-2011 |
20110080210 | MICROCOMPUTER - A power consumption of a light-receiving device is reduced while a power consumption of a microcomputer that controls the light-receiving device is reduced as well. The microcomputer is structured to include a drive circuit, a sampling/detection circuit, a timer, a system clock generation circuit, a CPU, a ROM and a RAM. The CPU stops providing the light-receiving device with a power supply by turning off a P channel type MOS transistor with the drive circuit and sets the microcomputer in a standby state for a predetermined period of time. When the microcomputer is released from the standby state, the CPU starts providing the light receiving device with the power supply by turning the P channel type MOS transistor on with the drive circuit. | 04-07-2011 |
20110090002 | HIGH VOLTAGE TOLERANCE OF EXTERNAL PAD CONNECTED MOS IN POWER-OFF MODE - An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads. | 04-21-2011 |
20110090003 | Control Module for Controlling Electro-phoretic Display Integrated Circuit and Method thereof - By classifying an electro-phoretic display integrated circuit (EPD IC) into a digital routine module, a digital non-routine module, and an analog routine module, and by switching off the digital non-routine module and the analog routine module, power consumption of the EPD IC may be effectively reduced, and an available time of an integrated circuit card utilizing the EPD IC may also be lengthened. | 04-21-2011 |
20110121892 | MOTION TRIGGERED MAGNETIC READING AND COMPASS HEADING CALCULATIONS TO REDUCE POWER CONSUMPTION - A method for reducing power consumption of an electronic device is disclosed. In one embodiment, an indication that an electronic device is oriented in a first orientation is received. An indication of rotation of the electronic device around an axis is received. A command is then generated to cause an electronic compass module disposed within the electronic device to transition from an idle operating state to an active operating state and to generate a compass heading. | 05-26-2011 |
20110163801 | Methods and Circuits for Optimizing Performance and Power Consumption in a Design and Circuit Employing Lower Threshold Voltage (LVT) Devices - Methods and circuits for optimizing performance and power consumption in a circuit design and circuit employing one or more lower threshold voltage (Lvt) cells or devices are described. A base supply voltage amplitude is determined for providing operating power for the circuit. The base supply voltage amplitude is a low or lowest voltage level that still satisfies a performance specification for the circuit. Providing a low or lowest base supply voltage level reduces or minimizes the standby (i.e., non-switching) power consumption in the Lvt device(s) since current leakage is reduced as the supply voltage level is reduced. Reducing the supply voltage level used to power the Lvt device(s) also reduces active power consumption for the circuit as well. Thus, total power consumption is optimized or reduced while still receiving the benefit of using Lvt devices to optimize or increase performance of a circuit layout and circuit. | 07-07-2011 |
20110169563 | SYSTEMS AND METHODS FOR MINIMIZING POWER CONSUMPTION - A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system. | 07-14-2011 |
20110193621 | Semiconductor Die with Event Detection in Thick Oxide for Reduced Power Consumption - According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block. | 08-11-2011 |
20110260785 | Low Leakage and Data Retention Circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 10-27-2011 |
20110291748 | POWER CONSUMPTION REDUCTION SYSTEMS AND METHODS - Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly. Histograms of idle period durations can be collected. Adjusting operations can include entering a low power state. | 12-01-2011 |
20120025902 | ELECTRONIC DEVICE WITH POWER SAVING FUNCTION AND OPERATING METHOD THEREOF - In an electronic device with power saving function, when the power saving function of the electronic device is active, the electronic device detects the distance between any object in a proximal area of the electronic device and the electronic device and stores the detected distance as an original distance, and then periodically detects the distance between the object and the electronic device, and stores the detected distance as a current distance. The electronic device is put into power saving mode if an difference between the original distance and the current distance does not fall into the predetermined range. | 02-02-2012 |
20120249228 | POWER-UP SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR APPARATUS - A power-up signal generation circuit of a semiconductor apparatus includes a driver configured to generate a power-up signal in response to a first voltage. The power-up signal generation circuit may also comprise a power control unit configured to provide the first voltage or a second voltage as a power supply voltage to the driver in response to the power-up signal. | 10-04-2012 |
20120293246 | Circuit, An Adjusting Method, and Use of a Control Loop - A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored. | 11-22-2012 |
20120293247 | Semiconductor Integrated Circuit Device - The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode. | 11-22-2012 |
20130009697 | PIPELINE POWER GATING - Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements. | 01-10-2013 |
20130009698 | REDUCING CURRENT LEAKAGE AND IMPROVING SHELF LIFE TIME OF BATTERY-BASED-DEVICES - An electronic device includes a rechargeable battery, an electrical circuit, a battery safety circuit, and a power down mode circuit. The electrical circuit is configured to generate a power mode control signal. The power down mode circuit receives the power mode control signal. If the power mode control signal has a first value, the power down mode circuit is configured to force a voltage at a first port of the battery safety circuit to a voltage value that is less than an under voltage lock out (UVLO) threshold value of the battery safety circuit to transition the electronic device from a normal operating mode to a low current power down mode. The electronic device may further include a wake up mode circuit. | 01-10-2013 |
20130027125 | LOW LEAKAGE AND DATA RETENTION CIRCUITRY - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 01-31-2013 |
20130106502 | METHOD AND SYSTEM FOR WAKING ON INUPUT/OUTPUT INTERRUPTS WHILE POWERED DOWN | 05-02-2013 |
20130200945 | STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN - Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state. | 08-08-2013 |
20130214855 | Integrated Circuit Die Stacks With Rotationally Symmetric VIAS - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die. | 08-22-2013 |
20130222053 | HIGH FREQUENCY SMART BUFFER - Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies. | 08-29-2013 |
20140002181 | LOW-POWER, HIGH-VOLTAGE INTEGRATED CIRCUITS | 01-02-2014 |
20140167840 | Dynamic Clock and Power Gating with Decentralized Wake-Ups - A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state. | 06-19-2014 |
20140247088 | MINIMIZING POWER CONSUMPTION IN ASYNCHRONOUS DATAFLOW ARCHITECTURES - A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein. | 09-04-2014 |
20150109052 | CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS - In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode. | 04-23-2015 |
20160036439 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - According to one embodiment, a semiconductor integrated circuit device includes a first line to which a voltage is applied; a first circuit operating based on a data; a second circuit capable of retaining the data; a third circuit between the first line and the first circuit and capable of shutting off a supply of the voltage to the first circuit; and a fourth circuit including a resistor element, the resistor element connected between the first line and the second circuit. The fourth circuit supplies the voltage to the second circuit via the resistor element in a period in which the third circuit shut off the supply of the voltage to the first circuit. | 02-04-2016 |
20160112045 | CONTROL CHIP AND SYSTEM USING THE SAME FOR POWER SAVING - A control chip for power saving is provided. The control chip is configured to operatively receive a first voltage and a first bias voltage. The control chip includes a microcontroller unit and a low power module. The low power module is coupled to the microcontroller unit. The microcontroller unit receives the first voltage to control the operation of at least one component under an operating mode and to stop receiving the first voltage under a power saving mode. The low power module operatively receives the first bias voltage. When the microcontroller unit switches from the operating mode to the power saving mode, the low power module operatively generates a first control signal to cause the microcontroller unit to stop receiving the first voltage. When the low power module detects a trigger signal, the power module operatively generates a second control signal to cause the microcontroller unit to continue receiving the first voltage. | 04-21-2016 |