Entries |
Document | Title | Date |
20080211571 | Device For Passive Stabilization of Supply Voltages of a Semiconductor Element - In a device for passive stabilization of voltage supplies of a semiconductor element, regions made of a second conductivity type are embedded in a first layer of a first conductivity type within lateral regions, which are used for the wiring of standard cells of components. Barrier layers whose capacitances are used for supporting supply voltages are formed on the boundary surfaces. For this purpose, the regions of the second conductivity type are connected either to first substrate of the same conductivity type or to troughs within standard cells, which have the second conductivity type. | 09-04-2008 |
20080218251 | Plasma television set and power supply circuit - A plasma television set includes a detection disabling circuit including a dividing resistance having one of two ends to which a constant voltage is supplied from an outside of the sustain voltage generation circuit and the other end which is grounded, the dividing resistance having a dividing point, and a diode having an anode connected to the dividing point of the second dividing resistance and a cathode connected to a dividing point of another dividing resistance, and a substitute voltage stop circuit including a resistance to which the predetermined starting voltage is supplied, an electrolytic capacitor having a positive electrode connected to the resistance and a negative electrode grounded, and a transistor having a base connected to the positive electrode of the electrolytic capacitor, an emitter grounded and a collector connected to the dividing point of the second dividing resistance. | 09-11-2008 |
20080238535 | POWER SUPPLY CIRCUIT AND DISPLAY DEVICE THEREWITH - An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents I | 10-02-2008 |
20080238536 | SUPPLY VOLTAGE GENERATING CIRCUIT - A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply. | 10-02-2008 |
20080246536 | Two-phase charge pump circuit without body effect - A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring. | 10-09-2008 |
20080258803 | Semiconductor circuit - A pseudo differential circuit is a circuit system taking the advantages of both a CMOS circuit and a differential circuit. However, when process variability and the like are taken into account, a cross point of positive and negative outputs is not constant, thereby increasing a variation in duty of an output waveform. A semiconductor circuit according to the present invention includes: a first transistor being of a first conductivity type, coupled between a first power supply and an output terminal, and applied with an input signal; a second transistor being of a second conductivity type and coupled between a second power supply and the output terminal; a third transistor being of the second conductivity type and coupled between the first power supply and the output terminal; and a fourth transistor being of the first conductivity type and coupled between the second power supply and the output terminal. | 10-23-2008 |
20080265983 | METHODS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS - A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits. | 10-30-2008 |
20090002061 | BIAS SUPPLY, START-UP CIRCUIT, AND START-UP METHOD FOR BIAS CIRCUIT - A bias supply, a start-up circuit, and a start-up method for a bias circuit are provided. The bias supply includes the bias circuit, an impedance unit, a charge storage unit, and a switch. The impedance unit is coupled between a first voltage and a node. The charge storage unit is coupled between the node and a second voltage. The switch decides whether or not to output a start-up voltage to the bias circuit according to the voltage of the node. In other words, charge/discharge properties of the charge storage unit are utilized for controlling whether the switch outputs a start-up voltage to the bias circuit or not. Therefore, the power consumption of the start-up circuit is decreased. | 01-01-2009 |
20090015319 | VOLTAGE CONTROLLED OSCILLATION CIRCUIT - The present invention provides a voltage controlled oscillator, which includes an amplifier circuit, an amplifier circuit tail current source, a latch circuit, a latch circuit tail current source, a load resistor, and a current modulation circuit. The amplifier circuit is provided with a first node, and an amplifier circuit tail current source having one end coupled to the first node and the other end coupled to the ground voltage (V | 01-15-2009 |
20090033408 | Voltage Pump Circuit with an Oxide Stress Control Mechanism for use in High-Voltage Applications in an Integrated Circuit - A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level. | 02-05-2009 |
20090058509 | Booster Circuit, Semiconductor Device, and Electronic Apparatus - A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current. The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased. | 03-05-2009 |
20090146728 | GENERIC VOLTAGE TOLERANT LOW POWER STARTUP CIRCUIT AND APPLICATIONS THEREOF - Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source. | 06-11-2009 |
20090153233 | BIAS CIRCUIT - A gm compensation current source controls current that runs through a current source transistor, source-grounded transistors that determine a gain so that mutual conductance gm of the source-grounded transistors is compensated and the gain is compensated. A 1/r current source runs current inversely proportional to variation of load resistors of an amplifier so that gate bias points of gate-grounded transistors that are connected to the source-grounded transistors remain constant, and deterioration of linearity at a drain terminal of a gate-grounded transistor is suppressed. | 06-18-2009 |
20090179693 | SEMICONDUCTOR DEVICE - The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation. | 07-16-2009 |
20090184754 | Signal amplifier - A signal amplifier including a transformer with a primary winding and a secondary winding, an oscillator circuit driven by an input signal establishing in the primary winding an oscillating signal amplified by the secondary, and a rectifier circuit responsive to the secondary winding configured to convert the amplified oscillating signal to an amplified version of the input signal. | 07-23-2009 |
20090195300 | Gate controlled atomic switch - The invention relates to a method for producing a switch element. The invention is characterised in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode. | 08-06-2009 |
20090201077 | CLOCKED INVERTER, NAND, NOR AND SHIFT REGISTER - A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series. In the clocked inverter, gates of the third transistor and the fourth transistor are connected to each other, drains of the third transistor and the fourth transistor are each connected to a gate of the first transistor, sources of the first transistor and the fourth transistor are each electrically connected to a first power source, a source of the second transistor is electrically connected to a second power source, and an amplitude of a signal inputted to a source of the third transistor is smaller than a potential difference between the first power source and the second power source. | 08-13-2009 |
20090243707 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND ELECTRONIC APPARATUS - Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor. | 10-01-2009 |
20090261894 | Over-voltage protection circuit and LCD driving circuit using the same - An LCD driving circuit comprising an over-voltage protection circuit includes an input terminal to receive an input voltage, a voltage-dividing circuit, a voltage-stabilizing circuit including a voltage-stabilizing element, a control circuit, a switching element, and an output terminal. The voltage-dividing circuit provides a reference voltage according to the input voltage to the voltage-stabilizing circuit, the voltage-stabilizing circuit determines whether the voltage-stabilizing element conducts according to the reference voltage, and the control circuit controls the switching element to switch on or off according to a working stage of the voltage-stabilizing element to determine whether the output terminal outputs an output voltage. | 10-22-2009 |
20090322414 | INTEGRATION OF SWITCHED CAPACITOR NETWORKS FOR POWER DELIVERY - Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module. | 12-31-2009 |
20100001788 | SYSTEM TO EVALUATE CHARGE PUMP OUTPUTS AND ASSOCIATED METHODS - A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal. | 01-07-2010 |
20100026375 | CIRCUIT TO GENERATE CMOS LEVEL SIGNAL TO TRACK CORE SUPPLY VOLTAGE (VDD) LEVEL - A method, system, and apparatus circuit to generate CMOS level signal to track core supply voltage (VDD) level are disclosed. In one embodiment, a system of an integrated circuit includes an HHV generation circuit located in the integrated circuit to provide an HHV voltage signal to a subsystem circuit of the integrated circuit to replace a core voltage signal used by the subsystem circuit when the core voltage signal is below a specified value, an core voltage source located within the integrated circuit to provide the core voltage signal to the HHV generation circuit, and an external voltage source to provide an external voltage signal of an other entity located outside the integrated circuit to the HHV generation circuit. The system may include a pad driver circuit configured to associate the integrated circuit with the other entity. | 02-04-2010 |
20100026376 | BIAS CIRCUIT FOR A MOS DEVICE - A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations. | 02-04-2010 |
20100033235 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor. | 02-11-2010 |
20100039168 | BIAS NETWORK - A network having a current mirror comprising: a output transistor having a gate electrode for controlling a first current between a first electrode and a second electrode, the first electrode being coupled to a positive reference potential and the second electrode being connected to ground. A second transistor has a gate electrode for controlling a second current between a first electrode and a second electrode of the second transistor. The gate electrodes are connected together to produce the first current and the second current with equal current densities. A first portion of current from a current source is fed to the first electrode of the second transistor and a second portion of current from the current source is fed to a bias voltage producing circuit producing a bias voltage at the gate electrode of the output transistor for tracking variations in the first current passing through the output transistor. | 02-18-2010 |
20100060344 | TRANSITIONING DIGITAL INTEGRATED CIRCUIT FROM STANDBY MODE TO ACTIVE MODE VIA BACKGATE CHARGE TRANSFER - Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode. | 03-11-2010 |
20100066440 | TRANSISTOR WITH A PASSIVE GATE AND METHODS OF FABRICATING THE SAME - Disclosed is a device having a transistor that includes a source, a drain, a channel region extending between the source and the drain, a gate disposed near the channel region, and a conductive member disposed opposite of the channel region from the gate. The conductive member may not overlap the source, the drain, or both the source and the drain. | 03-18-2010 |
20100085112 | Method of Manufacturing a Transistor, and Method of Controlling a Threshold Voltage of the Transistor - A transistor has a gate electrode, a gate insulation layer structure, a channel layer and source/drain layers. The gate insulation layer structure includes a lower gate insulation layer, a control layer for controlling a threshold voltage of the transistor, and an upper gate insulation layer. The channel layer contacts a surface of the gate insulation layer structure and vertically overlaps the gate electrode. The source/drain layers are adjacent to but not contacting the gate electrode. | 04-08-2010 |
20100097128 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit ( | 04-22-2010 |
20100097129 | CMOS Circuit and Semiconductor Device - There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude. | 04-22-2010 |
20100117720 | Integrated Circuit with a Power Transistor Gate Bias Controlled by the Leakage Current - The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.). | 05-13-2010 |
20100127762 | OPEN-DRAIN OUTPUT BUFFER FOR SINGLE-VOLTAGE-SUPPLY CMOS - An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages. By electrical coupling across maximal voltages, the voltage dividers generate reference voltages that induce proper selection of well-bias voltages to the floating wells. | 05-27-2010 |
20100164607 | SEMICONDUCTOR DEVICE THAT CAN ADJUST SUBSTRATE VOLTAGE - To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value. | 07-01-2010 |
20100171546 | Polycrystalline silicon thin film transistors with bridged-grain structures - A low temperature polycrystalline silicon device and techniques to manufacture thereof with excellent performance. Employing doped poly-Si lines which we called a bridged-grain structure (BG), the intrinsic or lightly doped channel is separated into multiple regions. A single gate covering the entire active channel including the doped lines is still used to control the current flow. Using this BG poly-Si as an active layer and making sure the TFT is designed so that the current flows perpendicularly to the parallel lines of grains, grain boundary effects can be reduced. Reliability, uniformity and the electrical performance of the BG poly-Si TFT are significantly improved compared with the conventional low temperature poly-Si TFT. | 07-08-2010 |
20100176874 | VOLTAGE DETECTION CIRCUIT - Provided is a voltage detection circuit having a small circuit scale. A P-type metal oxide semiconductor (PMOS) transistor ( | 07-15-2010 |
20100214011 | BOOSTING CIRCUIT - Provided is a boosting circuit which avoids a malfunction of a peripheral circuit to be connected to the boosting circuit. The boosting circuit includes: a first discharge circuit for discharging a voltage of a first output terminal when a boosting unit stops a boosting operation; and a second discharge circuit for discharging a voltage of a second output terminal. The second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage. | 08-26-2010 |
20100214012 | ELECTRONIC-STRUCTURE MODULATION TRANSISTOR - An electronic structure modulation transistor having two gates separated from a channel by corresponding dielectric layers, wherein the channel is formed of a material having an electronic structure that is modified by an electric field across the channel. | 08-26-2010 |
20100231289 | CMOS BIAS CIRCUIT - A CMOS bias circuit includes a starter circuits and a started circuit part which supplies a current to the outside. The starter circuits has a connection node (first terminal) between it and the started circuit part. The starter circuits includes a first MOS transistor connected at its drain to the first terminal, a first current supply circuit which supplies a starter current to the started circuit via the first MOS transistor, and a circuit which supplies a second current in a direction that interrupts a current flowing through the first MOS transistor to a node between the first MOS transistor and the first current supply circuit in accordance with a potential at the first terminal. The starter circuits has a function of preventing a current flowing between the drain and source of the first MOS transistor in the opposite direction by increasing or decreasing a gate bias of the first MOS transistor in accordance with a value of the second current. | 09-16-2010 |
20100244936 | Semiconductor device having a complementary field effect transistor - A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value. | 09-30-2010 |
20100253419 | SEMICONDUCTOR DEVICE AND SYSTEM - A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased. | 10-07-2010 |
20100283535 | System and Method for a Reference Generator - In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node. | 11-11-2010 |
20100289558 | Booster Circuit, Semiconductor Device, and Electronic Apparatus - A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current. The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased. | 11-18-2010 |
20100289559 | DRAM TUNNELING ACCESS TRANSISTOR - In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the second side of the top of the pillar and serially coupled to the top drain region for the first transistor. A second n+ drain region is doped into the substrate adjacent the pillar. Ultra-thin body layer run along each pillar sidewall between their respective active regions. A gate structure is formed along the pillar sidewalls and over the body layers. The transistors operate by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current. | 11-18-2010 |
20100315155 | HIGH SPEED, LOW POWER CONSUMPTION, ISOLATED ANALOG CMOS UNIT - A semiconductor device including: a low threshold PMOS device formed over an N-type region, the source and drain of the low threshold PMOS formed in P-regions surrounded by N-regions; a low threshold NMOS device formed in a P-type region, the source and drain of the low threshold NMOS formed in N-regions surrounded by P-regions; first and second substrate bias generators, each connected to one of the low threshold devices for generating a substrate bias; a voltage source for generating substrate bias during a standby mode to reduce leakage current; wherein a low voltage threshold is established by the source and drain regions of the low threshold devices and their respective surrounding regions of opposite polarity. | 12-16-2010 |
20100321100 | NEGATIVE ANALOG SWITCH DESIGN - A transmission gate includes first and second MOS transistors of opposite conductivity type coupled in parallel with each other. Each transistor includes a body connection that is separately biased by corresponding first and second biasing circuits. The first biasing circuit generates a first bias voltage having a voltage level that is generated as a function of the signal at the first node and a first (for example, positive) reference voltage. The second biasing circuit generates a second bias voltage having a voltage level that is generated as a function of the signal at the first node and a second (for examples ground) reference voltage. | 12-23-2010 |
20110012672 | BODY-BIAS VOLTAGE CONTROLLER AND METHOD OF CONTROLLING BODY-BIAS VOLTAGE - A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal. | 01-20-2011 |
20110018619 | INTEGRATED NEGATIVE VOLTAGE GENERATOR - A negative voltage generator with AC coupled control signals is described. In an exemplary design, the generator includes four switches (which may be implemented with MOS transistors) and a capacitor. A first switch is coupled between a positive input voltage and a first end of the capacitor. A second switch is coupled between the first end of the capacitor and circuit ground. A third switch is coupled between a second end of the capacitor and circuit ground. A fourth switch is coupled between the second end of the capacitor and a negative output voltage. The first and second switches are controlled by first and second control signals, respectively. The third and fourth switches are controlled by first and second AC coupled control signals, respectively. The first and second AC coupled control signals may be generated by AC coupling the first and second control signals, respectively, and applying appropriate biasing. | 01-27-2011 |
20110018620 | Semiconductor Integrated Circuit Having Normal Mode And Self-Refresh Mode - An SDRAM includes a DC-DC converter IC for generating a first internal power supply voltage from external power supply voltage, a regulator IC for generating a second internal power supply voltage lower than the first internal power supply voltage, from external power supply voltage, and a switching portion for supplying the first internal power supply voltage to an internal circuit in a normal operation mode and supplying the second internal power supply voltage to the internal circuit in a self-refresh mode. The switching unit allows the DC-DC converter IC and the regulator IC to operate simultaneously only for a prescribed overlapped period, at a time of operation mode switching. The DC-DC converter IC temporarily increases the first internal power supply voltage within the operating voltage range of the internal circuit in the overlapped period. | 01-27-2011 |
20110050329 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a cascode circuit having a transistor, a detector circuit and a bias generator circuit. A bias is applied to a substrate of the transistor. The detector circuit generates a signal related to a threshold voltage of the transistor. The bias generator circuit generates the bias based on the signal generated by the detector circuit. | 03-03-2011 |
20110063019 | DUAL DIELECTRIC TRI-GATE FIELD EFFECT TRANSISTOR - A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt | 03-17-2011 |
20110089998 | Logic circuits, inverter devices and methods of operating the same - An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor. | 04-21-2011 |
20110115553 | SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE - SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection. | 05-19-2011 |
20110133822 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures. | 06-09-2011 |
20110133823 | Booster Circuit, Semiconductor Device, and Electronic Apparatus - A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current. The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased. | 06-09-2011 |
20110163797 | POWER SWITCH WITH REVERSE CURRENT BLOCKING CAPABILITY - A switching circuit controls the flow of current between its input and output in accordance with the state of a control signal applied to the circuit. When the control signal is in a first state and the voltage applied to the input is higher than the voltage at the output, the circuit provides a low resistance path between its input and output terminals thereby enabling current to flow from the input to the output. When the control signal is in the first state and the voltage at the output is higher than the voltage at the input, the circuit inhibits current flow from the output to the input. When the control signal is in a second state, the circuit is turned off thus inhibiting current flow between the input and the output. | 07-07-2011 |
20110169559 | CHARGE PUMP CIRCUIT WITH IMPROVED RELIABILITY - A charge pump circuit, including a charging capacitor, a pumping capacitor, a switch, two voltage-limiting devices, and two path-control devices, generates an output voltage by amplifying an input voltage. The charging capacitor is charged by the input voltage and discharged according to the voltage level of a node. The pumping capacitor can provide the output voltage by storing the charges transmitted from the charging capacitor. The switch controls the signal transmission path between the node and a ground terminal according to a clock signal. The first path-control device controls the signal transmission path between the input signal and the charging capacitor. The second path-control device controls the signal transmission path between the charging capacitor and the pumping capacitor. | 07-14-2011 |
20110169560 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND ELECTRONIC APPARATUS - Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor. | 07-14-2011 |
20110175674 | METHOD OF DRIVING TRANSISTOR AND DEVICE INCLUDING TRANSISTOR DRIVEN BY THE METHOD - Disclosed is a method of driving a transistor including a semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, and a second conductive layer such that the semiconductor layer is disposed between the first and second insulating layers, one surface of the first insulating layer opposite the other surface in contact with the semiconductor layer is in contact with the first conductive layer, one surface of the second insulating layer opposite the other surface in contact with the semiconductor layer is in contact with the second conductive layer. The method includes applying a voltage VBG that satisfies the relation of VBG≦VON | 07-21-2011 |
20110215860 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells. | 09-08-2011 |
20110215861 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a photodiode, a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor have a function of retaining a charge accumulated in a gate of the first transistor. In a period during which the second transistor and the third transistor are off, a voltage level of a voltage applied to a gate of the second transistor is set to be lower than a voltage level of a source of the second transistor and a voltage level of a drain of the second transistor, and a voltage level of a voltage applied to a gate of the third transistor is set to be lower than a voltage level of a source of the third transistor and a voltage level of a drain of the third transistor. | 09-08-2011 |
20110221515 | BODY BIAS COORDINATOR, METHOD OF COORDINATING A BODY BIAS AND SUB-CIRCUIT POWER SUPPLY EMPLOYING THE SAME - A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. | 09-15-2011 |
20110234306 | BOOSTER CIRCUIT - In a booster, a first transistor of a second conduction-type is formed on a first conduction-type substrate and connected to between a voltage-source and an output so that the first transistor functions as a diode. A first capacitor is connected to a first node of the first transistor on a voltage-source side, and transmits a first clock to the first node. A second transistor of the first conduction-type is connected to a second node of the first transistor on an output side to receive the first clock. A second capacitor is connected to the second node and transmits a second clock having an opposite phase of the first clock to the second node. The first transistor transfers the first node's voltage stepped up by the first clock to the second node. The second transistor transfers the second node's voltage stepped up by the second clock to an output side. | 09-29-2011 |
20110260780 | HIGH POWER FET SWITCH - Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage. | 10-27-2011 |
20110260781 | INTEGRATED CIRCUIT DEVICE - The interposer is disposed on an upper surface of the stacked structure formed by stacking a plurality of a DRAM chip and a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished in comparison to a voltage boost circuit using a charge pump connected in parallel with a plurality of a capacitance. | 10-27-2011 |
20110304386 | CONSTANT-VOLTAGE CIRCUIT - A constant-voltage circuit includes: first and second field-effect transistors; a first node connected to the drains of the first and second field-effect transistors; a second node connected to the gates of the first and second field-effect transistors; a bipolar transistor whose collector is connected to the second node; a resistor connected to the source of the second field-effect transistor and the collector of the bipolar transistor; and a bias circuit that is connected to the source of the second field-effect transistor and supplies a bias voltage to the base of the bipolar transistor, wherein a power supply is connected to the first node and a constant voltage is outputted from the source of the first field-effect transistor. | 12-15-2011 |
20110316619 | POWER SUPPLY VOLTAGE MONITOR CIRCUIT - According to one embodiment, a power supply voltage monitor circuit includes a constant voltage circuit, a level shift circuit, a clamping circuit, a first differential circuit, and a second differential circuit. The first differential circuit include a differential unit receiving a constant current supplied from a current source and outputting an output voltage in accordance with a potential difference between a first input voltage obtained by subjecting the second constant voltage to resistive division and a second input voltage obtained by subjecting the power supply voltage to resistive division, and an output unit outputting a rectangular signal in accordance with the output voltage of the differential unit. The second differential circuit turns off the current source of the differential unit depending on a potential difference between the first constant voltage and the first input voltage to thereby control the output operation of the output unit, in a case where the clamping circuit does not fix the first constant voltage. On the other hand, The second differential circuit turns on the current source of the differential unit depending on a potential difference between the clamping voltage and the first input voltage. | 12-29-2011 |
20120013394 | SOURCE FOLLOWER CIRCUIT OR BOOTSTRAP CIRCUIT, DRIVER CIRCUIT COMPRISING SUCH CIRCUIT, AND DISPLAY DEVICE COMPRISING SUCH DRIVER CIRCUIT - In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized. | 01-19-2012 |
20120025899 | TUNABLE TRANSCONDUCTANCE-CAPACITANCE FILTER WITH COEFFICIENTS INDEPENDENT OF VARIATIONS IN PROCESS CORNER, TEMPERATURE, AND INPUT SUPPLY VOLTAGE - A transconductance-capacitance (G | 02-02-2012 |
20120032732 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions. | 02-09-2012 |
20120032733 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SUPPLY VOLTAGE SUPERVISOR - A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor. The Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased. | 02-09-2012 |
20120038414 | METHOD FOR OPERATING SEMICONDUCTOR DEVICE - A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage. | 02-16-2012 |
20120056665 | INPUT/OUTPUT CIRCUIT WITH HIGH VOLTAGE TOLERANCE AND ASSOCIATED APPARATUS - An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias voltage higher than an internal operating voltage of the charge pump itself, and a switch between an external circuit and an internal circuit of the integrated circuit. When the switch conducts between the external circuit and the internal circuit, the switch provides a clamping voltage according to the bias voltage and a cross voltage of the switch, so that a voltage of the internal circuit is bounded by the clamping voltage to prevent the internal circuit from over-voltage. | 03-08-2012 |
20120075010 | DISCHARGE CIRCUIT FOR VOLTAGE MULTIPLIERS - An embodiment of a discharge circuit for evacuating electric charge accumulated in circuit nodes of a charge pump during a discharge phase consequent to a shutdown of the charge pump is proposed. The charge pump is configured to bias each circuit node with a corresponding pump voltage during an operational phase of the charge pump. The discharge circuit includes a generator circuit configured to generate a discharge current during the discharge phase. The discharge circuit further includes means for evacuating the electric charge stored in each circuit node of the charge pump during a corresponding portion of the discharge phase; such means for evacuating include a respective discharge stage for each circuit node of the charge pump. Each discharge stage includes a first discharge circuit branch and a second discharge circuit branch coupled to the corresponding circuit node. The discharge stage is configured to cause the discharge current flowing through the first discharge circuit branch—during the portion of the discharge phase of the corresponding circuit node—when the pump voltage of the corresponding circuit node is higher than a respective threshold, and through the second discharge circuit branch when the pump voltage of the corresponding circuit node is lower than said respective threshold. | 03-29-2012 |
20120098590 | QUANTUM ELECTRO-OPTICAL DEVICE USING CMOS TRANSISTOR WITH REVERSE POLARITY DRAIN IMPLANT - A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode. | 04-26-2012 |
20120112819 | ELECTROMIGRATION-COMPLAINT HIGH PERFORMANCE FET LAYOUT - An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor. | 05-10-2012 |
20120119823 | Bias Circuit with High Enablement Speed and Low Leakage Current - A circuit includes a first and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground. | 05-17-2012 |
20120119824 | BIAS VOLTAGE SOURCE - An integrated circuit that includes a data storage cell. The data storage cell has a PMOS transistor in an n-well. In addition, the data storage cell has a PMOS diode connecting a voltage source to a bias node of the n-well. Alternatively, an integrated circuit that includes a data storage cell. The alternative data storage cell has an NMOS transistor in an isolated p-well. In addition, the alternative data storage cell has an NMOS diode connecting a voltage source to a bias node of the isolated p-well. | 05-17-2012 |
20120126880 | IGBT DEVICE WITH BURIED EMITTER REGIONS - An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element. | 05-24-2012 |
20120139623 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND ELECTRIC POWER CONVERTER - A semiconductor element | 06-07-2012 |
20120169410 | TECHNIQUE TO MINIMIZE VDS MISMATCH DRIVEN VOLTAGE SWING VARIATION IN OPEN DRAIN TRANSMITTER - A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage. | 07-05-2012 |
20120200342 | GATE CONTROLLED PN FIELD-EFFECT TRANSISTOR AND THE CONTROL METHOD THEREOF - The present invention belongs to the technical field of semiconductor devices, and more specifically, relates to a gate-controlled PN field-effect transistor and the control method thereof The gate-controlled PN field-effect transistor disclosed by the present invention comprises a semiconductor substrate region, a drain region and a source region on the left and right sides of the substrate region, and gate regions on the upper and lower sides of the substrate region. The gate-controlled PN field-effect transistor works in the positive bias state of the source-drain PN junction and is conducted from the middle of the substrate region. The gate-controlled PN field-effect transistor provided by the present invention decreases the leakage current and increases the drive current at the same time, namely decreases the chip power consumption and improves the chip performances at the same time. The present invention further discloses a method for controlling the gate-controlled PN field-effect transistor, including cut-off and conduction operation. | 08-09-2012 |
20120212286 | SEMICONDUCTOR DEVICE THAT CAN CANCEL NOISE IN BIAS LINE TO WHICH BIAS CURRENT FLOWS - Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line. | 08-23-2012 |
20120229198 | POWER SUPPLY REGULATOR - Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply. | 09-13-2012 |
20120235731 | CONTINUOUS TUNABLE LC RESONATOR USING A FET AS A VARACTOR - A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET. | 09-20-2012 |
20120319763 | BANDGAP CIRCUIT AND START CIRCUIT THEREOF - A start circuit including a load unit, a first switch, a second switch and a reset control circuit is provided. The load unit receives a power voltage. The first switch is electrically connected between the load unit and a ground, and receives a node voltage from the reference circuit. The second switch has a first end electrically connected to the reference circuit, a second end electrically connected to the ground, and a control end electrically connected to the second end of the load unit. The second switch determines whether to provide a start voltage to a reference circuit according to a conducting state thereof. The reset control circuit provides a discharge path between the control end of the first switch and the ground, and conducts the discharge path according to the power voltage during a period when the power voltage is smaller than a threshold voltage. | 12-20-2012 |
20130015912 | SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE - SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection. | 01-17-2013 |
20130038382 | ADJUSTABLE BODY BIAS CIRCUIT - Body biasing circuit and methods are implemented in a variety of different instances. One such instance involves placing, a first well of a first body bias island and a second well of a second body bias island in a first bias mode by controlling switches of a body bias switch circuit. The biasing is one of a reverse body bias, a nominal body bias and a forward body bias. The second well is also biased according to one of a reverse body bias, a nominal body bias and a forward body bias. In response to the bias-mode input, the first well of the first body bias island and the second well of the second body bias island are each placed in a second bias mode by controlling switches of the body bias switch circuit. The bias of the first well and second well can be changed. | 02-14-2013 |
20130038383 | PIEZOELECTRIC ELECTROMECHANICAL DEVICES - An piezoelectric electromechanical transistor has first and second terminals formed in a semiconductor region, a gate and a piezoelectric region between the gate and the semiconductor region. The piezoelectric region may be configured to drive the semiconductor region to vibrate in response to a signal applied to the gate. The transistor may be configured to produce a signal at the first terminal at least partially based on vibration of the semiconductor region. | 02-14-2013 |
20130038384 | CANCELING THIRD ORDER NON-LINEARITY IN CURRENT MIRROR-BASED CIRCUITS - A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current. | 02-14-2013 |
20130043934 | Analog floating gate charge loss compensation circuitry and method - An analog floating gate circuit ( | 02-21-2013 |
20130057335 | POWER SUPPLY STABILIZING CIRCUIT OF SOLID-STATE IMAGING DEVICE - According to one embodiment, a power supply stabilizing circuit includes at least one bias voltage generation circuit and at least one voltage supply circuit. The at least one bias voltage generation circuit is configured to compare a reference voltage and a signal corresponding to a bias voltage which is generated from an unstable voltage, thereby generating the bias voltage. The at least one voltage supply circuit is disposed near a functional circuit, is connected to the functional circuit by a wiring line, and is configured to stabilize the unstable voltage, based on the bias voltage which is supplied from the at least one bias voltage generation circuit, and to supply a stabilized voltage to the functional circuit. | 03-07-2013 |
20130063204 | Output Signal Circuit For Use In A Receiver - According to one embodiment, an output signal circuit for use in a receiver is provided. The output signal circuit is provided with first and second transistors of an insulated gate field effect type, and a backgate bias generator. A source of the first transistor is capable of receiving an input signal. A source of the second transistor is capable of generating an output signal. A backgate bias generator produces a backgate bias voltage which is applied to backgate of the first and second transistors commonly. | 03-14-2013 |
20130069712 | POWER SEMICONDUCTOR DEVICES AND FABRICATION METHODS - We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer. | 03-21-2013 |
20130088284 | SEMICONDUCTOR DEVICE - A semiconductor device includes a precharge circuit configured to precharge a voltage output node, a boosting circuit configured to boost a voltage at the voltage output node by a predetermined level after the voltage output node is precharged, and a voltage supply circuit configured to supply a pumping voltage to increase the voltage at the voltage output node to a target level. | 04-11-2013 |
20130099853 | METHODOLOGY AND APPARATUS FOR TUNING DRIVING CURRENT OF SEMICONDUCTOR TRANSISTORS - A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics. | 04-25-2013 |
20130106499 | SEMICONDUCTOR DEVICE WITH POWER ELEMENT AND CIRCUIT ELEMENT FORMED WITHIN THE SAME SEMICONDUCTOR SUBSTRATE | 05-02-2013 |
20130113547 | Method and apparatus for floating or applying voltage to a well of an integrated circuit - In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well. | 05-09-2013 |
20130127524 | HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE - A high-voltage integrated circuit device can include, in a surface layer of a p semiconductor substrate, an n region which is a high-side floating-potential region, an n | 05-23-2013 |
20130162338 | TUNABLE TRANSCONDUCTANCE-CAPACITANCE FILTER WITH COEFFICIENTS INDEPENDENT OF VARIATIONS IN PROCESS CORNER, TEMPERATURE, AND INPUT SUPPLY VOLTAGE - A transconductance-capacitance (G | 06-27-2013 |
20130181768 | 3X INPUT VOLTAGE TOLERANT DEVICE AND CIRCUIT - A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages. | 07-18-2013 |
20130241631 | OUTPUT STAGE CIRCUIT - An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current. | 09-19-2013 |
20130241632 | BIAS VOLTAGE GENERATION CIRCUIT AND DIFFERENTIAL CIRCUIT - A bias voltage generation circuit includes a first current source connected to a first power source; a first transistor which is diode connected and is connected to the first current source; a second transistor connected between the first transistor and a second power source; a second current source connected to the first power source; a third transistor connected to the second current source; a fourth transistor connected between the third transistor and the second power source; a first output point connected to the first transistor and the third transistor and outputs a first bias voltage; a second output point connected to the fourth transistor and the second current source and outputs a second bias voltage; and a bias voltage adjusting circuit which adjusts the first bias voltage in accordance with a control input. | 09-19-2013 |
20130293285 | Booster Circuit, Semiconductor Device and Electronic Apparatus - A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current. The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased. | 11-07-2013 |
20130328619 | INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE - An integrated circuit in which a voltage divider circuit is integrated comprises a first resistor, second resistor, control portion, switch, and switching portion. The first resistor and second resistor form a resistive voltage divider element for dividing a voltage obtained by rectifying an alternating-current voltage, or a direct-current voltage, supplied to a control portion. The switch is provided in series with the resistive voltage divider element, and passes or cuts off current passing through the resistive voltage divider element. The switching portion switches the switch so as to pass current during driving of the control portion, and cut off current during standby of the control portion. | 12-12-2013 |
20140015599 | SUBSTRATE BIAS CONTROL CIRCUIT - An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value. | 01-16-2014 |
20140091858 | LOCAL VOLTAGE CONTROL FOR ISOLATED TRANSISTOR ARRAYS - Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor. | 04-03-2014 |
20140097888 | MULTI-VOLTAGE SUPPLIED INPUT BUFFER - An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage. The input buffer further includes a bias circuit configured to generate the variable voltage responsive to a state of the input signal. | 04-10-2014 |
20140103991 | BOUNDED BIAS CIRCUIT WITH EFFICIENT VT-TRACKING FOR HIGH VOLTAGE SUPPLY/LOW VOLTAGE DEVICE - Disclosed is a device and method for providing a bounded bias voltage with improved Process Voltage Temperature (PVT) adjustment. An embodiment may include a bias_n generation circuit that adjusts a bias_n voltage for PVT as a function of two bias_n NMOS transistors/diodes and a bias_p generation circuit that adjusts a bias_p voltage for PVT as a function of two bias_p PMOS transistors/diodes. An embodiment may further include a PVT adjusted bounded bias voltage circuit comprised of a NMOS transistor with the bias_n voltage at the gate and a PMOS transistor with the bias_p voltage at the gate such that a common connection between the NMOS and PMOS transistors generates a bounded bias voltage adjusted for PVT as a function of two body biased voltages (bias_n/bias_p). The bounded bias voltage may be used to provide a low supply voltage to a low voltage device using an available high voltage supply. | 04-17-2014 |
20140103992 | BIASING IN CMOS INVERTER - Biasing circuit for providing a supply voltage (Vdd) for an inverter based circuit. The biasing circuit is provided on a same die as the inverter based circuit, and includes a first shorted inverter circuit (T | 04-17-2014 |
20140125404 | HIGH-VOLTAGE TOLERANT BIASING ARRANGEMENT USING LOW-VOLTAGE DEVICES - A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly. | 05-08-2014 |
20140152380 | SEMICONDUCTOR DEVICE THAT CAN CANCEL NOISE IN BIAS LINE TO WHICH BIAS CURRENT FLOWS - Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line. | 06-05-2014 |
20140159806 | SEMICONDUCTOR DEVICE AND BODY BIAS METHOD THEREOF - Exemplary embodiments disclose a semiconductor device which includes a function block including a plurality of transistors; a temperature detector configured to detect a driving temperature of the function block in real time; and an adaptive body bias generator configured to provide a body bias voltage to adaptively adjust leakage currents of the transistors according to the detected driving temperature, wherein the adaptive body bias generator is further configured to generate a body bias voltage corresponding to a predetermined minimum leakage current according to the driving temperature. | 06-12-2014 |
20140167838 | POWER SEMICONDUCTOR DEVICE - According to one or more embodiments of the present invention, a method for driving a power semiconductor device that has a source electrode, a drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, a plurality of gate electrodes formed within the semiconductor layer, and a plurality of conductive layers that are formed between the gate electrodes and the drain electrode and in electrical communication with the gate electrodes. The method comprises providing a first electric potential to the source electrode, providing a second electric potential to the drain electrode, providing a third electric potential to the gate electrodes, providing a first electric potential to at least one of the conductive layers, and providing a third electric potential to at least another one of the conductive layers. | 06-19-2014 |
20140176230 | High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices - A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly. | 06-26-2014 |
20140197882 | SWITCHING DEVICE WITH RESISTIVE DIVIDER - Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the FET at a position electrically between a gate terminal of the FET and a body terminal of the FET. | 07-17-2014 |
20140197883 | WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT - A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively. | 07-17-2014 |
20140203865 | OUTPUT BUFFERS - An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage. | 07-24-2014 |
20140240036 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage. | 08-28-2014 |
20140266411 | SWITCHING DEVICE - The present invention provides a switching device capable of further minimizing the ON resistance of a switching element. Switching element has hole injecting unit that includes injecting electrode which is directly connected to semiconductor substrate. Injection driving unit of driving unit is connected to injecting electrode and source electrode of switching element, and applies an injection voltage Vin between injecting electrode and source electrode. Injection driving unit injects holes from hole injecting unit to a hetero-junction interface of semiconductor substrate, by applying the injection voltage Vin exceeding a threshold value to switching element.
| 09-18-2014 |
20140285255 | INTEGRATED CIRCUITS HAVING CASCODE TRANSISTOR - An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor. | 09-25-2014 |
20140300410 | CASCODED SEMICONDUCTOR DEVICES - The invention provides a cascode transistor circuit with a depletion mode transistor and a switching device. A gate bias circuit is connected between the gate of the depletion mode transistor and the low power line. The gate bias circuit is adapted to compensate the forward voltage of a diode function of the switching device. The depletion mode transistor and the gate bias circuit are formed as part of an integrated circuit. | 10-09-2014 |
20140347121 | LOCAL VOLTAGE CONTROL FOR ISOLATED TRANSISTOR ARRAYS - Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor. | 11-27-2014 |
20140375379 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined. | 12-25-2014 |
20150015326 | BULK-MODULATED CURRENT SOURCE - A bulk-modulated current source includes: an output terminal configured to supply an output current; a first transistor comprising: a first electrode coupled to the output terminal, a second electrode, a bulk electrode, and a gate electrode configured to receive a bias voltage; and an amplifier comprising: an input terminal electrically coupled to the first electrode of the first transistor, and an output terminal electrically coupled to the bulk electrode of the first transistor. | 01-15-2015 |
20150028939 | Circuit for Clamping Current in a Charge Pump - A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump. | 01-29-2015 |
20150042399 | ANALOG SWITCH FOR RF FRONT END - Techniques for improving the linearity of radio-frequency (RF) front-end switches. In an aspect, open-loop techniques are disclosed for superimposing the output voltage of one or more negative rectifiers on a negative substrate bias voltage to reduce the non-linearities associated with voltage-dependent substrate leakage current. In another aspect, closed-loop techniques are further disclosed for maintaining the substrate bias voltage close to a reference voltage. Exemplary embodiments of the circuit blocks are further described. | 02-12-2015 |
20150070084 | SEMICONDUCTOR DEVICE - A semiconductor device includes an input-part receiving a first voltage and an output-part outputing a second voltage. A current mirror part receives the first voltage. A reference voltage is supplied to a gate of a reference transistor. The reference transistor is electrically connected between the current-mirror part and a ground voltage. A monitor transistor includes a gate electrically connected to the second power-supply voltage, and is electrically connected between the current-mirror part and the ground voltage. A voltage-generation transistor includes a gate electrically connected to both the current-mirror part and the reference transistor. The voltage-generation transistor is electrically connected between the input-part and the output-part. A first capacitor including one end electrically connected to the output-part, and the other end electrically connected to both the current-mirror part and the reference transistor. | 03-12-2015 |
20150137877 | BIAS CIRCUIT USING NEGATIVE VOLTAGE - Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node. | 05-21-2015 |
20150145592 | DUAL MODE TRANSISTOR - A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology. | 05-28-2015 |
20150301539 | BAND-GAP CURRENT REPEATER - A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier. | 10-22-2015 |
20150355664 | DIFFERENTIAL OUTPUT CIRCUIT AND SEMICONDUCTOR DEVICE - A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor. | 12-10-2015 |
20150358019 | GATE POTENTIAL CONTROL CIRCUIT - A gate potential control circuit includes a driving switching element, a first gate potential supply part, a first switching element, a first resistor, and a first operational amplifier. The first operational amplifier includes an output portion connected to a gate of the first switching element, an inverting input into which a first reference potential is input, and a non-inverting input into which a closer one of a first value and a second value to a potential of the first gate potential supply part is input. The first value is based on a potential difference obtained by subtracting a potential of a terminal of the first resistor on a driving switching element side from a potential of a terminal of the first resistor on a first gate potential supply part side. The second value is based on a potential of a terminal of the first switching element. | 12-10-2015 |
20150365089 | SEMICONDUCTOR DEVICE AND DESIGNING METHOD OF SEMICONDUCTOR DEVICE - Out of a plurality of transistors, in a power switch which controls, for each logic block, a supply and an interruption of power with respect to the each logic block, each having a gate electrode connected to a well via a contact electrode, and a body region connected to a connection portion of the well with the contact electrode via a well resistor under an element isolation insulating film, and controlling a threshold voltage by changing an electric potential applied to the body region in accordance with a signal of the gate electrode, a plurality of first transistors and a plurality of second transistors which are different from the plurality of first transistors are made to have different delay characteristics from each other between the respective connection portions of the well with the contact electrodes and the respective body regions. | 12-17-2015 |
20160026207 | POWER UP BODY BIAS CIRCUITS AND METHODS - An integrated circuit device can include at least a first body bias circuit configured to generate a first body bias voltage different from power supply voltages of the IC device; at least a first bias control circuit configured to set a first body bias node to a first power supply voltage, and subsequently enabling the first body bias node to be set to the first body bias voltage; and a plurality of first transistors having bodies connected to the first body bias node. | 01-28-2016 |
20160028376 | INTEGRATED CIRCUIT DEVICE AND REPAIR METHOD THEREOF - The present disclosure provides integrated circuit (IC) devices and repair methods of the IC devices. An IC device includes a PMOS transistor including a substrate, a gate dielectric layer on the substrate, and a gate on the gate dielectric layer. The IC device also includes a repair circuit configured to apply a negative bias voltage to the substrate of the PMOS transistor, when the PMOS transistor is in an OFF state, to cause injections of electrons in the substrate into the gate dielectric layer to neutralize holes caused by negative bias temperature instability (NBTI) effect. The repair circuit is further configured to stop applying the negative bias voltage to the substrate of the PMOS transistor when the PMOS transistor is in an ON state. As such, the disclosed IC device repairs defect caused by NBTI effect in the PMOS transistor and prolongs the lifespan of the PMOS transistor. | 01-28-2016 |
20160043234 | SEMICONDUCTOR TUNNELING DEVICE - The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure. | 02-11-2016 |
20160043717 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined. | 02-11-2016 |
20160049928 | SYSTEM-ON-CHIP INCLUDING BODY BIAS VOLTAGE GENERATOR - A system-on-chip includes a body bias voltage generator having a voltage divider and a filter. The voltage divider includes a switched capacitor circuit and a resistor circuit. The switched capacitor circuit operates based on a first clock signal and a second clock signal. The resistor circuit outputs a first voltage through a first node, which is coupled to the switched capacitor circuit and the resistor circuit. The first and second clock signals have a same frequency. The filter performs a filtering operation on the first voltage to generate a body bias voltage. | 02-18-2016 |
20160071849 | Mode-Variant Adaptive Body Bias Scheme For Low-Power Semiconductors - A complementary metal oxide semiconductor (CMOS) device having an active mode and a standby mode. The CMOS device includes a first transistor having a first body, a second transistor having a second body, a first forward body bias voltage source, and a second forward body bias voltage source. The first forward body bias voltage source is coupled to the first body when the CMOS device is in the active mode, and is disconnected from the first body when the CMOS device is in the standby mode. The second forward body bias voltage source is coupled to the second body when the CMOS device is in the active mode, and is disconnected from the second body when the CMOS device is in the standby mode. | 03-10-2016 |
20160093750 | VARACTOR DEVICE WITH BACKSIDE CONTACT - An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact. | 03-31-2016 |
20160156350 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE | 06-02-2016 |