Class / Patent application number | Description | Number of patent applications / Date published |
327292000 | Clock fault compensation or redundant clocks | 20 |
20080211562 | METHOD AND DEVICE FOR GENERATING A CLOCK SIGNAL - A method and device for generating a clock signal, the method including measuring, using a first clock signal, a characteristic of a reference event in a received signal, determining, using the first clock signal, a variation of a characteristic of a second event in a received signal, correcting the measurement according to the variation of the characteristic of the second event, and generating a second clock signal using the first clock signal according to the corrected measurement. | 09-04-2008 |
20080224752 | INTERNAL CLOCK GENERATOR, SYSTEM AND METHOD - An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection. | 09-18-2008 |
20080224753 | Clock generator circuit, clock selector circuit, and semiconductor integrated circuit - A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector. | 09-18-2008 |
20080231338 | Converter systems having reduced-jitter, selectively-skewed interleaved clocks - Converter systems are disclosed that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process. | 09-25-2008 |
20080238518 | PROCESS, VOLTAGE, AND TEMPERATURE COMPENSATED CLOCK GENERATOR - According to some embodiments, a process, voltage, and temperature compensated clock generator is disclosed. The clock generator may be a charge-charge clock generator including a first load capacitive element and a second load capacitive element. A process, voltage, and temperature compensated current source is coupled to the charge-charge clock generator, and is used to charge the first load capacitive element and the second load capacitive element. | 10-02-2008 |
20080258793 | Clock generating circuit and semiconductor device provided with clock generating circuit - An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively utilize the remaining power of the battery. A structure includes an output voltage detecting circuit for detecting an output voltage from a battery; a frequency-division number determining circuit for determining the number of frequency-division by a value of the output voltage detected by the output voltage detecting circuit; an oscillation circuit for outputting a reference clock signal depending on the output voltage; a counter circuit for counting a number of waves of the reference clock signal that depends on the number of frequency-division; and a frequency-dividing circuit that frequency-divides the reference clock signal depending on the number of waves counted by the counter circuit. | 10-23-2008 |
20090102534 | Decentralised fault-tolerant clock pulse generation in vlsi chips - The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu | 04-23-2009 |
20090322398 | Dual-path clocking architecture - A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal. | 12-31-2009 |
20100039157 | CLOCK ADJUSTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output. | 02-18-2010 |
20110215854 | Clock Distribution Network Architecture with Clock Skew Management - Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal. | 09-08-2011 |
20110234285 | SWITCHING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME - A switching device includes a first switch disposed between a power source voltage and an intermediate node, the first switch forming a current path on the basis of an input signal, a second switch disposed between the intermediate node and a ground, the second switch forming a current path on the basis of a voltage of the intermediate node, and a transmission gate receiving the input signal, the transmission gate outputting the input signal on the basis of the voltage of the intermediate node. | 09-29-2011 |
20130088275 | DYNAMIC VOLTAGE DROP AWARE CLOCK INSERTION TOOL - A clock tree power decoupling system includes a pre-decoupling processor that provides a clock tree that supports a critical timing path condition. The clock tree power decoupling system also includes a clock tree power decoupler having a clock tree module that identifies clock buffers in the clock tree corresponding to synchronous start and end points of the critical timing path condition, and a power decoupling module that inserts a decoupling capacitance proximate the clock buffers in the clock tree, wherein the decoupling capacitance is sized to rectify the critical timing path condition. The clock tree power decoupling system additionally includes a post-decoupling processor that provides a power-decoupled clock-inserted database employing the decoupling capacitance. A method of clock tree power decoupling is also provided. | 04-11-2013 |
20140021997 | Method and Apparatus for Calibrating Low Frequency Clock - A method and an apparatus for calibrating a low frequency clock are disclosed. The method includes: calculating a frequency of a low frequency clock in a current low frequency clock calibration; and calculating an average value of low frequency clock frequencies in n clock calibrations before the current calibration, where n is greater than 1 and is an integer; judging whether a difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than a preset threshold for the difference; and if the difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than the preset threshold for the difference, calculating the number of sleep cycles according to the calculated and obtained frequency of the low frequency clock in the current low frequency clock calibration. | 01-23-2014 |
20140035647 | APPARATUS AND METHOD FOR ENHANCING STABILITY OF ELECTRONIC DEVICE HAVING A HIGH-ACCURACY CLOCK - An embodiment relates to an apparatus and method for enhancing stability of electronic device having a high-accuracy clock. Specifically, there is disclosed a controller for an electronic device, including a control core configured to generate a signal for controlling operation of the electronic device, an internal clock source coupled to the control core and configured to provide a high-speed internal (HSI) clock signal to the control core to act as a drive signal, and at least one timing-sensitive component coupled to an external clock source of the controller and configured to receive a high-speed external (HSE) clock signal generated by an external clock source to act as a drive signal. There is further disclosed a method for driving such kind of controller. According to an embodiment, the high-clock-accuracy requirement and the stability and robustness requirement can be satisfied simultaneously. | 02-06-2014 |
20140159791 | ADAPTIVE CLOCK SIGNAL GENERATOR WITH NOISE IMMUNITY CAPABILITY - An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases. | 06-12-2014 |
20140210536 | Technique For Filtering Of Clock Signals - In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC. | 07-31-2014 |
20140253202 | NOISE TOLERANT CLOCK CIRCUIT WITH REDUCED COMPLEXITY - The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal. | 09-11-2014 |
20150116021 | CLOCK GENERATION DEVICE, ELECTRONIC APPARATUS, MOVING OBJECT, AND CLOCK GENERATION METHOD - A clock generation device measures a frequency ratio between a clock signal CK | 04-30-2015 |
20160028381 | FAULT PROTECTION FOR CLOCK TREE CIRCUITRY - An Integrated Circuit (IC) includes clock-tree circuitry and protection circuitry. The clock-tree circuitry is configured to distribute a clock signal across the IC. The protection circuitry is clocked by multiple instances of the clock signal that are sampled at multiple sampling points in the clock-tree circuitry, and is configured to detect a fault in the clock-tree circuitry in response to an abnormality in one or more of the instances of the clock signal. | 01-28-2016 |
20160116937 | DETECTING AND CORRECTING AN ERROR IN A DIGITAL CIRCUIT - A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival signal transition of the input signal, at an intermediate point of a path, the path being one through which the input signal transits. The method further includes predicting an error in the input signal in response to detecting the late arrival signal transition at the intermediate point of the path. In addition, the method includes correcting the error in the input signal by manipulating the timing signal and/or a supply voltage. | 04-28-2016 |