Entries |
Document | Title | Date |
20080197897 | PLL CIRCUIT AND WIRELESS DEVICE - A PLL circuit according to the present invention includes: a voltage controlled oscillator | 08-21-2008 |
20080197898 | Charge pump regulator and method of producing a regulated voltage - A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the current flowing therethrough according to an output-dependent feedback signal. | 08-21-2008 |
20080218228 | Symmetrical Time/Voltage Conversion Circuit - The invention relates to a time/voltage conversion circuit, comprising two simple time/voltage converters (CTT | 09-11-2008 |
20080218229 | ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY - Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit. | 09-11-2008 |
20080224745 | PHASE-LOCKED LOOP AND COMPOUND MOS CAPACITOR THEREOF - Compound MOS capacitors and phase-locked loop with the compound MOS capacitors are disclosed. In the phase-locked loop, the compound MOS capacitors of the loop filter are HV (high voltage) devices, and the voltage control oscillator is a LV (low voltage) device. The compound MOS capacitor comprises a HV PMOS capacitor having a base coupled to a source terminal of a low voltage source and a HV NMOS capacitor having a base coupled to a ground terminal of the low voltage source. The gates of the HV PMOS capacitor and the HV NMOS capacitor are connected together to receive a control voltage. The capacitance of the compound MOS capacitor is near constant in any control voltage. | 09-18-2008 |
20080224746 | Charge Pump Circuit - A charge pump circuit including an input rail, an output rail, a voltage rail, a control line, an MOS input transistor including a gate and a channel connected between the input rail and the voltage rail, and an MOS output transistor including a gate and a channel connected between the output rail and the voltage rail. The gate of the input transistor is connected to the gate of the output transistor and a switch connects the channel of the output transistor to the voltage rail in response to a signal on the control line. The channel of an input cascode transistor connects the channel of the input transistor to the input rail and the channel of an output cascode transistor connects the channel of the output transistor to the output rail. The gate of the input cascode transistor is connected to the gate of the output cascode transistor. | 09-18-2008 |
20080231333 | Spread Spectrum Clock Generator - A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum. | 09-25-2008 |
20080238505 | System and method for an automatic coarse tuning of a voltage controlled oscillator in a phase-locked loop (PLL) - Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop. | 10-02-2008 |
20080252341 | CLOCK SIGNAL DISTRIBUTION CIRCUIT AND INTERFACE APPARATUS USING THE SAME - A clock signal distribution circuit comprises a voltage control and distribution circuit configured to change a delay of a received clock signal in response to a control voltage and to generate a distributed clock signal, and control voltage generation circuit configured to generate the control voltage using a phase difference between received data and the distributed clock signal. | 10-16-2008 |
20080252342 | Charge pump for PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 10-16-2008 |
20080272811 | SIGNAL GENERATING APPARATUS AND METHOD THEREOF - A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode. | 11-06-2008 |
20080290917 | MULTI-BAND FREQUENCY GENERATION METHOD AND APPARATUS - A frequency generation unit (FGU) | 11-27-2008 |
20080297214 | Low Lock Time Delay Locked Loops Using Time Cycle Suppressor - A delay locked loop (DLL) architecture includes a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit. | 12-04-2008 |
20080303565 | DLL CIRCUIT AND RELATED METHOD FOR AVOIDING STUCK STATE AND HARMONIC LOCKING UTILIZING A FREQUENCY DIVIDER AND AN INVERTER - Disclosed is a DLL circuit for avoiding stuck and harmonic locking errors by utilizing a frequency divider and an inverter. This DLL circuit includes: a delay line, a control circuit, a first frequency divider, a second frequency divider and an inverter. The delay line is utilized for receiving a first clock signal and delaying the first clock signal by a delay amount to generate a second clock signal. Additionally, the control circuit, which is coupled to the delay line, is utilized for controlling the delay line. The first frequency divider, which is coupled to the delay line and the control circuit, is utilized for receiving the first clock signal and dividing a frequency of the first clock signal according to a first frequency dividing factor to form a third clock signal. | 12-11-2008 |
20080303566 | SPREAD SPECTRUM CLOCK GENERATOR WITH LOW JITTER - A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N−a)(P−S) through receiving the frequency divided signal and a control word; wherein N, P, and S are integers, and a, b are fractional numbers, and S can be adjusted by the delta-sigma modulator. | 12-11-2008 |
20080309386 | BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE - An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, careful selection of parameters for providing the reference voltage and/or providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation. | 12-18-2008 |
20080315926 | Frequency Synthesizer - Disclosed is a frequency synthesizer. The frequency synthesizer includes a phase frequency detector for generating an up signal and a down signal by detecting frequency and phase differences between a reference signal and a comparison signal, a charge pump for outputting a control signal according to the up signal and the down signal, a voltage controlled oscillator for outputting an oscillation output signal according to the control signal, a duty cycle correction circuit connected with the voltage controlled oscillator to compensate for a duty cycle of the oscillation output signal, and a feedback divider for providing the comparison signal to the phase frequency detector by dividing a frequency of the oscillation output signal. | 12-25-2008 |
20090002038 | Phase Locked Loop with Stabilized Dynamic Response - A hybrid phase locked loop (PLL) circuit for obtaining stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping. | 01-01-2009 |
20090009223 | PLL CIRCUIT AND SEMICONDUCTOR INTEGRATED DEVICE - A charge pump circuit comprises two MOS transistors serially connected between a power supply voltage VDD and ground, a switch SW | 01-08-2009 |
20090033383 | HIGH OUTPUT RESISTANCE, WIDE SWING CHARGE PUMP - Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation. | 02-05-2009 |
20090039929 | Method to Reduce Static Phase Errors and Reference Spurs in Charge Pumps - A phase-locked-loop (PLL) circuit, that includes: a differential phase-frequency detector, a charge pump and at least one logical gate disposed therebetween for providing cancellation of pulses of a substantially equivalent value output by the detector to the charge pump; wherein the at least one logical gate receives the detector output signals and generates control signals for the charge pump such that the pulses of substantially equivalent value are eliminated. | 02-12-2009 |
20090085621 | LOOP FILTERS - Loop filters are provided, in which a first resistor comprises a first terminal coupled to a first node, and a second terminal coupled to a second node; a first capacitor is coupled between the second node and a ground voltage, a second resistor comprises a first terminal coupled to the first node and a second terminal coupled to a third node. An operational amplifier comprises a non-inversion input terminal coupled to the second node, an inversion input terminal coupled to the third node, and an output terminal, and a second capacitor is coupled between the output terminal of the operational amplifier and the third node. | 04-02-2009 |
20090108892 | FREQUENCY SYNTHESIZER - A frequency synthesizer includes: a fractional-N synthesizer configured to provide, in a locked condition, an output signal with an output frequency based on an input signal with a reference frequency, the fractional-N synthesizer including a charge pump outputting a current to be calibrated; a lock detector coupled to the fractional-N synthesizer to detect the locked condition, the lock detector being configured to send a first signal indicating the detection; a calibration component coupled to the lock detector and the fractional-N synthesizer, the calibration component being configured to provide a second signal to calibrate the current after receiving the first signal, based on a voltage sampled from the fractional-N synthesizer; and a current source array coupled to the calibration component and the fractional N synthesizer, the current source array being configured to calibrate the current based on the second signal. | 04-30-2009 |
20090115473 | LOOP FILTER, PHASE-LOCKED LOOP, AND METHOD OF OPERATING THE LOOP FILTER - A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current. | 05-07-2009 |
20090121759 | FAST-SWITCHING LOW-NOISE CHARGE PUMP - In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump. | 05-14-2009 |
20090121760 | Charge pump for PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 05-14-2009 |
20090128204 | Time delay apparatus - A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by. phase shifting the digital signal according to the phase control signal. | 05-21-2009 |
20090134923 | ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL) - A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL. | 05-28-2009 |
20090153204 | PHASE LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME - To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal. | 06-18-2009 |
20090160510 | BIAS VOLTAGE GENERATION CIRCUIT AND CLOCK SYNCHRONIZING CIRCUIT - Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage. | 06-25-2009 |
20090160511 | PLL CIRCUIT - The PLL circuit includes: a voltage control oscillating circuit including: a voltage-current converter circuit; a current adder; and a current control oscillating circuit, the voltage control oscillating circuit outputting a pulse having a frequency corresponding to a control voltage and a control current; a phase detector which outputs a first control signal and a second control signal based on a phase difference between the pulse and a reference pulse having a frequency which should be generated by the voltage control oscillating circuit; a first charge pump circuit which outputs one of a first charge current and a first discharge current in accordance with the first control signal; a loop filter which generates the control voltage in accordance with the one of the first charge current and the first discharge current, and then outputs the generated control voltage to the voltage control oscillating circuit; and a second charge pump circuit which generates the control current serving as one of a second charge current and a second discharge current in accordance with the second control signal, and then outputs the generated control current to the voltage control oscillating circuit. | 06-25-2009 |
20090167385 | PHASE LOCKED LOOP DEVICE AND CONTROL METHOD THEREOF - A phase locked loop device is provided. The phase locked loop device includes a phase/frequency detector, a charge pump, a low pass filter, a voltage-controlled oscillator, and a control unit. The phase/frequency detector generates a compared signal corresponding to a phase difference between a reference clock signal and a feedback clock signal. The charge pump coupled to the phase/frequency detector generates a pump current according to the compared signal. The low pass filter coupled to the charge pump generates an operating voltage corresponding to the pump current. The voltage-controlled oscillator coupled to the low pass filter generates an output clock signal in response to the operating voltage. The control unit coupled to the low pass filter and the voltage-controlled oscillator constrains the operating voltage to a predetermined voltage level when the frequency of the output clock signal is out of a predetermined frequency range. | 07-02-2009 |
20090167386 | Charge pumping circuit, clock synchronization circuit having the charge pumping circuit, and method for operating the clock synchronization circuit - A charge pumping circuit includes a first charge pump configured to perform a charge pumping operation on an output terminal in response to a first pumping control signal, an auxiliary charge pumping controller configured to generate a second pumping control signal activated during a predetermined section of an activation period of the first pumping control signal and a second charge pump configured to perform a charge pumping operation on the output terminal in response to the second pumping control signal. | 07-02-2009 |
20090167387 | DELAY-LOCKED LOOP FOR TIMING CONTROL AND DELAY METHOD THEREOF - A delay-locked loop for timing control, includes a voltage-controlled delay line that delays a reference clock to generate a multi-phase clock comprising a plurality of delayed phase clocks; and an up/down controller that receives one of the delayed phase clocks as a feedback clock and generates a frequency up/down control signal based on whether a rising edge of the feedback clock coincides with a falling edge of the reference clock. The delay-locked loop further includes a charge pump that charges or discharges a loop filter connected to the voltage-controlled delay line according to a frequency up/down control signal from the up/down controller; and a harmonic lock detector that compares phases of multiple ones of the delayed phase clocks with a phase of the reference clock, and operates such that the multi-phase clock is locked within a first cycle of the reference clock. | 07-02-2009 |
20090174446 | SYSTEMS AND METHODS FOR CALIBRATING THE LOOP BANDWIDTH OF A PHASE-LOCKED LOOP (PLL) - A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A Programmable charge pump current is tuned to the calculated first charge pump current. | 07-09-2009 |
20090184740 | Phase-Locked Loop Circuit with Accelerated Frequency Acquisition - Frequency acquisition is accelerated in a phase-locked loop circuit. A duration of time for sinking current from or sourcing current to a loop filter is calculated in order to accelerate frequency acquisition of a reference frequency of a reference signal and a feedback frequency of a feedback signal fed back from a controlled oscillator when the feedback signal frequency is changed or frequency of the reference signal is changed by a predetermined amount. The feedback signal frequency is changed or frequency of the reference signal is changed by the predetermined amount. Sinking current from or sourcing current to a loop filter electrically connected to the controlled oscillator for the duration of time is performed resulting in the reduction of the time for frequency acquisition. | 07-23-2009 |
20090189654 | Common-Mode Feedback Method Using a Current Starved Replica Biasing - A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion. | 07-30-2009 |
20090189655 | PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT - A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage. | 07-30-2009 |
20090195276 | System and method for implementing a digital phase-locked loop - An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter. | 08-06-2009 |
20090201058 | CHARGE PUMP FOR PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operations amplifier also mitigates the effects of low power supply voltage. | 08-13-2009 |
20090206894 | Phase-Locked Loop with Adaptive Performance - A phase-locked loop capable of being dynamically configured to optimize phase-noise performance during different modes of operation. The phase-locked loop may include a switchable charge pump, loop filter and voltage-controlled oscillator having auxiliary circuit components that may be switched in and out to achieve calibration settings for optimizing phase-noise performance for different modes of operation, while minimizing unnecessary power consumption, and without disturbing the stability of the phase-locked loop. | 08-20-2009 |
20090206895 | PHASE SYNCHRONIZATION APPARATUS - A phase synchronization apparatus includes an oscillator gain setting member configured to discriminate a frequency by sequentially delaying input clock signal after dividing the input clock signal at a predetermined division ratio and to generate an oscillator gain setting signal by using discriminated frequency information, and a phase locked loop (PLL) circuit configured to oscillates output clock signal having a frequency corresponding to the oscillator gain setting signal in response to the input clock signal. | 08-20-2009 |
20090237131 | Phase locked loop - A disclosed exemplary embodiment is a phase locked loop comprising a main charge pump driven by a phase error signal, and providing a first input to a loop filter. An auxiliary charge pump driven by the phase error signal feeds a second input of the loop filter. The loop filter can be an active loop filter comprising an operational amplifier and a feedback RC network. The first input of the active loop filter can be an inverting input of the operational amplifier and the second input can be a non-inverting input of the operational amplifier. An on-chip stabilizing capacitor fed by the auxiliary charge pump and coupled to the second input of the loop filter is significantly smaller than the conventional stabilizing capacitors. The loop filter outputs a regulating voltage for regulating the oscillation frequency of a voltage controlled oscillator in the phase locked loop. | 09-24-2009 |
20090237132 | Phase-locked loop - A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations. | 09-24-2009 |
20090243670 | SELF-REGULATED CHARGE PUMP WITH LOOP FILTER - One embodiment described is a charge pump arrangement that includes at least one input node and two output nodes. A regulator is included to regulate at least one of the two output nodes, the regulator is decoupled from one of the two output nodes, and the regulator has at least one input coupled directly to virtual ground. | 10-01-2009 |
20090243671 | DISTURBANCE SUPPRESSION CAPABLE CHARGE PUMP - One embodiment described is charge pump arrangement that includes a regulator to regulate signals associated with two output nodes. A switching mechanism may be coupled to the regulator. The switching mechanism is to interrupt the regulator. | 10-01-2009 |
20090243672 | MULTI-POLE DELAY ELEMENT DELAY LOCKED LOOP (DLL) - In general, in one aspect, the disclosure describes a delay line including a cascade of delay stages where each stage delays the phase a defined amount. Each delay stage includes an active voltage control delay element and one or more passive delay elements (e.g., resistive-capacitive (RC) networks). The aggregate amplitude gain roll-off of an active/passive multi pole delay stage delaying the phase a defined amount is less than the amplitude gain roll-off of a single pole delay stage delaying the phase the defined amount. Accordingly jitter amplification of the active/passive multi pole delay stage is less than that of a single pole delay stage. The power consumption of an active/passive multi pole delay stage is less than an all active multi pole delay stage. | 10-01-2009 |
20090243673 | PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP - A PLL (phase locked loop) system includes a PLL and a lock detector. The PLL is for outputting a phase-locking clock signal. The lock detector is coupled to the PLL for detecting whether or not the frequency of the phase-locking clock signal falls within a predetermined frequency range and detecting whether or not the phase-locking clock signal is stable. If the frequency of the phase-locking clock signal has fallen within the predetermined frequency range and the phase-locking clock signal is stable by detection, the lock detector outputs a lock signal. | 10-01-2009 |
20090243674 | Fractional-N Phased-Lock-Loop (PLL) System - In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented. | 10-01-2009 |
20090243675 | Optimization Method For Fractional-N Phased-Lock-Loop (PLL) System - In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented. | 10-01-2009 |
20090243676 | Design Structure For Fractional-N Phased-Lock-Loop (PLL) System - In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. A method in a computer-aided design system for generating a functional design model of a fractional-N phased-lock-loop (PLL) structure is provided in one embodiment. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is presented in another embodiment. | 10-01-2009 |
20090256602 | VARIABLE LOOP BANDWIDTH PHASE LOCKED LOOP - An apparatus comprising a voltage controlled oscillator, a first charge pump, a second charge pump, a switch circuit and a comparator circuit. The voltage controlled oscillator may be configured to generate an output signal oscillating at a first frequency in response to a control signal. The charge pump circuit may be configured to generate a first component of the control signal in response to a first adjustment signal and a second adjustment signal. The second charge pump may be configured to generate a second component of the control signal in response to a first intermediate signal and a second intermediate signal. The switch circuit may be configured to generate the first intermediate signal and the second intermediate signal in response to the first adjustment signal and the second adjustment signal. The comparator circuit may be configured to generate the first and second adjustment signals in response to a comparison between (i) an input signal having a second frequency and (ii) the output signal. | 10-15-2009 |
20090261875 | ELECTRONIC CIRCUIT - An electric circuit, for use in a phase lock loop circuit, the electric circuit comprising: a first circuit element, being a phase frequency detector or a charge pump; at least one LC resonant loop, the first circuit element forming part of the loop; and means arranged to reduce ringing in said at least one LC resonant loop. | 10-22-2009 |
20090261876 | VOLTAGE CONTROLLED OSCILLATOR - An embodiment of the voltage controlled oscillator is provided. The oscillator comprises a first inductor set, a second inductor set, a second capacitor, a voltage source and a negative resistance element. The inductance of the second inductor set is k times the inductance of the first inductor set. The voltage source applies an ac voltage to the second inductor set. The negative resistance element is coupled to the second inductor set to provide a negative resistance to resonate the second capacitor at the second inductor set. | 10-22-2009 |
20090267662 | FAST RESPONSE PHASE-LOCKED LOOP CHARGE-PUMP DRIVEN BY LOW VOLTAGE INPUT - Phase-locked loop charge pump driven by low voltage input. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current transistor providing a sourcing current, wherein the sourcing current transistor is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump, and a sinking control circuit uses low-voltage sinking control signals to selectively cause the charge pump to sink the sinking current from the output. | 10-29-2009 |
20090273379 | Self-Biased Phase Locked Loop and Phase Locking Method - The present invention discloses a self-bias phase locked loop including a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a divider and a bias current converter. A charging or discharging current output from the charge pump equals to a first control current. A resistor of the loop filter is controlled by a first control voltage a second control voltage which is adjusted according to the first control voltage and a second control current. The loop filter boosts or lowers the first control voltage according to the charging or discharging current output from the charge pump. The voltage control oscillator generates a bias current according to the first control voltage and increases or decreases an oscillation frequency according to the boosted or lowered first control voltage, and symmetric loads of the voltage control oscillator are controlled by the first control voltage. The first control current output from the bias current converter equals to the ratio of the bias current to a constant, and the second control current output from the bias current converter equals to the ratio of the bias current to a frequency division factor. The circuit of the self-bias phase locked loop is simple and a low jitter. | 11-05-2009 |
20090289673 | VOLTAGE CONTROLLED OSCILLATORS AND PHASE-FREQUENCY LOCKED LOOP CIRCUIT USING THE SAME - A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal. | 11-26-2009 |
20090289674 | PHASE-LOCKED LOOP - A phase-locked loop includes a phase detector, a charge pump and a controllable oscillator. The phase detector is supplied by a first supply voltage and is utilized for comparing a phase difference between an reference input signal and a feedback signal based on an output signal to generate at least one detect signal. The charge pump is supplied by a second supply voltage, and is utilized for generating a control signal with charge amounts according to the detect signal, where the first supply voltage is different from the second supply voltage. The controllable oscillator is utilized for generating the output signal according to the control signal, wherein a frequency of the output signal is adjusted by the control signal. | 11-26-2009 |
20090295440 | Systems and Methods for Cancelling Phase-Locked Loop Supply Noise - One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise. | 12-03-2009 |
20090302907 | CIRCUIT ARRANGEMENT FOR PRODUCING A DEFINED OUTPUT SIGNAL - A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD. | 12-10-2009 |
20090302908 | OSCILLATOR AND A TUNING METHOD OF A LOOP BANDWIDTH OF A PHASE-LOCKED-LOOP - There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal. | 12-10-2009 |
20090315598 | CONSTANT VOLTAGE BOOST POWER SUPPLY - A constant voltage boost power supply according to an aspect of the invention includes a voltage-controlled variable frequency oscillator that produces and supplies a clock signal and changes an oscillating frequency of the supplied clock signal according to an input control voltage; a charge pump into which the clock signal is fed, the charge pump performing a pumping operation in synchronization with the clock signal to boost an input voltage and supply an output voltage in which the input voltage is boosted; a voltage dividing circuit that divides the output voltage of the charge pump to supply a monitor voltage; and a differential amplifier into which the monitor voltage and a reference voltage are fed, the differential amplifier amplifying a potential difference between the monitor voltage and the reference voltage to supply the control voltage. | 12-24-2009 |
20090315599 | CIRCUIT WITH A REGULATED CHARGE PUMP - A circuit, method for regulation, and use thereof is provided, whereby the circuit can include a charge pump that is connected to a supply voltage terminal in order to produce a pump voltage from a supply voltage, and includes a control circuit whose inputs are connected to the output of the charge pump and to the supply voltage terminal in order to sense a difference between the pump voltage and the supply voltage as a controlled variable. The circuit is designed to compare the controlled variable to a reference variable, and output is connected to a control input of the charge pump in order to control the charge pump as a function of the comparison. | 12-24-2009 |
20100001771 | PHASE LOCKED LOOP WITH LEAKAGE CURRENT CALIBRATION - A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering. | 01-07-2010 |
20100052747 | PLL FREQUENCY SYNTHESIZER - A PLL frequency synthesizer | 03-04-2010 |
20100060333 | DIGITAL CHARGE PUMP PLL ARCHITECTURE - A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator. | 03-11-2010 |
20100066420 | Wide Range Operational Charge Pump Circuit - A charge pump that includes cascade transistors and current mirror circuitry to form a folded cascade structure that isolates the control inputs from the charge pump output and also increases the range of the output. The charge pump includes inputs to receive UP and DN (down) control signals and provides an output current that is based on the control signals. The charge pump may be configured as either a differential or non-differential device. The switching transistors that receive the control signals may use a lower voltage than the current source transistors in the charge pump In differential-type embodiments of the present charge pump, an amplifier can be used to control current source transistors based on differences between the output voltages of the charge pump, thereby adjusting the current flowing through the current source transistors and driving the average of the output voltages to a desired common mode voltage. | 03-18-2010 |
20100073048 | PHASE LOCKED LOOP AND CALIBRATION METHOD - A phase locked loop (PLL) directly uses a charge pump and loop filter therein for fast and low-costly calibration. The PLL comprises a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to adjust the time measured by the counting device to a desired time. | 03-25-2010 |
20100073049 | SWITCHED-CAPACITOR CHARGE PUMP DEVICE FOR GENERATION OF OUTPUT DIRECT-CURRENT VOLTAGE WITH WIDE AMPLITUDE RANGE - A switched-capacitor charge pump device is proposed, which is designed for integration to a circuit system, such as a PLL (phase-locked loop) circuit system, for generation of an output direct-current (DC) voltage with a wide amplitude range; and which is characterized by the utilization of two switched-capacitor circuit units in addition to the output capacitor circuit and the utilization of an output voltage comparing circuit (such as a Schmitt trigger) for comparing the end-result output DC voltage against a half-amplitude drive voltage such that when the switched-capacitor circuit units are subjected to a charging-discharging action for voltage pump-up or pump down operations, the switched-capacitor circuit units are switched between a full-amplitude drive voltage and a half-amplitude drive voltage. This feature allows the invention to provide an output DC voltage with a wider amplitude range than prior art. | 03-25-2010 |
20100073050 | DIFFERENTIAL SIGNAL DRIVEN DIRECT-CURRENT VOLTAGE GENERATING DEVICE - A differential signal driven direct-current voltage generating device is proposed, which is designed for use with a PLL (phase-locked loop) circuit or a DLL (delay-locked loop) circuit system for generating an output of a direct-current (DC) voltage in response to a pair of differential signals, such as phase-difference signals; and which is characterized by the utilization of a capacitor-switched voltage doubler for doubling the output voltage of a charge pump so that the doubled voltage can be used as a control voltage for a PLL-VCO (voltage-controlled oscillation) or a DLL-VCDL (voltage-controlled delay line) circuit for generation of an output oscillating signal with a wider frequency range. | 03-25-2010 |
20100073051 | LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS - ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range. | 03-25-2010 |
20100073052 | FRACTIONAL RESOLUTION INTEGER-N FREQUENCY SYNTHESIZER - Embodiments of the invention may provide for a frequency synthesizer capable to generate an output signal in which the frequency is a fractional portion of the reference frequency without a fractional divider. Based on mathematical relationship (“relatively prime”) between the reference frequency and other injection frequencies mixed with the output signal of a voltage controlled oscillator, the synthesizer is able to generate signals evenly spaced in the frequency domain like Fractional-N PLLs. The synthesizer may include an Integer-N PLL, a SSB mixer, frequency dividers, and frequency multipliers. A Integer-N PLL may include a Phase and Frequency Detector, a Charge Pump, a Loop Filter and a Dual Modulus Divider. By not requiring a fractional divider, the frequency synthesizer is able to avoid adopting any compensation circuits such as Sigma-Delta modulator to suppress fractional spurs. Therefore, the chip area, power consumption and complexity will be reduced considerably. | 03-25-2010 |
20100085090 | CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL) - A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal. | 04-08-2010 |
20100085091 | PROPORTIONAL PHASE COMPARATOR AND METHOD FOR PHASE-ALIGNING DIGITAL SIGNALS - Embodiments of a proportional phase comparator and method for aligning digital signals are generally described herein. In some embodiments, circuitry to align digital signals comprises a proportional phase comparator that generates triangular-shaped pulses for application to a charge pump. The triangular-shaped pulses may reduce an amount of charge injection in the charge pump close to convergence. | 04-08-2010 |
20100085092 | Phase-Locked Loop Integrated Circuits Having Dual Feedback Control - Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump. | 04-08-2010 |
20100085093 | MULTI-PHASE CLOCK SYSTEM - The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLK | 04-08-2010 |
20100090734 | WIDE DYNAMIC RANGE CHARGE PUMP - A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage. | 04-15-2010 |
20100102859 | LC VOLTAGE CONTROLLED OSCILLATOR TANK WITH LINEARIZED FREQUENCY CONTROL - Over the past few decades, phased locked loops or PLLs have become increasingly common in a variety of microelectronic applications. As such, the PLLs have both decreased in size and increased in speed, following the same trend as all other microelectronics. With this change in size and speed, alternative designs for voltage controlled oscillator tanks or VCOs (and other components of PLLs) are being developed. Here, an LC VCO with a correction circuit (for linearizing the frequency versus control voltage characteristics of the VCO) is described that can allow a small and fast PLL to remain generally stable over a wide range of frequencies. | 04-29-2010 |
20100117694 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal. | 05-13-2010 |
20100123493 | System and method for implementing a digital phase-locked loop - An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter. | 05-20-2010 |
20100134161 | Phase Detector Circuit for Automatically Detecting 270 and 540 Degree Phase Shifts - Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal. | 06-03-2010 |
20100134162 | CLOCK SIGNAL GENERATION CIRCUIT - A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal. | 06-03-2010 |
20100134163 | SEMICONDUCTOR INTEGRATED CIRCUIT - A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop. | 06-03-2010 |
20100141311 | Phase-Locked Loop and Bias Generator - A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced. | 06-10-2010 |
20100156483 | DELAY LOCKED LOOP CIRCUIT - The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off. | 06-24-2010 |
20100156484 | FAST-RESPONSE PHASE-LOCKED LOOP CHARGE-PUMP DRIVEN BY LOW VOLTAGE INPUT - Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals. | 06-24-2010 |
20100164570 | DEVICE AND METHOD FOR GENERATING CLOCK SIGNALS FOR DC-DC CONVERTERS - An electronic device includes a DC-DC converter for voltage conversion in a slave mode an in a master mode and including a phase locked loop. The phase locked loop comprises a controlled oscillator, a filter having an integration capacitor coupled to a control input of the controlled oscillator, a charge pump, and a phase frequency detector. In the slave mode, the controlled oscillator, the filter, the charge pump and the phase frequency detector are coupled to operate as the phase locked loop. There is a comparator coupled with an input to a control input of the controlled oscillator and with an output to the charge pump. In the master mode, the comparator is configured to control the charge pump in response to a control signal at the control input of the controlled oscillator when the phase frequency detector is switched off so as to perform a modulation of the control signal at the control input of the controlled oscillator by charging and discharging the integration capacitor. | 07-01-2010 |
20100171535 | CALIBRATION SYSTEM AND METHOD FOR PHASE-LOCKED LOOPS - A method for calibrating a bandwidth of a phase-locked loop begins with detecting an error signal generated by the phase-locked loop in response to a stimulus signal. The difference between the integral of the error signal and a nominal value thereof is computed, and the bandwidth of the phase-locked loop is adjusted based on the computed difference. | 07-08-2010 |
20100182057 | LOCKED LOOPS, BIAS GENERATORS, CHARGE PUMPS AND METHODS FOR GENERATING CONTROL VOLTAGES - Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase detector and a charge pump. The charge pump can either charge or discharge a capacitor as a function of a signal from the phase detector to generate a control voltage. The bias generator can receive the control voltage from the capacitor, and it generates bias voltages corresponding thereto. A portion of the bias generator can have a topography that is substantially the same as at least a portion of the topography of the charge pump. As a result, it can cause the charge pump to charge the capacitor at the same rate that it discharges the capacitor over a relatively wide range of control voltages. The charge pump and the bias generator can also include circuitry for limiting the charging of the capacitor when the control voltage is relatively low. | 07-22-2010 |
20100207673 | ASYMMETRIC CHARGE PUMP AND PHASE LOCKED LOOPS HAVING THE SAME - A charge pump includes a current source configured to generate a first current and a switch circuit including an output node and connected to the current source. The switch circuit is configured to be switched to provide one of the first current to the output node or discharge a second current from the output node according to a phase difference between a reference signal and a feedback signal. The switch circuit is further configured to compare a charge supplied to the output node and a charge discharged from the output node and to adjust an inflow time of the first current to the output node or an outflow time of the second current from the output node according to the comparison result. | 08-19-2010 |
20100225368 | PHASE-LOCKED LOOP CIRCUIT AND AN ASSOCIATED METHOD - The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider. | 09-09-2010 |
20100244914 | CLOCK GENERATOR TO REDUCE LONG TERM JITTER - A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals. | 09-30-2010 |
20100253403 | Radiation-Hardened Charge Pump Topology - A radiation-hardened charge pump circuit is provided. The circuit includes a first charge pump having a first charge pump output, a second charge pump having a second charge pump output, a first coincidence detector receiving as inputs the first charge pump output and the second charge pump output and producing as an output a first coincidence signal, and an analog 2:1 multiplexor for selecting either the first charge pump output or the second charge pump output based on the first coincidence signal. In alternative embodiment, the circuit includes at least three charge pumps, at least two coincidence detectors, decision logic, and a correspondingly-sized analog multiplexor. | 10-07-2010 |
20100259305 | INJECTION LOCKED PHASE LOCK LOOPS - A signal generating circuit for generating an output signal is provided. A phase detection circuit is arranged to detect a phase difference between an input reference signal and a feedback signal, and generate a control signal according to the phase difference. An injected controlled oscillator is arranged to receive the control signal and an injection signal and generate the output signal according to the control signal and the injection signal. A frequency of the output signal is proportional to a frequency of the input reference signal, and a frequency of the injection signal does not equal to the frequency of the output signal. | 10-14-2010 |
20100259306 | PHASE LOCKED LOOP AND METHOD FOR CHARGING PHASE LOCKED LOOP - A phase locked loop (PLL) and a method for charging the PLL are disclosed. The charge circuit includes: a threshold judging module, adapted to output a signal to a receiving module, and when the voltage of a filter reaches a preset threshold, output a valid signal to the receiving module; the receiving module, adapted to receive a trigger signal and output a first control signal to a charging module, and when the signal from the threshold judging module is a valid signal, adapted to output a second control signal to the charging module; the charging module, adapted to charge the filter when receiving the first control signal and stop charging the filter when receiving the second control signal. So that a better voltage may be provided to the PLL to shorten the locking time of the PLL. | 10-14-2010 |
20100259307 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal and the frequency-divided clock signal, and outputting an output signal based on a comparison result; an adder adding output signals from each of the control units; and a low-pass filter filtering an output of the adder and outputting to the voltage-controlled oscillator, wherein setting information related to a frequency division ratio made of N pieces of data cycled and supplied in a sequence in synchronization with the frequency-divided clock signal is supplied to each of the control units with initial values made different from one another and a frequency-division operation and a comparison operation are performed thereby to form a moving average filter by N pieces of control units and to reduce a quantization noise, so that occurrence of a spurious in the output clock signal can be suppressed. | 10-14-2010 |
20100264963 | Clock data recovery circuit and multiplied-frequency clock generation circuit - Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section. | 10-21-2010 |
20100264964 | Pll circuit - There is provided a PLL circuit including a first loop filter and a second loop filter, which includes a current signal generation circuit that includes a first output driver that generates a first current signal to be output to the first loop filter and a second output driver that generates a second current signal to be output to the second loop filter, and a control circuit that selects which of the first output driver and the second output driver is to be activated. | 10-21-2010 |
20100264965 | Fractional-N frequency synthesizer having reduced fractional switching noise - A fractional-N frequency synthesizer having reduced fractional switching noise and spurious signals is provided. The synthesizer includes a voltage controlled oscillator for providing an output signal. A fractional-N divider is responsive to the voltage controlled oscillator for providing a divided output signal having fractional switching noise. A band pass filter is responsive to the fractional-N divider for reducing the fractional switching noise and non-linearities that result in spurious signals. A phase detector is responsive to a reference signal and the band pass filter for providing a control signal representative of the phase difference between the reference signal and the signal from the band pass filter. A loop filter is responsive to the phase detector for filtering the control signal to control the voltage controlled oscillator, the output of the loop filter having reduced fractional switching noise and spurious signals. | 10-21-2010 |
20100271088 | SYNTHESIZER, SYNTHESIZER MODULE, AND RECEPTION DEVICE AND ELECTRONIC DEVICE USING SAME - A synthesizer including an oscillator for outputting an oscillation signal based on an output signal from a comparator, a frequency divider for dividing a frequency of an output signal from the oscillator based on control from a controller, and a temperature sensor for detecting an error between a preset frequency and a frequency based on a reference oscillation signal. The comparator compares an output signal from the frequency divider with an output signal from a MEMS oscillator and outputs a signal indicating the comparison result to the oscillator. The controller changes the frequency division ratio of the frequency divider based on an output signal from the temperature sensor and changes the frequency division ratio in a state in which the frequency division ratio is kept at the past value. Thus, phase noise deterioration in the synthesizer can be suppressed. | 10-28-2010 |
20100271089 | Enhanced polar modulator for transmitter - Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±π/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +π (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics. | 10-28-2010 |
20100283517 | CHARGE PUMP FOR PHASE LOCKED LOOP - A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal ( | 11-11-2010 |
20100289539 | METHOD AND SYSTEM OF OPTIMIZING A CONTROL SYSTEM USING LOW VOLTAGE AND HIGH-SPEED SWITCHING - A phase-locked loop charge pump driven by low voltage input is disclosed. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current source providing a sourcing current, wherein the sourcing current source is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump. A sinking control circuit uses low-voltage sinking control signals at a low voltage and utilizes a low-swing current mechanism to sink the sinking current from the output of the charge pump. In another aspect, the sourcing control circuit is cascode and the sinking circuit is non-cascode. In another aspect the sourcing current source and the sinking current source are both cascode. In another aspect, the sourcing current source is non-cascode and the sinking current source is cascode. In another aspect, the sourcing current source and the sinking current source are both non-cascode. | 11-18-2010 |
20100289540 | DELAY CIRCUIT - In a delay circuit for inputting square waves, fluctuations in the amount of delay brought about by noise pulses present in input signals are reduced. A switch (SW | 11-18-2010 |
20100295586 | PLL INTEGRAL CONTROL - A phase locked loop has an integral control path, in which digital representations of phase error are added over successive time intervals, and a charge pump circuit is configured to charge or discharge an integrating capacitor according to successive resultant sum values, with a voltage on the integrating capacitor used to control an output frequency of a controlled oscillator in the phase locked loop. | 11-25-2010 |
20100295587 | PLL FREQUENCY SYNTHESIZER - In a PLL frequency synthesizer, a loop is constituted by a phase comparison unit, a gate unit, a charge pump, a capacitive element, a potential adjustment unit, a voltage-controlled oscillator, and a feedback division unit. In this loop, the gate unit and the charge pump are provided in parallel with the potential adjustment unit. A charging/discharging current is input from the charge pump to the capacitive element and the potential of a first end of the capacitive element is adjusted by the potential adjustment unit, so that a phase difference between a reference oscillation signal and a feedback oscillation signal input to the phase comparison unit is small. | 11-25-2010 |
20100301911 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals. | 12-02-2010 |
20100315138 | SYNTHESIZER AND RECEPTION DEVICE USING THE SAME - A synthesizer of the present invention includes a synthesizer section that generates an oscillation signal based on a reference oscillation signal output from a MEMS resonator and inputs the oscillation signal to a frequency converter; and a control section that adjusts a frequency of the oscillation signal output from the synthesizer section. In frequency adjustment by the control section, when a frequency adjustment unit of the synthesizer section is defined as predetermined value F in which quality of an output signal from the frequency converter is a quality limit threshold value, frequency adjustment unit Δfcont of the synthesizer section is within predetermined value F. | 12-16-2010 |
20100321074 | METHODS AND APPARATUSES FOR INCREMENTAL BANDWIDTH CHANGES RESPONSIVE TO FREQUENCY CHANGES OF A PHASE-LOCKED LOOP - In a phase-locked loop, a desired change in frequency is indicated. The phase-locked loop locks to the new frequency and a loop bandwidth of the phase-locked loop is changed. In changing the loop bandwidth, a frequency adjustment signal to a voltage-controlled oscillator may include a voltage spike. The voltage spike is reduced by detecting a lock when the reference clock and a feedback clock reach a same frequency, then waiting for a time delay after the detecting the lock, and adjusting a current level of a charge pump pulse by an incremental amount to achieve a fractional portion of a new loop bandwidth. The charge pump pulse is filtered to generate the frequency adjustment signal and the frequency spike reduction process is repeated until the new loop bandwidth is achieved. | 12-23-2010 |
20100321075 | Dual Phase Detector Phase-Locked Loop - A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal. | 12-23-2010 |
20110006820 | Dual Phase-Locked Loop Circuit and Method for Controlling the Same - A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency. | 01-13-2011 |
20110012653 | CHARGE PUMP WITH LOW CHARGE INJECTION AND LOW CLOCK FEED-THROUGH - A charge pump with low charge injection and low clock feed-through for a phase locked loop (PLL). A first source-switched current mirror has a source transistor and an output transistor. The source transistor has a drain connected to a first current source. The output transistor has a drain connected to an output of the charge pump. The gates of the source and output transistors are coupled together by a first conductive link. A switch is coupled between a supply voltage source and a source of the output transistor of the current mirror. A tuner is coupled between the switch and the output transistor of the current mirror. A source of the tuner is coupled to a drain of the switch and to the source of the output transistor. A drain of the tuner is coupled to the first conductive link between the source and output transistors of the current mirror. | 01-20-2011 |
20110018598 | PLL CIRCUIT - A PLL circuit according to the present invention includes a VCO that outputs an VCO signal having a frequency according to an input voltage, a loop filter that feeds a voltage according to an input current to the VCO, a phase comparator that outputs a phase difference pulse having a width according to a phase difference between a first input signal and a second input signal, a charge pump circuit that receives the phase difference pulse, and inputs the current to the loop filter, and a phase-difference-pulse stop unit that stops the input of the phase difference pulse to the charge pump circuit in a non-input state in which an REF signal (reference frequency signal) is not input. The first input signal is the REF signal itself or a signal obtained by dividing the frequency of the REF signal, and the second input signal is the VCO signal itself or a signal obtained by dividing the frequency of the VCO signal. | 01-27-2011 |
20110025387 | Charge Transfer in a Phase-Locked Loop - A phase-locked loop arranged to generate an output signal having a first frequency that is a static value times the frequency of a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided to cause the output signal to have a frequency that is said static value times the frequency of the reference signal, a comparison unit arranged to compare the feedback signal with the reference signal, one or more current generators arranged to output current pulses in dependence on said comparison, a summation unit arranged to receive the current pulses output by the current generator(s) and form a single current pulse therefrom and a loop filter arranged to filter the single current pulse to form a control signal for controlling the signal generator, the phase-locked loop being arranged such that the current generator(s) generate(s) a first current pulse dependent on a phase-difference between the feedback signal and the reference signal and a second current pulse whose magnitude and sign are dependent on an error in the feedback signal that is caused by the variation of the divisor, and the summation unit receives the first and second current pulses and stores an electrical charge representative of those current pulses and the summation unit outputs a single current pulse dependent on the electrical charge stored by the summation unit, said single current pulse being representative of a phase-difference that would have existed between the reference signal and the feedback signal if the feedback signal had been formed by dividing the output signal by said static value and not by the varied divisor. | 02-03-2011 |
20110025388 | Charge Pump For Phase-Locked Loop - A current generator for a phase-locked loop arranged to generate an output signal having predetermined frequency-relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided, a comparison unit arranged to compare the feedback signal with the reference signal and output a first error signal indicative of the phase-difference between the feedback signal and the reference signal to the current generator and a loop filter arranged to filter a current signal output by the current generator to form a control signal for controlling the signal generator, the current generator being capable of receiving the first error signal and generating a current in dependence thereon, receiving a second error signal indicative of an error in the feedback signal caused by the variation of the divisor by which the output signal is divided and generating a current having a magnitude and sign that is dependent on that error and combining the currents generated in dependence on the first error signal and the second error signal to form a current signal output to the loop filter that is representative of an overall error in the output signal of the phase-locked loop relative to the reference signal. | 02-03-2011 |
20110050302 | CHARGE PUMP CIRCUIT AND PLL CIRCUIT USING THE SAME - A charge pump circuit ( | 03-03-2011 |
20110057694 | REGULATOR HAVING INTERLEAVED LATCHES - A charge pump system ( | 03-10-2011 |
20110057695 | PHASE LOCK LOOP AND CONTROL METHOD THEREOF - A phase lock loop (PLL) featuring automatic stabilization is provided, in which a first charge pump is coupled to a driving control signal to generate a first current, a filter with a zero-point path and the first charge pump are coupled at a first node, and a current adjustment circuit adjusts a current on the first node according to a voltage difference in the zero-point path. | 03-10-2011 |
20110057696 | Frequency Calibration Apparatus of Phase Locked Loop and Method Thereof - A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve. | 03-10-2011 |
20110063002 | BIAS CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT USING THE SAME - A bias circuit for generating an output bias current includes a first transistor, a passive component, a second transistor, and a bias current generator. The first transistor has a first node coupled to a first reference voltage, a second node, and a control node. The passive component is coupled between the first reference voltage and the control node of the first transistor. The second transistor has a first node coupled to the control node of the first transistor, a control node coupled to the second node of the first transistor, and a second node for providing the output bias current according to a current passing through the passive component. The bias current generator is coupled to the second node of the first transistor, and implemented for providing the first transistor with a bias current. | 03-17-2011 |
20110063003 | PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE - Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals. | 03-17-2011 |
20110063004 | Frequency synthesis system with self-calibrated loop stability and bandwidth - In a frequency synthesis system with self-calibrated loop stability and bandwidth, a detector produces a detection signal based on a difference between an input signal and a feedback signal; a charge pump produces a control signal based on the detection signal; a filter produces a tuning signal and a source current based on the control signal; a bias circuit produces first and second bias signals; a controllable oscillator produces a differential output signal with a selected specific frequency; a differential-to-single converter produces an output signal with the selected specific frequency; a programmable frequency divider produces the feedback signal; a current mirror circuit receives the source current for producing a mirror current; a compensation circuit produces a compensation current based on the mirror current for compensating the variation of the damping factor and the bandwidth-to-reference frequency ratio. | 03-17-2011 |
20110080198 | CHARGE PUMP CIRCUIT, AND METHOD OF CONTROLLING CHARGE PUMP CIRCUIT - A charge pump circuit of the present invention comprises a resistance voltage divider provided between a reference voltage source and an output terminal, a differential amplifier which has an inverting input terminal applied with a divided voltage portion from the resistance voltage divider and a non-inverting input terminal applied with a comparison voltage and is configured to output an output signal obtained by amplifying a potential difference between the divided voltage portion and the comparison voltage through an output terminal, a clock feeder configured to output first and second clock signals according to an original clock signal, and a pump circuit section which is applied with the first and second clock signals alternately and control an output voltage at an output terminal, and the clock feeder is configured to regulate amplitude levels of the first and second clock signals according to the voltage of the output signal. | 04-07-2011 |
20110080199 | Bandwidth Control Apparatus for Phase Lock Loop and Method Thereof - A loop bandwidth control apparatus applied to a phase locked loop (PLL) includes a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first filter module and the second loop filter module output a first voltage and a second voltage, respectively. The second loop filter module has a bandwidth different from that of the first loop filter module. According to one of the first voltage and the second voltage, the control module generates a bandwidth control signal. According to the bandwidth control signal, the first switching module forms a path between a charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between a voltage-controlled oscillator (VCO) and one of the first loop filter module and the second loop filter module. | 04-07-2011 |
20110084742 | DYNAMIC CURRENT SUPPLYING PUMP - A pump system that can dynamically increase its current capability includes: a pump circuit, for producing an output voltage; an oscillator, for driving the pump circuit to pump at a particular frequency according to a pump enable signal; a limiter, coupled to both the oscillator and the output voltage fed back from the pump circuit, for generating the pump enable signal to the oscillator according to the output voltage feedback signal; and an edge timer, coupled to both the oscillator and the pump enable signal, for driving the oscillator to operate at an increased frequency according to a threshold parameter of the pump enable signal. | 04-14-2011 |
20110084743 | PHASE LOCKED LOOP AND VOLTAGE CONTROLLED OSCILLATOR THEREOF - A phase locked loop (PLL) and a voltage controlled oscillator (VCO) thereof are provided. The VCO includes a ring oscillator circuit and a control circuit. The ring oscillator circuit is used for providing an output clock signal; and the control circuit is coupled to the ring oscillator circuit, and used for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain. | 04-14-2011 |
20110102032 | LOOP FILTER - A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node. such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit. | 05-05-2011 |
20110102033 | LOW POWER CLOCKING SCHEME FOR A PIPELINED ADC - Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount of power. Here, a DLL is provided with a modified charge pump that allows for reduced power consumption. | 05-05-2011 |
20110102034 | CHARGE PUMP FOR PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 05-05-2011 |
20110109355 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first frequency-divided clock to a selector. The frequency divider outputs a plurality of second frequency-divided clocks each shifted in phase by 1/m of a period based on a control signal of a control circuit. The selector selects two frequency-divided clocks having the closest phase shift from among the first and second frequency-divided clocks. Based on a weighting data signal output from the control circuit, a phase interpolation circuit phase-shifts the frequency-divided clock by a phase shift obtained by dividing the phase difference between the two frequency-divided clocks, and outputs the resultant clock as an output clock. | 05-12-2011 |
20110115535 | LOOP FILTER AND PHASE LOCKED LOOP INCLUDING THE SAME - Provided is a loop filter which receives first and second currents whose current ratio is n (where n is a natural number). The loop filter includes a first-order filter path, a second-order filter path, and a third-order filter path. The first-order filter path includes an operational amplifier generating an output impedance by increasing by as much as n times an impedance of a second input node to which the second current is applied. The first-order filter path performs a first-order filtering on the first current applied to a first input node by using the operational amplifier. The second-order filter path performs a second-order filtering on the first current applied to the first input node. The third-order filter path performs a third-order filtering on the first current applied to the first input node. | 05-19-2011 |
20110121874 | Systems and Methods for PLL Linearity Measurement, PLL Output Duty Cycle Measurement and Duty Cycle Correction - Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%. | 05-26-2011 |
20110133799 | CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP - A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop. | 06-09-2011 |
20110133800 | CHARGE PUMPING CIRCUIT AND CLOCK GENERATOR - A charge pumping circuit comprises: a charging pump capacitance; a charging unit; a discharging unit; a detection resistor having one terminal and the other terminal, the one terminal being connected between a first node and a second node in a second mode; a voltage source for supplying a reference voltage to the other terminal of the detection resistor; a correction unit for correcting a charging current output from the charging unit and a discharging current that is to be sunk by the discharging unit to equalize the charging current and the discharging current in the second mode, based on a difference between a voltage of the one terminal of the detection resistor and the reference voltage when the charging unit outputs the charging current to the one terminal of the detection resistor and the discharging unit sinks the discharging current from the one terminal of the detection resistor. | 06-09-2011 |
20110148485 | PHASE-LOCKED LOOP CIRCUIT COMPRISING VOLTAGE-CONTROLLED OSCILLATOR HAVING VARIABLE GAIN - A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition. | 06-23-2011 |
20110156777 | CLOCK AND DATA RECOVERY CIRCUIT WITH PROPORTIONAL PATH - A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path. | 06-30-2011 |
20110187425 | PHASE-LOCKED LOOP SYSTEMS USING ADAPTIVE LOW-PASS FILTERS IN SWITCHED BANDWIDTH FEEDBACK LOOPS - Methods and systems directed toward a PLL circuit ( | 08-04-2011 |
20110187426 | HIGH SPEED CHARGE PUMP - In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage. | 08-04-2011 |
20110199136 | CHARGE PUMP AND PHASE-DETECTING APPARATUS, PHASE-LOCKED LOOP AND DELAY-LOCKED LOOP USING THE SAME - A charge pump including a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch, and a reset switch is provided. First terminals of the first and the third switch are coupled to the first current source. First terminals of the second and the fourth switch are coupled to the second current source. Second terminals of the first, the second, and the reset switch are coupled to an output terminal of the charge pump. A first terminal of the reset switch is coupled to the second terminals of the third and the fourth switch. Control terminals of the first, the second, the third, and the fourth switch respectively receive a first control signal, a second control signal, an inverted signal of the first control signal, and an inverted signal of the second control signal. | 08-18-2011 |
20110199137 | LOOP FILTER AND VOLTAGE CONTROLLED OSCILLATOR FOR A PHASE-LOCKED LOOP - A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (g | 08-18-2011 |
20110204937 | PHASE- LOCKED LOOP WITH SWITCHED PHASE DETECTORS - A phase-locked loop includes: a voltage-controlled oscillator (VCO) system receiving one or more control signals and in response thereto generating a PLL output signal; a plurality of phase detectors for comparing a reference signal having a reference frequency to a PLL feedback signal having a PLL feedback frequency derived from the PLL output signal, and in response thereto to output a comparison signal; and a plurality of signal processing paths each connected to an output of a corresponding one of the phase detectors for outputting a phase detection output signal. The signal processing paths have different frequency responses from each other. In operation only one of the phase detectors is activated, and a switching arrangement selectively switches between outputs of the signal processing paths to select the phase detection output signal from the activated phase detector to generate the control signal(s) for the VCO system. | 08-25-2011 |
20110204938 | Charge Pump For a Phase-Locked Loop - A charge pump circuit for connection to another circuit via an output node ( | 08-25-2011 |
20110204939 | Circuit for Clamping Current in a Charge Pump - A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump. | 08-25-2011 |
20110204940 | CLOCK GENERATOR, SEMICONDUCTOR DEVICE, AND CLOCK GENERATING METHOD - There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop. | 08-25-2011 |
20110215847 | Frequency synthesizer - The frequency synthesizer has two fixed frequency dividers, two charge pumps, five capacitors, a voltage controlled oscillator, and a transconductance voltage amplifier. The pulse widths of the input reference signal and the output signal are compared and the resultant signal is coupled to the oscillator to adjust its frequency. The circuit exhibits accurate frequency synthesizing, and thus can be used in wireless communication and signal processing systems. It provides a precise integer and fractional frequency division with a low phase noise. Moreover, it has a simple and compact structure that can be implemented in integrated circuit technologies such as CMOS. | 09-08-2011 |
20110215848 | FREQUENCY SYNTHESIZER - A frequency synthesizer includes a controlled oscillator configured to extend a temperature range and phase noise of the synthesizer without compromising the frequency coverage of the synthesizer. The frequency synthesizer also includes bias generation circuitry that sets a bias current of a charge pump to reduce bandwidth variations of the synthesizer. The frequency synthesizer further includes switching circuitry to dynamically turn a charge pump on and off to reduce effects of current leakage in the charge pump. | 09-08-2011 |
20110215849 | CHARGE PUMP FOR PHASE LOCKED LOOP - A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal ( | 09-08-2011 |
20110221494 | PHASE-LOCKED LOOP START UP CIRCUIT - A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit. | 09-15-2011 |
20110227615 | PLL WITH CONTINUOUS AND BANG-BANG FEEDBACK CONTROLS - Phase locked loops (PLLs) are commonly employed in synthesizers, and there is ever increasing pressure to build PLLs that have better performance using low cost and low voltage digital complementary metal oxide semiconductor (CMOS) processes. Here, a PLL is generally provided that employs several continuous (analog) control loops and a digital “Bang-Bang” control loop. This PLL provide superior performance over other conventional PLL in terms of its low noise characteristics and its rapid settling time. | 09-22-2011 |
20110227616 | PHASE LOCKED LOOP CIRCUIT, METHOD OF DETECTING LOCK, AND SYSTEM HAVING THE CIRCUIT - Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal. | 09-22-2011 |
20110227617 | PHASE LOCKED LOOP CIRCUIT AND SYSTEM HAVING THE SAME - A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other. | 09-22-2011 |
20110234272 | METHOD AND APPARATUS FOR CHARGE PUMP LINEARIZATION IN FRACTIONAL-N PLLS - Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls. | 09-29-2011 |
20110234273 | METHOD AND APPARATUS FOR CHARGE LEAKAGE COMPENSATION FOR CHARGE PUMP - An apparatus is disclosed, the apparatus comprising: a charge pump for receiving a phase signal representing a result of a phase detection and for outputting a current flowing between an internal node and an output node; a capacitive load shunt at the output node; a current source controlled by a bias voltage for outputting a compensation current to the internal node; a current sensor inserted between the internal node and the output node for sensing the current; and a feedback network for adjusting the bias voltage in accordance with an output of the current sensor. | 09-29-2011 |
20110234274 | SEMICONDUCTOR DEVICE - A digital compensation phase locked loop circuit of a semiconductor device includes a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage, and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator whose gain is determined by an applied voltage is discretely changed by a control signal of the digital compensation circuit. The digital compensation circuit dynamically controls the gain so as to secure the optimum phase margin by applying a load (capacitor) to the oscillation node of the voltage controlled oscillator with respect to a phase lead and decreasing the load (capacitor) with respect to a phase delay. | 09-29-2011 |
20110234275 | PLL CIRCUIT - In the PLL circuit including a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator, the loop band after the locking can be expanded in such a manner that, when the phase difference between a reference clock signal and a feedback clock signal is larger than a threshold value, an output current corresponding to the phase difference is outputted by reducing the change of the output current per unit amount of the phase difference, and that, when the phase difference is at most the threshold value, the output current corresponding to the phase difference is outputted by increasing the change of the output current per unit amount of the phase difference. | 09-29-2011 |
20110234276 | VOLTAGE-CURRENT CONVERTER CIRCUIT AND PLL CIRCUIT HAVING THE SAME - According to an embodiment, a voltage-current converter circuit includes a first current mirror circuit, a first transistor, a variable resistor, a second transistor and a first current output unit. The first current mirror circuit includes a first conductivity type transistor supplied with a first voltage, and the first current mirror circuit is configured to produce a second electric current based on a first electric current. The first transistor has a second conductivity type, and the first electric current flows through the first transistor. One end of the variable resistor is connected to a source of the first transistor, the other end of the variable resistor is supplied with a second voltage, and a resistance value of the variable resistor changes depending on an input control voltage. The second transistor has the second conductivity type, and the second electric current flows through the second transistor. A drain and a gate of the second transistor are connected to the gate of the first transistor, and a source of the second transistor is supplied with the second voltage. The second transistor is configured such that a ratio W/L, a ratio of a gate width W to a gate length L, is smaller than a ratio W/L of the first transistor. The first current output unit is configured to output an output current based on the first electric current or the second electric current. | 09-29-2011 |
20110248755 | CROSS-FEEDBACK PHASE-LOCKED LOOP FOR DISTRIBUTED CLOCKING SYSTEMS - According to various embodiments, a cross-feedback phase-locked loop (XF-PLL) may include a secondary phase/frequency detector to detect the phase/frequency differences between two adjacent domains and feed the phase/frequency differences back into the main feedback loop of the XF-PLL, thereby reducing accumulated jitter and inter-domain clock skew in a distributed clocking system. Other embodiments may be described and claimed. | 10-13-2011 |
20110254601 | LOCK DETECTOR, METHOD APPLICABLE THERETO, AND PHASE LOCK LOOP APPLYING THE SAME - A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses, respectively; first and second delay circuits, delaying the third and the fourth pulses into first and second sampling clocks, respectively; and a cross-sampling circuit, sampling the third pulse based on the second sampling clock and sampling the fourth pulse based on the first sampling clock to indicate whether the PLL is locked. | 10-20-2011 |
20110260763 | FREQUENCY SYNTHESIZER - The present invention discloses a frequency synthesizer which includes: a PLL including an oscillator for generating an oscillator signal and a first frequency divider for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit for switching the PLL to either an open loop status or a closed loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result. | 10-27-2011 |
20110285438 | PLL CIRCUIT FOR REDUCING REFERENCE LEAK AND PHASE NOISE - A phase locked loop circuit comprises a charge pump fed with a phase error output signal; a loop filter charged or discharged with an output of the charge pump; an oscillator, an oscillating frequency of which is controlled by a voltage of the loop filter; and a frequency/phase comparator having a switching function which is fed with a reference signal and an output signal of the oscillator and outputs the phase error output signal; the frequency/phase comparator being configured to, based on a lock detection signal, switch between comparing frequencies by detecting rising edges of the reference signal and the comparison signal to detect a phase difference between the reference signal and the comparison signal, and comparing phases by detecting voltage levels of the reference signal and the comparison signal to detect a phase difference between the reference signal and the comparison signal. | 11-24-2011 |
20110291715 | PHASE ADJUSTMENT CIRCUIT - In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first 1/2 frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter. | 12-01-2011 |
20110291716 | FAST-SWITCHING LOW-NOISE CHARGE PUMP - In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump. | 12-01-2011 |
20110298508 | DATA INTERFACE WITH DELAY LOCKED LOOP FOR HIGH SPEED DIGITAL TO ANALOG CONVERTERS AND ANALOG TO DIGITAL CONVERTERS - A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay. | 12-08-2011 |
20110304365 | FAST PHASE LOCKING SYSTEM FOR AUTOMATICALLY CALIBRATED FRACTIONAL-N PLL - The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal. | 12-15-2011 |
20110304366 | PLL CIRCUIT - A PLL circuit comprises a phase frequency detector configured to output a phase frequency difference signal with a pulse duration according to a phase difference and a frequency difference between a reference clock signal and a feedback clock signal according to an output clock signal; a charge pump circuit configured to output a charge pump current which is an output current according to the phase frequency difference signal and reduce a charge pump current amount in accordance with a charge pump current amount control signal for reducing the charge pump current amount stepwisely; and a lock detecting unit configured to detect whether or not the feedback clock signal is locked to the reference clock signal and output a lock detection signal when detecting a lock of the reference clock signal and the feedback clock signal | 12-15-2011 |
20110304367 | APPARATUS AND METHOD FOR FREQUENCY CALIBRATION IN FREQUENCY SYNTHESIZER - An apparatus and a method for frequency calibration in a frequency synthesizer are disclosed. The present invention includes an up/down processor. The up/down processor is utilized for outputting one of a GND voltage and a VDD voltage to a voltage-controlled oscillator via a loop filter in an open loop status, or outputting one of a step-up voltage and a step-down voltage in accordance with a phase difference to the voltage-controlled oscillator via the loop filter in a close loop status. When the up/down processor outputs one of the GND voltage and the VDD voltage in the open loop status, a memory bank selector compares frequencies for selecting a value of a memory bank and then adds an offset to the value of the memory bank so as to determine a final value of a VCO memory bank in the phase locked loop. | 12-15-2011 |
20110304368 | WIDEBAND PHASE MODULATOR - An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals. | 12-15-2011 |
20110309867 | PHASE LOCKED LOOP - A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal. | 12-22-2011 |
20120007643 | Binary-Weighted Delta-Sigma Fractional-N Frequency Synthesizer With Digital-To-Analog Differentiators Canceling Quantization Noise - A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator. | 01-12-2012 |
20120007644 | COMPARATOR-BASED BUFFER WITH RESISTIVE ERROR CORRECTION - A comparator-based buffer method and system enhance the driving capability of high-gain amplifiers with switched-capacitor loads. It includes a current source, a comparator, switches, sampling capacitor and overshoot correction resistor. A correction solution using a resistor in the charging path and a correction phase reduces the overshoot of the output voltage while constraining power consumption and minimizing components. Spectre® simulations verify the effectiveness of the invention. | 01-12-2012 |
20120019294 | DUAL-LOOP PHASE LOCK LOOP - A dual-loop phase lock loop includes a phase frequency detector, a first charge pump, a second charge pump, a first capacitor, a filter, a first adder, a voltage controlled delay line, and a frequency divider. The phase frequency detector is used for outputting a switch signal according to a reference clock and a divided feedback clock. The first charge pump and the first capacitor are used for generating a coarse control voltage according to the switch signal. The second charge pump, the filter, and the first adder are used for generating a fine control voltage according to the switch signal and the coarse control voltage. The voltage controlled delay line is used for outputting a feedback clock according to the coarse control voltage and the fine control voltage. The frequency divider is used for dividing the feedback clock to output the divided feedback clock. | 01-26-2012 |
20120019295 | CLOCK DISTRIBUTION APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed. | 01-26-2012 |
20120025881 | HIGH FREQUENCY QUADRATURE PLL CIRCUIT AND METHOD - A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit. | 02-02-2012 |
20120025882 | CALIBRATION FOR PHASE-LOCKED LOOP - A method for calibrating a bandwidth of a phase-locked loop begins with detecting an error signal generated by the phase-locked loop in response to a stimulus signal. The difference between the integral of the error signal and a nominal value thereof is computed, and the bandwidth of the phase-locked loop is adjusted based on the computed difference. | 02-02-2012 |
20120038402 | Clock generation circuit and electronic apparatus - Disclosed herein is a clock generation circuit, including a current-controlled oscillation section including a plurality of delay circuits, which include a plurality of current-controlled delay circuits adapted to delay a signal by a delay amount corresponding to current supplied thereto, connected so as to form a closed loop and adapted to output a clock signal formed by the closed loop; a phase controlling section including a comparator adapted to compare the clock signal with a reference signal and adapted to output controlling current, which varies so as to decrease the phase difference between the clock signal and the reference signal, to the current-controlled delay circuits; and a spread current generation section adapted to supply spread spectrum current of a current value different from that of the controlling current in place of the controlling current to a particular one or ones of the current-controlled delay circuits. | 02-16-2012 |
20120056652 | DLL circuit with dynamic phase-chasing function and method thereof - A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor. | 03-08-2012 |
20120062291 | CLOCK DATA RECOVERY CIRCUIT - Multiple flip-flops each latch input data at a time point of the corresponding clock signal. The i-th (i represents an integer) first logical gate generates an internal up signal which is asserted when the output of the (2×i−1)-th flip-flop does not match the output of the (2×i)-th flip-flop. The j-th (j represents an integer) second logical gate generates an internal down signal which is asserted when the output of the (2×j)-th flip-flop does not match the output of the (2×j+1)-th flip-flop. A third logical gate generates an up signal based upon the multiple internal up signals. A fourth logical gate generates a down signal based upon the multiple internal down signals. | 03-15-2012 |
20120062292 | PHASE-LOCKED LOOP CIRCUIT AND RADIO RECEIVER - The voltage-controlled oscillator generates a first signal and a second signal having a phase reverse to that of the first signal, frequencies thereof being controlled depending on control voltages. The sub-sampling phase comparator generates first/second sampled voltages by sampling voltages of the first/second signals in each cycle of the reference signal having cycles. The current generating circuit has first/second charge pumps configured to generate first/second current signal depending on supply voltages, the second current signal having a polarity reverse to that of the first current signal. The selection controller selectively carries out a first supply mode for supplying the first and second sampled voltages to the second and first charge pumps and a second supply mode for supplying the first and second sampled voltages to the first and second charge pumps respectively. The loop filter generates the control voltages supplied to the voltage-controlled oscillator by smoothing the composite current signal. | 03-15-2012 |
20120062293 | INJECTION-LOCKED PHASE-LOCKED LOOP WITH A SELF-ALIGNED INJECTION WINDOW - An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of differential terminals of an injection-locked voltage-controlled oscillator (ILVCO) of the ILPLL. According to the detection, the phase detector generates a control signal, to align an oscillation output, generated from the pair of differential terminals of the ILVCO, with an injection pulse utilized in the ILVCO. | 03-15-2012 |
20120068744 | Phase Locked Loop Circuits - A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selector, a dividing unit, a converter, a low pass filer (LPF), and a modulator. The selector selects one of the internal clock signals to serve as a selection clock signal according to an enable signal. The first dividing unit performs dividing operations to the selection clock signal to generate the output clock signal and a feedback clock signal. The converter detects phase difference between the feedback clock signal and a reference clock signal to generate a detection signal. The LPF performs a filtering operation to the detection signal to generate a filtering signal. The modulator modulates the filtering signal to generate the enable signal. | 03-22-2012 |
20120068745 | INJECTION-LOCKED FREQUENCY DIVIDER - A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is electrically connected to the differential direct injection pair and produces an operating frequency based on the mixed differential injection signals. | 03-22-2012 |
20120068746 | PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT - A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage. | 03-22-2012 |
20120074996 | METHOD AND APPARATUS FOR CORRECTING PHASE OFFSET ERRORS IN A COMMUNICATION DEVICE - A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An auto-tuning circuit and technique provide a measurement of static phase error by integrating the static phase error in the DLL/PLL circuit. A correction value is determined and applied as a current at the charge pump or as a time/phase offset at the phase detector to minimize static phase error. During normal operation the DLL/PLL is operated with the correction value resulting in substantially reduced spur levels and/or improved settling time. | 03-29-2012 |
20120074997 | PHASE-LOCKED LOOP BASED FREQUENCY SYNTHESIZER AND METHOD OF OPERATING THE SAME - A phase-locked loop based frequency synthesizer generates a plurality of output reference signals by phase-delaying an input reference signal and generates a plurality of comparison signals by using a signal having a frequency divided by the fractional frequency divider. Here, the comparison signals are lower than the divided frequency. Further, the phase-locked loop based frequency synthesizer controls an output frequency of a voltage controlled oscillator through phase and frequency comparison between the plurality of output reference signals and the plurality of comparison signals. | 03-29-2012 |
20120074998 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR COMPENSATING FREQUENCY DRIFT OF A CONTROLLABLE OSCILLATOR - An integrated circuit device for compensating frequency drift of a controllable oscillator is described. The integrated circuit device includes at least one compensation module including: an input for receiving at least an indication of a frequency control signal (vci) from at least one frequency control module; and an output for providing at least one compensation signal (vct) to the controllable oscillator. The at least one compensation module is arranged to compare the at least indication of the frequency control signal (vci) with a reference voltage signal (vref); and generate the at least one compensation signal (vct) based at least partly on the comparison of the indication of the frequency control signal (vci) to the reference voltage signal (vref). | 03-29-2012 |
20120092050 | OSCILLATOR CIRCUIT AND METHOD FOR GAIN AND PHASE NOISE CONTROL - An oscillator circuit and method for gain and phase noise control. A gain and phase noise controlled oscillator circuit includes a variable electronic oscillator and a tuning loop circuit. In operation, the variable electronic oscillator generates a clock signal and has a clock signal frequency that is controlled by a sense voltage received by the variable electronic oscillator or by one or more capacitive loads coupled to the variable electronic oscillator. Further, the tuning loop circuit is coupled to the variable electronic oscillator and compares the sense voltage to a control voltage received by the tuning loop circuit and produces one or more correction signals based on the comparison, where the one or more capacitive loads change capacitance based on the one or more correction signals. | 04-19-2012 |
20120098579 | CHARGE-BASED PHASE LOCKED LOOP CHARGE PUMP - Charge-based charge pumps are described which include a switchable capacitor configured for connection to a voltage source, a ground, and a charge pump output. A first pair of switches include a first switch configured to connect the switchable capacitor to ground and a second switch configured to connect the switchable capacitor to the voltage source. A second pair of switches include a third switch configured to connect a first node, between the switchable capacitor and ground, to the charge pump output, and a fourth switch configured to connect a second node, between the switchable capacitor and the voltage source, to the charge pump output. Locked loop designs, such as phase locked loops or delay locked loops, are described that include charge-based charge pumps. | 04-26-2012 |
20120098580 | TIMING ADJUSTING CIRCUIT - A timing adjusting circuit including a time amplifier and a phase adjusting module is provided. The time amplifier is used for increasing the active pulse-width of a phase control signal, so as to generate an adjusted control signal. Based on the adjusted control signal, the phase adjusting module adjusts the phase of an output signal. The phase of the output signal is associated with the active pulse-width of the phase control signal. | 04-26-2012 |
20120098581 | CHARGE PUMP FOR PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 04-26-2012 |
20120112809 | METHOD AND DIGITAL CIRCUIT FOR GENERATING A WAVEFORM FROM STORED DIGITAL VALUES - In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path. | 05-10-2012 |
20120126866 | Phase-Locked Loop with Calibration Function and Associated Calibration Method - A phase-locked loop (PLL) includes a charge pump, a frequency divider, a voltage detector, a control module, and a calibration module. When a predetermined current amount and a predetermined frequency dividing amount are provided, the voltage detector measures a voltage associated with an output frequency of the PLL to generate a first reference voltage. When a test current amount and the predetermined frequency dividing amount are provided, the voltage detector again measures the voltage to generate a second reference voltage. When the predetermined current amount and a test frequency dividing amount are provided, the voltage detector again measures the voltage to generate a third reference voltage. The control module estimates a loop gain of the PLL according to the current amounts, the frequency dividing amounts and the reference voltages. The calibration module calibrates the PLL according to the loop gain. | 05-24-2012 |
20120126867 | SIGNAL PATTERN AND DISPERSION TOLERANT STATISTICAL REFERENCE OSCILLATOR - Disclosed is a statistical reference oscillator that includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divides the frequency of an output signal at a second frequency division ratio and outputs a feedback signal; a frequency detector which outputs a difference signal based on a difference between the reference signal and the feedback signal; and an output signal generator which outputs the output signal based on the difference signal. | 05-24-2012 |
20120133404 | CHARGE PUMP, PHASE FREQUENCY DETECTOR AND CHARGE PUMP METHODS - A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state. | 05-31-2012 |
20120146692 | DIFFERENTIAL CONTROLLED PHASE LOCKED LOOP CIRCUIT - Provided is a PLL circuit driven with a differential controlled voltage. The PLL circuit includes a VCO. The VCO outputs an oscillation signal in response to a difference between first and second control voltages. The PLL circuit includes a first loop for generating the first control voltage, and a second loop for generating the second control voltage having a phase opposite to the first control voltage. Intermediate generated signals of the first loop and intermediate generated signals of the second loop which respectively correspond to the intermediate generated signals of the first loop have opposed phases. | 06-14-2012 |
20120153999 | CLOCK SIGNAL GENERATION CIRCUIT - A clock signal generation circuit includes a clock inversion unit inverting a reference clock signal and an internal clock signal to generate an inverted reference clock signal and an inverted internal clock signal, a first clock detection unit comparing the reference clock signal with the internal clock signal to output a first detection signal, a second clock detection unit comparing the inverted reference clock signal with the inverted internal clock signal to output a second detection signal, first and second charge pump units generating charge current or discharge current in response to the first second detection signals, respectively, a loop filter unit producing a control voltage signal having a voltage level corresponding to the charge currents or discharge currents, and an internal clock signal output unit producing the internal clock signal according to the control voltage signal. | 06-21-2012 |
20120154000 | PLL CIRCUIT - A PLL circuit, has a phase comparator for comparing phases of a reference clock and a feedback clock, and outputting a phase comparison signal indicating the phase difference; a charge pump circuit, which, during a time period corresponding to the phase difference, outputs a first charge pump current and a second charge pump current; a loop filter, having a capacitor storing electric charge based on the first and second charge pump currents, which generates a control voltage due to stored electric charge; an oscillator generating an output clock at a frequency according to the control voltage; a frequency divider frequency-dividing the output clock and outputs the feedback clock; and a charge pump adjustment circuit, which, when in a locked state, adjusts current quantity of the first or the second charge pump current such that the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal. | 06-21-2012 |
20120161835 | CONTROLLING A FREQUENCY LOCKED LOOP - An apparatus includes a frequency locked loop and a controller. The controller stores a state of the frequency locked loop at which an output signal of the frequency locked loop is locked onto a reference signal and subsequently initializes the frequency locked loop with the stored state to cause the frequency locked loop to relock the output signal to the reference signal. | 06-28-2012 |
20120161836 | CHARGE PUMP DEVICE AND METHOD FOR REGULATING THE SAME - A charge pump device is provided. The charge pump device includes a clamping unit providing a first pulse and a second pulse having a phase identical to that of the first pulse, wherein each of the first and the second pulses has an amplitude; a charge pump unit outputting a first voltage in response to the first pulse and the second pulse; and a feedback unit outputting a second voltage in response to the first voltage, wherein the clamping unit adjusts the amplitude of one of the first pulse and the second pulse in response to the second voltage to regulate the first voltage. | 06-28-2012 |
20120176171 | LOOP FILTER BUFFER WITH LEVEL SHIFTER - A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter. | 07-12-2012 |
20120187989 | PHASE-LOCKED LOOP HAVING HIGH-GAIN MODE PHASE-FREQUENCY DETECTOR - A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode. | 07-26-2012 |
20120187990 | CLOCK DATA RESTORATION DEVICE - A clock data restoration device ( | 07-26-2012 |
20120194237 | DELAY LOCK LOOP AND METHOD FOR GENERATING CLOCK SIGNAL - A delay lock loop (DLL) including a voltage control delay line (VCDL), a phase frequency detecting loop (PFD loop), and a phase limiting loop is provided. The VCDL generates an output clock signal according to a DC voltage signal, wherein the VCDL delays an input clock signal by a specific period so as to generate the output clock signal. The PFD loop generates the DC voltage signal according to the phase difference of the input clock signal and the output clock signal and is controlled by an initiation signal. The phase limiting loop limits the delay of the output clock signal to be less than a delay time and generates the initiation signal to enable the PFD loop. Furthermore, a clock signal generating method is also provided. | 08-02-2012 |
20120194238 | Delay-Locked Loop with Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. A charge pump system is coupled with the phase detector, including (1) a charge pump responsive to assertion of actuating signals from the UP output and the DOWN output to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust a bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output. | 08-02-2012 |
20120200327 | CHARGE PUMP AND ACTIVE FILTER FOR A FEEDBACK CIRCUIT - A circuit containing a pair of charge pumps and an active filter receives outputs of a phase frequency detector used in a phase locked loop. The charge pump is implemented using switches and resistors to reduce performance variations due to component mismatches. The loop filter includes a resistor and a capacitor coupled in series, the resistor and the capacitor determining a zero of the transfer function of the loop filter. The charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node formed by a junction of the resistor and the capacitor. The polarity of the first current pulse is the opposite of the polarity of the second current pulse. Multiplication of the capacitance of the capacitor is thereby achieved, enabling implementation of the loop filter in integrated circuit form. | 08-09-2012 |
20120200328 | Reference Clock Compensation for Fractional-N Phase Lock Loops (PLLs) - In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity. | 08-09-2012 |
20120212267 | Circuit for Clamping Current in a Charge Pump - A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump. | 08-23-2012 |
20120223752 | PHASE LOCKED LOOP WITH CHARGE PUMP - A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal. | 09-06-2012 |
20120223753 | DIGITAL DELAY LINES - In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage. | 09-06-2012 |
20120235718 | ADAPTIVE BANDWIDTH PHASE-LOCKED LOOP - A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current converter converts a control voltage to a first current. A current-controlled oscillator generates the oscillator signal based on the first current. A dual charge pump circuit generates first and second charge pump currents having a predetermined ratio, based on a second current generated by a current mirror circuit and an error (feedback) signal. An active loop filter generates the control voltage based on the first and second charge pump currents. The active loop filter includes an input capacitance that varies with a variation in the predetermined ratio of the charge pump currents. The active loop filter also includes a transconductance stage having a transconductance that varies based on a third current generated by a current mirror circuit. The PLL bandwidth is independent of PVT variations and dependent only on the frequency of the input reference signal. In addition, the size of the input capacitor is relatively small so that the circuit requires very little space. | 09-20-2012 |
20120235719 | DEVICE OF PHASE LOCKED-LOOP AND THE METHOD USING THE SAME - Nowadays, electronic product designs are aimed at saving, due to the trend to reduce energy consumption and carbon output. Ethernet technology has also been aimed specifically at saving energy; IEEE P802.3az standard (Energy Efficient Ethernet, EEE), for Ethernet released by Broadcom is one example. The disclosure turns off the phase-locked loop when the network communication stops, effectively saving the energy consumption of the network chip under the EEE standard. In the case of network reconnection, the disclosure turns on the phase-locked loop to start the network communication through adjusting the current of current source and the parameters of a low pass filter to increase the charging speed for the reference voltage generation of the low pass filter. The disclosure then shortens the start-up time to quickly output the standard output frequency and phase of the phase-locked loop. | 09-20-2012 |
20120242384 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN ON-CHIP PLL AND OPERATING METHOD THEREOF - An on-chip phase-locked loop circuit has reduced power consumption in a semiconductor integrated circuit. The phase locked loop circuit is equipped with a phase frequency comparator, a loop attenuator, a charge pump, a loop filter, a voltage controlled oscillator and a divider. The attenuator includes a sampling circuit and a counter. A sampling pulse and first and second output signals both outputted from the phase frequency comparator are supplied to the sampling circuit. The sampling circuit outputs a sampling output signal. When the counter completes a countup of a predetermined number of sampling pulses outputted from the sampling circuit, the counter outputs a countup completion output signal. The charge pump outputs a charging current or a discharging current to the loop filter in response to the countup completion output signal. | 09-27-2012 |
20120249198 | DUAL LOOP PHASE LOCKED LOOP WITH LOW VOLTAGE-CONTROLLED OSCILLATOR GAIN - A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply. | 10-04-2012 |
20120268178 | Fully differential adaptive bandwidth PLL with differential supply regulation - Provided is a fully differential adaptive bandwidth phase locked loop with differential supply regulation. One fully differential phase locked loop includes a differential active loop filter and regulator coupled to an output of a differential charge pump, a differential voltage-controlled oscillator coupled to differential control voltages developed by the differential active loop filter and regulator, and a bias circuit coupled to the differential control voltages and providing a bias current to the differential charge pump. | 10-25-2012 |
20120268179 | VOLTAGE GENERATOR AND METHOD OF GENERATING VOLTAGE - A voltage generator includes a clock generator configured to generate a first clock signal and a second clock signal having a longer cycle than the first clock signal, a pumping unit configured to generate a pumping voltage in response to the first or second clock signal, a first detection circuit configured to detect the pumping voltage and generate a first control signal for controlling the operation of the pumping unit based on the result of the detection, and a second detection circuit configured to generate a second control signal for outputting the first or second clock signal generated from the clock generator depending on whether the first control signal maintains an enable state for a specific time. | 10-25-2012 |
20120274372 | Phase Locked Loop Frequency Synthesizer Circuit with Improved Noise Performance - A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector UP signals (UP/DN) dependent on the sign of the phase difference; and a charge pump ( | 11-01-2012 |
20120280730 | APPARATUS AND METHODS FOR ADJUSTING VOLTAGE CONTROLLED OSCILLATOR GAIN - Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations. | 11-08-2012 |
20120280731 | PHASE-LOCKED-LOOP CIRCUIT INCLUDING DIGITALLY-CONTROLLED OSCILLATOR - A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal. | 11-08-2012 |
20120293223 | PHASE LOCKED LOOP AND SEMICONDUCTOR DEVICE USING THE SAME - It is an object of the present invention to provide a phase locked loop in which a voltage signal input to a voltage controlled oscillator after a return from a stand-by state becomes constant in a short time and power consumption is reduced. A transistor including a semiconductor layer formed using an oxide semiconductor material is provided between an input terminal of a voltage controlled oscillator and a capacitor of a loop filter. The transistor is turned on in a normal operation state and turned off in a stand-by state. | 11-22-2012 |
20120313679 | PUMP CIRCUIT AND METHOD FOR PUMPING VOLTAGE IN SEMICONDUCTOR APPARATUS - A pump circuit includes a first clock generation unit, a second clock generation unit and a pumping stage unit. The first clock generation unit is configured to generate a first clock with a first amplitude by using an input clock and an external voltage. The second clock generation unit is configured to generate a second clock with a second amplitude larger than the first amplitude by using the input clock and an amplified voltage generated by amplifying the external voltage. The pumping stage unit is configured to increase an input voltage using the first clock and the second clock and generate amplified output voltages. | 12-13-2012 |
20120313680 | POWER DETECTION CIRCUIT AND POWER DETECTION METHOD - A power detection circuit according to the present invention includes a variable frequency oscillator | 12-13-2012 |
20130002319 | Frequency Divider and Phase Locked Loop Including the Same - A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode. | 01-03-2013 |
20130027101 | PHASE LOCKED LOOP - A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages. | 01-31-2013 |
20130038365 | Sampling Phase Lock Loop (PLL) With Low Power Clock Buffer - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time. | 02-14-2013 |
20130049830 | DELAY LOCK LOOP CIRCUIT - The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals. | 02-28-2013 |
20130057328 | PHASE DETECTOR CIRCUIT FOR AUTOMATICALLY DETECTING 270 AND 540 DEGREE PHASE SHIFTS - Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal. | 03-07-2013 |
20130063192 | PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION - A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter. | 03-14-2013 |
20130063193 | CALIBRATION DEVICE AND RELATED METHOD FOR PHASE DIFFERENCE BETWEEN DATA AND CLOCK - A calibration device and related method for a phase difference between data signal and clock signal are disclosed. An apparatus of the invention includes: an adjustable delay circuit for delaying at least one of a first input signal and a second input signal according to a delay control signal, and generating a first signal and a second signal; a phase detection circuit for detecting a phase difference between the first signal and the second signal to output a phase difference signal; a charge pump and a capacitor for outputting a control signal according to the phase difference signal; a comparison circuit for outputting a comparison result according to the control signal; and, a digital control circuit for outputting the delay control signal according to the comparison result. | 03-14-2013 |
20130069700 | CIRCUIT AND METHOD FOR CONTROLLING MIXED MODE CONROLLED OSCILLATOR AND CDR CIRCUIT USING THE SAME - A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal. | 03-21-2013 |
20130076414 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN ON-CHIP PLL AND OPERATING METHOD THEREOF - An on-chip phase-locked loop circuit has reduced power consumption in a semiconductor integrated circuit. The phase locked loop circuit is equipped with a phase frequency comparator, a loop attenuator, a charge pump, a loop filter, a voltage controlled oscillator and a divider. The attenuator includes a sampling circuit and a counter. A sampling pulse and first and second output signals both outputted from the phase frequency comparator are supplied to the sampling circuit. The sampling circuit outputs a sampling output signal. When the counter completes a countup of a predetermined number of sampling pulses outputted from the sampling circuit, the counter outputs a countup completion output signal. The charge pump outputs a charging current or a discharging current to the loop filter in response to the countup completion output signal. | 03-28-2013 |
20130082754 | PHASE LOCKED LOOP CALIBRATION - An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range. | 04-04-2013 |
20130093481 | HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO - A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal. | 04-18-2013 |
20130093482 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES - An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. | 04-18-2013 |
20130093483 | Dual Phase Detector Phase-Locked Loop - A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal. | 04-18-2013 |
20130113535 | Apparatus and Method for Fast Phase Locked Loop (PLL) Settling for Cellular Time-Division Duplex (TDD) Communications Systems - A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation. | 05-09-2013 |
20130120040 | SYSTEM AND METHOD OF STABILIZING CHARGE PUMP NODE VOLTAGE LEVELS - A method includes tracking a tuning voltage at a first circuit coupled to a first drain node of a first supply of a charge pump. The method also includes tracking the tuning voltage at a second circuit coupled to a second drain node of a second supply of the charge pump. The method further includes stabilizing a first voltage of the first drain node and a second voltage of the second drain node responsive to the tuning voltage. | 05-16-2013 |
20130120041 | Leakage Tolerant Delay Locked Loop Circuit Device - Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals. | 05-16-2013 |
20130127505 | CLOCK GENERATOR, SEMICONDUCTOR DEVICE, AND CLOCK GENERATING METHOD - There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop. | 05-23-2013 |
20130135018 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits. | 05-30-2013 |
20130141145 | CLOCK AND DATA RECOVERY CIRCUIT - The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal. | 06-06-2013 |
20130141146 | PLL CIRCUIT, CALIBRATION METHOD AND WIRELESS COMMUNICATION TERMINAL - An ILFD controller sets a control parameter on the basis of a frequency of a frequency-divided signal and a frequency of a reference signal measured by a clock counter. A VCO controller selects an oscillation band that defines an oscillation frequency of a VCO and also selects an oscillation band of the VCO on the basis of the frequency of the reference signal and a frequency of a frequency-divided signal that is a result obtained by frequency-dividing an output signal, which is delivered from the VCO in response to the selected oscillation band, by means of an ILFD and a frequency divider. | 06-06-2013 |
20130147530 | HIGH FREQUENCY QUADRATURE PLL CIRCUIT AND METHOD - A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit. | 06-13-2013 |
20130154695 | PHASE LOCK LOOP WITH ADAPTIVE LOOP BANDWIDTH - Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors. | 06-20-2013 |
20130154696 | CHARGE PUMP CIRCUIT AND PHASE LOCK LOOP CIRCUIT - A charge pump circuit is provided. The charge pump circuit includes a current driving unit, a current draining unit, a switch, and a voltage splitting circuit. The current driving circuit receives a first control signal to transmit a driving current to the first end or the second end according to the first control signal. The current draining unit receives a second control signal to drain a draining current from the first end or the second end according to the second control signal. The switch is coupled between the first end and the second end, and the switch is turned on or turned off according to a power down control signal. The voltage splitting circuit receives a reference power voltage, and is coupled to the first end. The voltage splitting circuit provides a splitting power to the first end by splitting the voltage of the reference power voltage. | 06-20-2013 |
20130154697 | PLL CIRCUIT - A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator. | 06-20-2013 |
20130154698 | DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 06-20-2013 |
20130154699 | REFERENCE FREQUENCY GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE - An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock. | 06-20-2013 |
20130154700 | Delay-Locked Loop with Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output. | 06-20-2013 |
20130154701 | CHARGE PUMP, PHASE FREQUENCY DETECTOR AND CHARGE PUMP METHODS - A phase/frequency detector for control signal to controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase. | 06-20-2013 |
20130169329 | METHOD FOR LOCKING A DELAY LOCKED LOOP - A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference. | 07-04-2013 |
20130181756 | CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP - A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop. | 07-18-2013 |
20130187689 | PHASE-LOCKED LOOP WITH TWO NEGATIVE FEEDBACK LOOPS - A phase-locked loop with two negative feedback loops including: a phase frequency detector which includes phase difference between the input clock and the feedback clock in a frequency-phase-locked loop and outputting up or down signals based on the phase difference; a charge pump outputting the current proportional to the up and down signals outputted from the phase frequency detector; a loop filter outputting the voltage by filtering the current outputted from the charge pump; a voltage controlled oscillator outputting the frequency based on the voltage outputted from the loop filter; a divider dividing the frequency outputted from the voltage controlled oscillator and feedbacking to the phase frequency detector; a frequency-voltage converter generating the voltage corresponding to the frequency outputted from the voltage controlled oscillator, and suppressing noise of the voltage controlled oscillator by feedbacking the generated voltage to the voltage controlled oscillator. | 07-25-2013 |
20130187690 | CAPACITIVE MULTIPLICATION IN A PHASE LOCKED LOOP - A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a phase and frequency detector. The frequency synthesizer circuit also includes a first charge pump and a second charge pump, each coupled to the phase and frequency detector. The frequency synthesizer circuit also includes a loop filter that includes a resistor and at least two capacitors. The second charge pump is coupled between the resistor and a capacitor that creates a zero in a transfer function of the loop filter. The frequency synthesizer circuit also includes a voltage controlled oscillator that produces an output frequency based on an output of the loop filter. | 07-25-2013 |
20130187691 | LOOP FILTER FOR CURRENT-CONTROLLED-OSCILLATOR-BASED PHASE LOCKED LOOP - A loop filter of a phase-locked loop (PLL) that uses a current-controlled oscillator (CCO) includes a capacitor, a voltage-to-current (V-to-I) converter, and a charge pump. The input node of the loop filter receives a first current from an external charge pump. The combination of the capacitor and the V-to-I converter generates a first component of the output current of the loop filter based on the first current. The charge pump of the loop filter generates a second component of the output current. The loop filter is implemented without the need for a zero-frequency-determining resistor, the resistor instead being realized by the product of the first current, the second component of the output current and the transconductance of the V-to-I converter. Phase noise reduction in the PLL, as well as implementation of the loop filter with a smaller area, are thus made possible. | 07-25-2013 |
20130187692 | TRANSITION TIME LOCK LOOP WITH REFERENCE ON REQUEST - Output driver feedback circuitry limits output slew rates across a wide range of output loads. A transition time lock loop architecture of the feedback circuitry compares a transition time pulse with a reference pulse to adjusts transition time of an output signal for various process-voltage-temperature (PVT) process corners, output voltage domains and output capacitances. Reference pulse generation circuitry provides a reference pulse in phase with the transition time pulse for each rise and fall of the output signal. | 07-25-2013 |
20130194012 | PHASE-LOCKED LOOP SYSTEM - A phase-locked loop system is provided. The system includes a charge pump, a voltage-controlled oscillator (VCO) and a bias converter. The charge pump outputs a control voltage according to a phase frequency detection signal, and generates an output current according to a bias signal. The VCO generates an output signal according to the control voltage. The bias converter is coupled between the VCO and the charge pump and for generating the bias signal according to the control voltage. | 08-01-2013 |
20130200932 | Delay Lock Loop Circuit and Method - A delay lock loop circuit includes a voltage controlled delay line for generating a plurality of specific phase differential signals and a feedback signal according to an input clock source and a control voltage, a detector for comparing at least one of phases and frequencies of the input clock source and the feedback signal to generate at least one detection signal, a charge pump for generating the control voltage according to the at least one detection signal, and a phase selection buffer for generating the output clock source according to the plurality of specific phase differential signals, wherein each of the plurality of specific phase differential signals includes at least a non-inversion signal and an inversion signal, and the feedback signal is the inversion signal of one of the plurality of specific phase differential signals. | 08-08-2013 |
20130207700 | Electrical Circuit Having a Controllable Oscillator - An electrical circuit including a controllable oscillator, a transmission line and a control loop. The controllable oscillator is configured to generate an oscillating signal. The transmission line is connected to an output of the oscillator, wherein the transmission line has a length which is a fraction of a wavelength of the oscillating signal. The control loop is configured to detect a difference between a first value of a signal parameter of the oscillating signal and a second value of the signal parameter of the oscillating signal having passed the transmission line. Furthermore, the control loop is configured to control the controllable oscillator in accordance with the difference. | 08-15-2013 |
20130214835 | LOCK DETENTION CIRCUIT, DLL CIRCUIT, AND RECEIVING CIRCUIT - According to one embodiment, a lock detection circuit includes an initial state response circuit. The initial state response circuit is configured to output a third control signal to delay lines and cause a charge pump to stop an output of a second control signal when a pulse width modulation signal is not input, the third control signal is configured to control a delay amount to cause a delay amount of an entire delay circuit to be within one selected from a range in which an OVER signal generation circuit is operable, a range in which an UNDER signal generation circuit is operable, and a range that is greater than an UNDER threshold and less than an OVER threshold. | 08-22-2013 |
20130214836 | FREQUENCY SYNTHESIZER - A phase difference detecting circuit | 08-22-2013 |
20130222024 | FREQUENCY GENERATING SYSTEM - A frequency generating system including a phase-locked loop (PLL) and a control signal generation unit is provided. The PLL outputs a phase-locked clock and controls a voltage-controlled oscillator (VCO) therein by using a dual-path architecture. The VCO includes a varactor. The control signal generation unit is coupled to the PLL and disposed in one of the dual paths. The control signal generation unit provides an up voltage, a down voltage, or a middle voltage as a control signal to control the VCO according to an up signal and a down signal of the PLL. The control signal generation unit provides the middle voltage in response to an electrical characteristic of the varactor to compensate the control signal. | 08-29-2013 |
20130222025 | PHASE LOCKED LOOP - A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal. | 08-29-2013 |
20130229213 | CAPACITOR LEAKAGE COMPENSATION FOR PLL LOOP FILTER CAPACITOR - An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump controls the output portion such that the magnitudes of the positive and negative current pulses are the same. Within the current control portion there is a “Charge Pump Output Voltage Replica Node” (CPOVRN). The voltage on this CPOVRN is maintained to be the same as a voltage on the charge pump output node. A capacitor leakage compensation circuit indirectly senses the voltage across a leaking capacitor of the loop filter by sensing the voltage on the CPOVRN. The compensation circuit imposes the sensed voltage across a replica capacitor, mirrors a current leaking through the replica, and supplies the mirrored current in the form of a compensation current to the leaking capacitor. | 09-05-2013 |
20130241612 | APPARATUS AND METHODS FOR ADJUSTING PHASE-LOCKED LOOP GAIN - Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations. | 09-19-2013 |
20130257496 | Frequency Synthesizer - The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter. | 10-03-2013 |
20130271191 | PLL CIRCUIT - A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal. | 10-17-2013 |
20130271192 | WIDE FREQUENCY RANGE DELAY LOCKED LOOP - A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power. | 10-17-2013 |
20130285721 | TIMING MONITOR FOR PLL - Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device. | 10-31-2013 |
20130285722 | PHASE LOCKED LOOP WITH A FREQUENCY MULTIPLIER AND METHOD OF CONFIGURING THE PHASE LOCKED LOOP - A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL. | 10-31-2013 |
20130285723 | PHASE LOCKED LOOP CIRCUIT - A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage. | 10-31-2013 |
20130300469 | INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL) - An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone. | 11-14-2013 |
20130300470 | Low Jitter Clock Generator for Multiple Lanes High Speed Data Transmitter - The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input. | 11-14-2013 |
20130300471 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO. | 11-14-2013 |
20130342247 | CAPACTIVE LOAD PLL WITH CALIBRATION LOOP - A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage. | 12-26-2013 |
20140002152 | CHARGE PUMP CIRCUIT | 01-02-2014 |
20140015577 | PHASE LOCKED LOOP CIRCUIT WITH REDUCED JITTER - A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF. | 01-16-2014 |
20140015578 | APPARATUS AND METHOD FOR PERFORMING SPREAD-SPECTRUM CLOCK CONTROL - A terminal includes control logic to control a phase-locked loop to output a spread-spectrum clocking signal. The control logic controls the generation of the spread-spectrum clocking signal by adjusting at least one parameter of the phase-locked loop. The parameter may be a charge pump setting or a loop-filter capacitance of the phase-locked loop, or their digital equivalents. Adjustment of the parameter reduces a predetermined portion of a communications spectrum. The predetermined portion may be located within a range of frequencies allocated to a specific channel, and reduction of the spectrum in this range may serve to reduce noise associated with clocking harmonics. | 01-16-2014 |
20140021988 | LOOP FILTER WITH NOISE CANCELLATION - A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal. | 01-23-2014 |
20140021989 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter. | 01-23-2014 |
20140049302 | PHASE-LOCKED LOOP AND METHOD FOR CLOCK DELAY ADJUSTMENT - A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. | 02-20-2014 |
20140049303 | FREQUENCY GENERATING SYSTEM, VOLTAGE-CONTROLLED OSCILLATOR MODULE AND METHOD FOR ADJUSTING SIGNAL FREQUENCY - A voltage controlled oscillator module including a VCO unit and a gain adjustment unit is provided. The VCO unit is configured to generate a frequency signal based on a control voltage. The gain adjustment unit is coupled to the VCO unit and configured to receive a first adjustment voltage, a second adjustment voltage, and a reference voltage and accordingly adjusts the control voltage to adjust a frequency value of the frequency signal. The gain adjustment unit includes an adjustment circuit unit and a reference circuit unit. A first voltage-frequency curve of the frequency value of the frequency signal and a voltage value of the first adjustment voltage changes in response to a structure characteristic of the adjustment circuit unit. Furthermore, a frequency generating system and a method for adjusting a signal frequency of the VCO module are provided. | 02-20-2014 |
20140049304 | DOUBLE OUTPUT LINEARIZED LOW-NOISE CHARGE PUMP WITH LOOP FILTER AREA REDUCTION - According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α*I and the second current has a magnitude of β*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α−β)*I. | 02-20-2014 |
20140062550 | PHASE LOCKED LOOP - A phase locked loop comprises a loop filter and a charge pump circuit. The loop filter comprises a parallel capacitor, a serial resistor and a serial capacitor. A first terminal of the serial resistor is electrically connected to a first terminal of the parallel capacitor. A first terminal of the serial capacitor is electrically connected to the second terminal of the serial resistor, and a second terminal of the serial capacitor is electrically connected to a second terminal of the parallel capacitor. The charge pump circuit comprises a first charge pump and a second charge pump. The first charge pump is electrically connected to the first terminal of the serial resistor, and the second charge pump is electrically connected to the second terminal of the serial resistor. The phase lock loop can reduce output jitter and therefore increases the performance of the phase lock loop. | 03-06-2014 |
20140084976 | Delay-Locked Loop with Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output. | 03-27-2014 |
20140091843 | PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS - A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit. | 04-03-2014 |
20140103975 | CHARGING/DISCHARGING CIRCUIT AND PLL CIRCUIT USING THE SAME - A charging/discharging circuit includes a connection terminal, a reference current providing module, an up current module and a down current module. The down current module includes: a first switch module, having a first control terminal, for receiving the down signal to determine whether the first switch module is turned on; a first bias transistor, having a first terminal coupled to the connection terminal, a second terminal coupled to the first switch module, and a control terminal coupled to the reference current providing module; and a first capacitor simulation transistor, having a first terminal and a second terminal coupled to the control terminal of the first switch module, and a control terminal coupled to the control terminal of the first bias transistor. | 04-17-2014 |
20140118039 | CHARGE PUMP CIRCUITS HAVING FREQUENCY SYNCHRONIZATION WITH SWITCHING FREQUENCY OF POWER CONVERTERS - A control circuit of a power converter is provided. The control circuit includes a switching circuit and a charge pump circuit. The switching circuit generates a switching signal for controlling the power converter. The charge pump circuit includes an oscillator for generating an oscillation signal synchronized with the switching signal. The oscillation signal is coupled to control a switch of the charge pump circuit for generating a voltage source. | 05-01-2014 |
20140118040 | SYNCHRONIZING CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME - A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage. | 05-01-2014 |
20140145768 | CORRECTING FOR OFFSET-ERRORS IN A PLL/DLL - The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for. | 05-29-2014 |
20140191787 | PHASE LOCKED LOOP CIRCUIT - A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal. | 07-10-2014 |
20140203853 | PHASE FREQUENCY DETECTOR AND CHARGE PUMP FOR PHASE LOCK LOOP FAST-LOCKING - The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques. | 07-24-2014 |
20140210529 | Phase Locked Loop and Method for Operating the Same - The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response. | 07-31-2014 |
20140210530 | CLOCK RECOVERY CIRCUIT AND CLOCK AND DATA RECOVERY CIRCUIT - A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock. | 07-31-2014 |
20140218082 | DIGITALLY SWITCHED CAPACITOR LOOP FILTER - A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output. | 08-07-2014 |
20140218083 | DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 08-07-2014 |
20140266343 | AREA-EFFICIENT PLL WITH A LOW-NOISE LOW-POWER LOOP FILTER - Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter. | 09-18-2014 |
20140266344 | VARAINDUCTOR, VOLTAGE CONTROLLED OSCILLATOR INCLUDING THE VARAINDUCTOR, AND PHASE LOCKED LOOP INCLUDING THE VARAINDUCTOR - A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane. | 09-18-2014 |
20140292387 | LOCK DETECTOR BASED ON CHARGE PUMP - A phase lock loop having a lock detector is provided. The lock detector is based on a replica charge pump and includes: a charge pump, a filter and a comparing circuit. The charge pump is arranged for providing an output according to a phase difference between an output signal and a reference signal. The filter is coupled to the charge pump, and is arranged for filtering the output of the charge pump to generate a filtered output voltage. The comparing circuit is coupled to the filter, and is arranged for comparing the filtered output voltage with a threshold setting to generate a lock indication signal to indicate whether the output signal is locked to the reference signal. | 10-02-2014 |
20140292388 | PHASE LOCKED LOOP CIRCUIT - The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input. | 10-02-2014 |
20140306741 | Phase-Locked Loop System and Operation - A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block. | 10-16-2014 |
20140312944 | CHARGE PUMP PHASE-LOCKED LOOP CIRCUITS - A charge pump phase-locked loop circuit includes an active loop filter, an adjustable reference voltage source, and a charge pump. The active loop filter includes an amplifier that has a negative input node, a positive input node, and an output node. The adjustable reference voltage source is coupled to the positive input node to provide an adjustable reference voltage. The charge pump is coupled to the negative input node to provide a current to or draw a current from the active loop filter in response to a signal from a phase detector. The charge pump includes a first current source coupled to a first voltage and a second current source electrically coupled to a second voltage, the second current source including a resistor. The second current source is configured such that a current provided by the second current source depends on a resistance value of the resistor and a difference between the reference voltage and the second voltage. | 10-23-2014 |
20140312945 | Delay Locked Loop - A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals. | 10-23-2014 |
20140320183 | PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING USING CHARGE PUMP CURRENT MODULATION - A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected. | 10-30-2014 |
20140320184 | PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING - A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range. | 10-30-2014 |
20140320185 | PLL CIRCUIT - A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator. | 10-30-2014 |
20140327478 | WIDEBAND FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD THEREOF - A wideband frequency synthesizer and a frequency synthesizing method thereof are provided. The wideband frequency synthesizer includes a phase-locked loop unit, a first voltage-controlled oscillating unit and a first frequency mixer unit. The phase-locked loop unit receives a reference signal and a feedback signal and generates a first oscillating signal according to the reference signal and the feedback signal. The first voltage-controlled oscillating unit generates a second oscillating signal. The first frequency mixer is coupled to the phase-locked loop unit and the first voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal for mixing frequencies of the first oscillating signal and the second oscillating signal to generate an output signal and taking the output signal as the feedback signal for outputting to the phase-locked loop unit. | 11-06-2014 |
20140333354 | CHARGE PUMP, A PHASE LOCKED LOOP CIRCUIT AND A CHARGE PUMP METHOD - The invention discloses a charge pump, a phase locked loop circuit and a charge pump method. The charge pump comprises an input port, a switch and an output port. The input port receives a phase frequency adjustment parameter. The switch switches a first current on or off, according to the phase frequency adjustment parameter, and keeps a second current on. The first current is larger than the second current. The output port outputs a sum of the first current and the second current to a low pass filter. | 11-13-2014 |
20140333355 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL. | 11-13-2014 |
20140340132 | METHOD AND APPARATUS FOR GENERATING A REFERENCE SIGNAL FOR A FRACTIONAL-N FREQUENCY SYNTHESIZER - A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal. | 11-20-2014 |
20140340133 | RADIATION HARDENED CIRCUIT - A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal. | 11-20-2014 |
20140347106 | DELAY-LOCKED LOOP (DLL) OPERATION MODE CONTROLLER CIRCUIT AND METHOD FOR CONTROLLING THEREOF - A delay-locked loop (DLL) operation mode control circuit and corresponding method are provided in which one of the output values from a display driver IC (DDI) is detected to switch a DLL block to standby mode. In examples, a CLKP/N frequency and CLKP/N common terminal voltage status are used to switch mode. Accordingly, since inoperable frequency domains otherwise present in a normal mode interval of the DLL block is included into standby mode, more stable operation of the DLL circuit is provided. | 11-27-2014 |
20140354335 | Digital Phase Locked Loop with Hybrid Delta-Sigma Phase/Frequency Detector - A PLL includes independent frequency-locking and phase-locking operational modes. In addition, the PLL includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (DS) phase/frequency detector. The detector may be implemented based on a continuous-time 1st-order DS Analog to Digital (ADC) converter. The ADC may be enhanced to 2nd-order by using, e.g., closed loop frequency detection. The PLL includes a fine resolution encoder for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise. | 12-04-2014 |
20140354336 | Digital PLL With Hybrid Phase/Frequency Detector and Digital Noise Cancellation - Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ PFD). A hybrid 2nd-order ΔΣ PFD may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ΔΣ quantization noise. The implementation of low complexity ΔΣ PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO). | 12-04-2014 |
20150048871 | REFERENCE-FREQUENCY-INSENSITIVE PHASE LOCKED LOOP - A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal. | 02-19-2015 |
20150061737 | PHASE LOCKED LOOP WITH BANDWIDTH CONTROL - A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal. | 03-05-2015 |
20150061738 | CHARGE PUMP CIRCUIT - There is provided a charge pump circuit, including: a step-up circuit unit stepping up an input voltage at least once, according to a frequency and a voltage level of a clock signal; and a control unit altering the voltage level of the clock signal according to an output voltage from the step-up circuit unit to regulate the output voltage from the step-up circuit. | 03-05-2015 |
20150077164 | PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING USING CHARGE PUMP CURRENT MODULATION - A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to perform a closed loop curve search operation to select one of the operating curves in the multi-curve VCO and to perform a curve tracking operation using the selected operating curve, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current during the curve tracking operation. | 03-19-2015 |
20150109035 | Phase-Locked Loop Filter with Coarse and Fine Tuning - A loop filter for a phase locked loop (PLL) having fast tuning capability while limiting phase noise. The filter includes a fine tune input port to receive a fine tune signal from the phase detector and a coarse tune input port to receive a coarse tune signal from the coarse tuner. The external coarse tuner provides the majority of the voltage slew on the loop filter while a fine tune control, thus reducing tune time. in one embodiment, the loop filter includes a voltage divider to limit the effective tuning sensitivity and thus control noise induced on a voltage-controlled oscillator from the loop filter. An elliptical filter may be employed to attenuate fractional spurs within the filter output signal. | 04-23-2015 |
20150116016 | Dead-Zone Free Charge Pump Phase-Frequency Detector - A charge-pump phase-frequency detector includes first and second flip-flops first and second delay circuits, a charge pump circuit and a reset gate. The flip-flops each have a respective data input connected to a fixed logic level, a reset input, a data output, and a clock input. The clock inputs of the first and second flip-flops are connected to receive a frequency reference signal and a feedback signal derived from the VCO, respectively. The reset gate includes a respective input connected to the data output of each of the flip-flops, and an output connected to the reset inputs of the flip-flops via the first delay circuit. The charge pump circuit includes an up input connected to the data output of the first flip-flop via the second delay circuit, a down input connected to the data output of the second flip-flop, and a control current output. | 04-30-2015 |
20150116017 | SELF-BIASED PHASE LOCK LOOP - A self-biased Phase Locked Loop (PLL) is provided. The self-biased PLL includes a bias current generator configured to generate a bias current Ib, wherein the bias current Ib includes one or more adjustable parameters for adjusting a loop bandwidth wn of the self-biased PLL. The one or more adjustable parameters in the bias current Ib includes at least one of a reference voltage Vref and a reference frequency Fref. | 04-30-2015 |
20150145568 | TIME-TO-DIGITAL CONVERTOR-ASSISTED PHASE-LOCKED LOOP SPUR MITIGATION - Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur. | 05-28-2015 |
20150145569 | TIME-TO-VOLTAGE CONVERTER USING A CAPACITOR BASED DIGITAL TO ANALOG CONVERTER FOR QUANTIZATION NOISE CANCELLATION - Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error. | 05-28-2015 |
20150145570 | TIME-TO-DIGITAL CONVERTER BASED ON A VOLTAGE CONTROLLED OSCILLATOR - A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators. | 05-28-2015 |
20150318859 | CHARGE PUMP CIRCUIT USED FOR CHARGE PUMP PHASE-LOCKED LOOP - A charge pump circuit used for a charge pump phase-locked loop that includes a charging and discharging unit, two complementary circuit units, two operational amplifier units, an inverter unit, and a current mirror unit. The charge pump circuit resolves the matching problem of charging and discharging currents and the charge sharing problem in existing charge pump circuits. Both complementary circuit units positively and reversely compensate the charging and discharging unit to keep the charging and discharging currents of capacitors constant. Thus, the problem of the change of charging and discharging currents is resolved, the voltage linear variation of the charge pump capacitors is achieved, and the charging and discharging of the capacitors can be accurately controlled. The charge pump circuit is simple in structure, easy to integrate, high in the matching precision of the charging and discharging current sources, and suitable for low voltage and low power consumption applications. | 11-05-2015 |
20150318860 | LOW NOISE PHASE LOCKED LOOPS - Aspects of circuits and methods for generating an oscillating signal are disclosed. The circuit includes a phase detector configured to output first and second signals responsive to a phase difference between two input signals. The phase detector is further configured to disable the first signal when outputting the second signal and to disable the second signal when outputting the first signal. The circuit further includes a voltage controlled oscillator (VCO) configured to generate an oscillating signal having a tunable frequency responsive to the first and second signals. | 11-05-2015 |
20150340946 | CHARGE PUMP CIRCUIT AND PLL CIRCUIT - A charge pump circuit includes a constant current circuit configured to have one terminal connected with a power source node; a first node configured to input or output a current; a second node configured to be set to have a potential difference with the first node being less than or equal to a predetermined value; a first transistor configured to have one terminal connected with the first node; a second transistor configured to have one terminal connected with the second node, and to operate inverse to an operation of the first transistor; and a third transistor configured to be connected between a connection node, to which another terminal of the first transistor and another terminal of the second transistor are connected, and another terminal of the constant current circuit. The third transistor has a gate connected with a constant voltage source, and functions as a constant current source. | 11-26-2015 |
20150358025 | PHASE LOCKED LOOP CIRCUIT EQUIPPED WITH UNITY GAIN BANDWIDTH ADJUSTMENT - An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control noise and power consumption. The additional circuitry includes a comparator and a measurement stage configured to measure and adjust a unity gain bandwidth of the phase locked loop. In one embodiment, the measurement stage includes two frequency-to-current converters and associated current mirrors. | 12-10-2015 |
20160006442 | Capacitance Multiplier and Loop Filter Noise Reduction in a PLL - According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path. | 01-07-2016 |
20160013784 | SIGNAL ADJUSTMENT CIRCUIT | 01-14-2016 |
20160013801 | REFERENCE-FREQUENCY-INSENSITIVE PHASE LOCKED LOOP | 01-14-2016 |
20160020689 | CHARGE PUMP CIRCUIT AND PHASE LOCK LOOP CIRCUIT HAVING THE SAME - A charge pump circuit and a phase lock loop circuit (PLL) having the same are provided. A main voltage divider and an assistant voltage divider configured in the charge pump circuit generate a voltage division within a predetermined time of activating the charge pump circuit. Therefore, when the charge pump circuit initiates operating, a voltage of a control end of a main switch set configured in the charge pump circuit is set to be the voltage division. The voltage of the control end is gradually decreased from the voltage division to a stable voltage according to a first current and a second current flowing through the main switch set. Accordingly, it can decrease the time from initiating operation of the pump circuit to stabilizing the voltage of the control end, thereby it can increase the working efficiency of the PLL. | 01-21-2016 |
20160043636 | Charge Pump with Matched Currents - A charge pump provides matched charging and discharging currents. One transistor is connected to an input of a charge pump core while two transistors are connected to the other input of the charge pump core, with each of the transistors mirroring a reference transistor through different mirroring pathways so that current through the transistor of the first input is equal to the sum of currents through the two transistors of the second input. | 02-11-2016 |
20160056826 | SEMICONDUCTOR DEVICE AND PHASE LOCKED LOOP INCLUDING THE SAME - Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor. | 02-25-2016 |
20160065224 | FAST FREQUENCY THROTTLING AND RE-LOCKING TECHNIQUE FOR PHASE-LOCKED LOOPS - Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO. | 03-03-2016 |
20160087525 | CHARGE PUMP WITH SUPPRESSED FEEDTHROUGH EFFECT - A charge pump circuit includes a capacitor, a current source circuit coupled to the capacitor for providing a charging current and a discharging current to the capacitor. The current source circuit includes a switch transistor with a gate terminal for receiving a control signal, a current source transistor having a source terminal coupled to a drain of the switch transistor, and a feedthrough suppression capacitor coupled between a gate terminal of a gate terminal of the switch transistor and a gate terminal of the current source transistor. The feedthrough suppression capacitor is configured to lower a feedthrough effect. | 03-24-2016 |
20160105189 | DELAY CIRCUIT, DELAY LOCKED LOOP CIRCUIT INCLUDING DELAY CIRCUIT AND PROCESSOR INCLUDING DELAY LOCKED LOOP CIRCUIT - A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers. | 04-14-2016 |
20160142063 | PHASE LOCKED LOOP AND ASSOCIATED METHOD FOR LOOP GAIN CALIBRATION - A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal. | 05-19-2016 |
20160164405 | HIGH-SPEED RESISTOR-BASED CHARGE PUMP FOR ACTIVE LOOP FILTER-BASED PHASE-LOCKED LOOPS - Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased. | 06-09-2016 |
20160164528 | FREQUENCY SOURCE WITH IMPROVED PHASE NOISE - A frequency source with improved phase noise. In one embodiment a phase-locked loop is used as a component of a frequency source and a signal to noise enhancer (SNE) is used to suppress phase noise produced by the phase-locked loop. The signal to noise enhancer is a nonlinear passive device that attenuates low-power signals while transmitting high power signals with little loss. The signal to noise enhancer may be fabricated as a thin film of yttrium iron garnet (YIG) epitaxially grown on a gadolinium gallium garnet (GGG) substrate, the GGG substrate being secured to a microwave transmission line from the input to the output of the signal to noise enhancer, such that the thin film of yttrium iron garnet is close to the transmission line. | 06-09-2016 |
20160181979 | Thyristor-Based Optoelectronic Oscillator with Tunable Frequency and Optical Phase Lock Loop Employing Same | 06-23-2016 |
20160182059 | Phase Switching PLL and Calibration Method | 06-23-2016 |
20160182064 | CHARGE PUMP CIRCUIT, PHASE LOCKED LOOP APPARATUS, INTEGRATED CIRCUIT, AND METHOD OF MANUFACTURE OF A CHARGE PUMP | 06-23-2016 |
20160204785 | Low Power and Integrable On-Chip Architecture for Low Frequency PLL | 07-14-2016 |
20160254817 | LEAKAGE COMPENSATION CIRCUIT FOR PHASE-LOCKED LOOP (PLL) LARGE THIN OXIDE CAPACITORS | 09-01-2016 |