Class / Patent application number | Description | Number of patent applications / Date published |
327151000 | With counter | 9 |
20090128202 | Timer unit circuit having plurality of output modes and method of using the same - First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits. | 05-21-2009 |
20090322387 | OUTPUT ENABLE SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency. | 12-31-2009 |
20100127740 | Semiconductor apparatus and anomaly detection method of the same - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal. | 05-27-2010 |
20110080194 | SEMICONDUCTOR APPARATUS AND ANOMALY DETECTION METHOD OF THE SAME - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal. | 04-07-2011 |
20110309864 | Apparatus and Method for Generating a Timing Signal - An apparatus is provided for generating a timing signal having an input for receiving a first signal indicating successive time intervals, means for receiving a second signal indicating successive time intervals, and a generator adapted to generate a timing signal based on the second signal and on a relationship between one or more time intervals of the first signal and one or more time intervals of the second signal. This arrangement enables a timing signal to be generated using a time signal produced by a source or device and to be based on a time signal produced by another source or device. | 12-22-2011 |
20120105113 | DATA TRANSFER CIRCUIT AND DATA TRANSFER METHOD FOR CLOCK DOMAIN CROSSING - A circuit that transfers data between a first clock domain using a first clock and a second clock domain using a second clock synchronized with the first clock. The circuit comprises a data holding circuit operating at the first clock, an enable signal generation circuit connected to the data holding circuit. Preferably, the data transfer circuit includes an edge signal generation circuit connected to the data holding circuit, the edge signal generation circuit generating an edge signal allowing the data holding circuit to receive and send the data when edges of the first clock and the second clock align, and applying the edge signal to the data holding circuit. | 05-03-2012 |
20130015893 | MULTI-CLOCK REAL-TIME COUNTERAANM Severson; Matthew L.AACI San DiegoAAST CAAACO USAAGP Severson; Matthew L. San Diego CA US - A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode | 01-17-2013 |
20130285719 | POWER SYSTEM DATA ACQUISITION SYSTEMS - A system comprising an interface configured to condition a signal associated with a power system; a clock module configured to generate a synchronization signal; and a module coupled to the interface and configured to digitize the signal from the interface; filter the digitized signal; and generate a time-shifted, digitized signal in response to the filtering and the synchronization signal. | 10-31-2013 |
20140203850 | POWER MANAGED SYNCHRONIZERS FOR ASYNCHRONOUS INPUT SIGNALS - Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain. The circuitry also includes a clock gater coupled to a clock input of the plurality of clock-gated synchronizers and coupled to receive an input clock and an enable signal. The clock gater is configured to provide the input clock to the plurality of synchronizers only upon receiving the enable signal. The circuitry also includes an enable generator coupled to receive the asynchronous input signals and configured to generate the enable signal for the clock gater responsive to the asynchronous input signals. | 07-24-2014 |