Entries |
Document | Title | Date |
20080218226 | CIRCUITS AND APPARATUS TO IMPLEMENT DIGITAL PHASE LOCKED LOOPS - Circuits and apparatus to implement digital phase locked loops are disclosed. A disclosed example digital phase locked loop circuit comprises a phase detector to detect a phase difference between a reference signal and a feedback signal, a time digitizer to convert the phase difference to a digital value, and an adder to add an offset to the digital value, the offset selected to reduce a digital phase locked loop dead zone | 09-11-2008 |
20080231332 | Clock Signal Generation Device, Semiconductor Integrated Circuit, and Data Reproduction Method - The present invention improves a lead-in time of the PLL with a phase error detector having an enlarged range of phase error detection and gain control based on the PLL synchronous state. The phase error detection range is enlarged by correcting the phase error detection point in a case where the phase error increases. A locked state of the PLL is determined based on a standard deviation of the smoothed phase error values and the gains are switched between a lead-in transient state and a stationary state. As a result, it is possible to shorten and stabilize the lead-in time of the PLL. | 09-25-2008 |
20080284474 | Techniques for integrated circuit clock management - A clock generator ( | 11-20-2008 |
20080290915 | SYSTEM AND METHOD FOR FAST RE-LOCKING OF A PHASE LOCKED LOOP CIRCUIT - A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles. | 11-27-2008 |
20080309385 | ELECTRONIC DEVICE AND METHOD FOR ON CHIP SKEW MEASUREMENT - The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value. | 12-18-2008 |
20090051395 | DC/DC converter with spread spectrum switching signals - A DC/DC converter includes a converting circuit for converting a first voltage into a second voltage; a controller for generating spread spectrum switching signals; and a switch according to the spread spectrum switching signals controlling the on/off state of the switch. | 02-26-2009 |
20090278577 | SEMICONDUCTOR DEVICE INCLUDING PHASE DETECTOR - A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal. | 11-12-2009 |
20090289672 | Method of processing signal data with corrected clock phase offset - The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained. | 11-26-2009 |
20100201412 | OSCILLATOR, AND RECEIVING DEVICE AND ELECTRONIC DEVICE USING THE OSCILLATOR - An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices. | 08-12-2010 |
20100213992 | Delay locked loop circuit and operation method thereof - A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal. | 08-26-2010 |
20100277210 | THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION - a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews. | 11-04-2010 |
20110006818 | CLOCK SYNCHRONIZATION SYSTEM, NODE, CLOCK SYNCHRONIZATION METHOD, AND PROGRAM - The invention provides a clock synchronization system which synchronizes the clock of a slave node with the clock of a master node by use of a timestamp packet transmitted from the master node to the slave node on the packet network, wherein the slave node includes a phase comparison part | 01-13-2011 |
20110156771 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal. | 06-30-2011 |
20110221487 | CLOCK SYNCHRONISER - A clock synchroniser for generating a local clock signal synchronised to a received clock signal. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. | 09-15-2011 |
20110298503 | Dynamic voltage-controlled oscillator calibration and selection - A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically. Another selection routine comprises a successive voltage-controlled oscillator routine that executes every time a frequency is requested by comparing a requested frequency to different frequency thresholds without executing a calibration operation. | 12-08-2011 |
20110304364 | Device For Removing Electromagnetic Interference And Semiconductor Package Including The Same - Provided is an electromagnetic interference (EMI) removing device for active reduction of electromagnetic interference and a semiconductor package including the same. The EMI removing device may include a film substrate having an antenna pattern configured to generate a second electromagnetic wave, which may have substantially the same frequency band, modulation mode, and directivity as a first electromagnetic wave generated by a first semiconductor chip and a phase opposite to a phase of the first electromagnetic wave | 12-15-2011 |
20110316593 | Phase Locked Loop with Startup Oscillator and Primary Oscillator - A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator. | 12-29-2011 |
20120013374 | PHASE-LOCK ASSISTANT CIRCUITRY - Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock. | 01-19-2012 |
20120043999 | MEMS STABILIZED OSCILLATOR - A voltage controlled crystal oscillator (VCXO) is locked to a MEMS oscillator with a variable frequency ratio that is a function of a sensed temperature. That allows the long-term stability of the MEMS oscillator and temperature compensation to be reflected in a VCXO output signal having good short-term stability. | 02-23-2012 |
20120068741 | PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME - A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal. | 03-22-2012 |
20120074993 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component. | 03-29-2012 |
20120133401 | PLL CIRCUIT, ERROR CORRECTING METHOD FOR THE SAME, AND COMMUNICATION APPARATUS INCLUDING THE SAME - A PLL circuit includes: the number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of the oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity. | 05-31-2012 |
20120161826 | COMPENSATING DFLL WITH ERROR AVERAGING - A compensating DFLL (CDFLL) is disclosed that utilizes temperature readings at regular intervals in combination with production characterization data of a reference oscillator to compensate for frequency drift and nominal frequency error. In some implementations, the CDFLL selects a calibration value that is not optimal for frequency accuracy to minimize accumulated frequency error over time. More particularly, during a calibration run, mismatch between an ideal frequency and an actual frequency is measured, and the measurement is used as a starting point for a next calibration run, such that the accumulated frequency error is averaged almost to zero over time. | 06-28-2012 |
20120161827 | CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE - A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals. | 06-28-2012 |
20120194231 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal. | 08-02-2012 |
20120200323 | PHASE-LOCK ASSISTANT CIRCUITRY - A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal. | 08-09-2012 |
20120235716 | ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE - An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop. | 09-20-2012 |
20130009679 | BANG-BANG PHASE DETECTOR WITH HYSTERESIS - In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state. | 01-10-2013 |
20130057325 | AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE - Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation. | 03-07-2013 |
20130113533 | TEMPERATURE COMPENSATED FREQUENCY REFERENCE COMPRISING TWO MEMS OSCILLATORS - A temperature compensated frequency reference comprising first MEMS oscillator (MEMS | 05-09-2013 |
20130207699 | FREQUENCY-LOCKED SYNTHESIZER WITH LOW POWER CONSUMPTION AND RELATED SYSTEM AND METHOD - An apparatus includes a first oscillator configured to generate a reference signal and a second oscillator configured to generate an output signal having a controllable frequency. The apparatus also includes a frequency difference detector configured to generate a difference signal having a frequency based on a frequency difference between the reference signal and the output signal. The apparatus further includes a discriminator configured to modify the frequency of the output signal based on the difference signal. The frequency difference detector can be configured to generate the difference signal having multiple pulses. The discriminator can be configured to count a number of pulses in the difference signal during a specified time period and to modify the frequency of the output signal based on the counted number of pulses. The specified time period can be adjustable. | 08-15-2013 |
20140055178 | ADAPTIVE PHASE-SHIFTED SYNCHRONIZATION CLOCK GENERATION CIRCUIT AND METHOD FOR GENERATING PHASE-SHIFTED SYNCHRONIZATION CLOCK - The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator. | 02-27-2014 |
20140091842 | Hybrid AFC using DCXO and RF PLL - A technique to provide hybrid compensation to correct for drifts in a reference frequency output from a digitally-controlled crystal oscillator (DCXO). A first compensation is provided to the DCXO to adjust for overlap or discontinuity of the reference frequency caused by switching capacitors in the capacitor array that controls drift of the reference frequency output. The second compensation is obtained at a phase-locked loop (PLL) that receives the reference frequency signal from the DCXO. The second compensation adjusts the PLL to adjust for variations of the reference frequency that remain after performing compensation in the DCXO. | 04-03-2014 |
20140159785 | METHOD AND APPARATUS FOR ATOMIC FREQUENCY AND VOLTAGE CHANGES - A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core. | 06-12-2014 |
20140184287 | ADJUSTABLE POLE AND ZERO LOCATION FOR A SECOND ORDER LOW PASS PATH FILTER USED IN A PHASE LOCK LOOP CIRCUIT - This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor. | 07-03-2014 |
20140240011 | METHOD AND ARRANGEMENT FOR GENERATING A CLOCK SIGNAL BY MEANS OF A PHASE LOCKED LOOP - A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output. | 08-28-2014 |
20140285245 | PLL CIRCUIT - A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency. | 09-25-2014 |
20140285246 | PLL CIRCUIT - A PLL circuit that operates in synchronization with an operating clock and generates and outputs a generated clock in synchronization with an external clock, including a multi-phase clock generating unit that generates multi-phase clocks including n clocks which have a same frequency and differ in phase one another, one of the clocks in the multi-phase clock being the operating clock, a frequency signal generating unit that outputs a frequency signal based on a phase difference signal from a phase comparator, an oscillating unit that generates and outputs a clock oscillating with a frequency corresponding to the frequency signal, and the phase comparator that measures a time difference between rising times or falling times of the inputted external clock and the oscillating unit based on the n clocks in the multi-phase clocks, and outputs a phase difference signal indicating the time difference based on a result of the measurement. | 09-25-2014 |
20150042387 | DATA RECOVERY CIRCUIT AND OPERATING METHOD THEREOF - A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal. | 02-12-2015 |
20150116014 | SAMPLE-RATE CONVERSION IN A MULTI-CLOCK SYSTEM SHARING A COMMON REFERENCE - A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL. | 04-30-2015 |
20150116015 | CLOCK GENERATING DEVICE, ELECTRONIC APPARATUS, MOVING OBJECT, CLOCK GENERATING METHOD - A clock generating device measures a frequency ratio between a clock signal (32.768 kHz+α) and a reference frequency value based on a clock signal (25 MHz); generates a clock signal obtained by masking a portion of clocks of the clock signal based on a measurement result of the frequency ratio; and updates a compensation value of a frequency temperature characteristic of the clock signal when a difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results is greater than a reference value of the frequency ratio. | 04-30-2015 |
20160036454 | ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) WITH REDUCED SETTLING TIME - Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time. | 02-04-2016 |