Class / Patent application number | Description | Number of patent applications / Date published |
327094000 | Sample and hold | 72 |
20080211545 | SAMPLE-AND-HOLD APPARATUS AND OPERATING METHOD THEREOF - A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively. | 09-04-2008 |
20080246517 | Sample and Hold Circuits - The voltage produced by an input current (i | 10-09-2008 |
20090009219 | Reducing Power Consumption In An Amplification Stage Driving A Sample And Hold Circuit While Maintaining Linearity - An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption. | 01-08-2009 |
20090039923 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant. A second capacitor is provided, having a first terminal connected to the first terminal of the resistor and having a second terminal connected to a power supply terminal. The second capacitor substantially reduces frequency-dependent harmonic distortion. | 02-12-2009 |
20090039924 | Systems and methods for reducing distortion in semiconductor based sampling systems - Circuits and methods that improve the performance of electronic sampling systems are provided. Parasitic capacitance associated with bootstrap circuitry is reduced, thereby decreasing signal distortion caused by capacitive loading at the input of the sampling circuit. The impedance of a sampling semiconductor switch is maintained substantially constant during sample states, at least in part, by accounting for non-linear parasitic capacitances associated with a sampling switch control terminal in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 02-12-2009 |
20090039925 | SAMPLE-AND-HOLD AMPLIFICATION CIRCUITS - A sample-and-hold amplification circuit comprises an amplifier, a first sample-and-hold unit, and a second sample-and-hold unit. The amplifier has an input terminal and an output terminal. The first sample-and-hold unit is coupled to the input terminal and the output terminal. The second sample-and-hold unit is coupled to the input terminal and the output terminal. When the first sample-and-hold unit is arranged to perform a sampling operation, the second sample-and-hold unit performs a holding operation, and when the first sample-and-hold unit is arranged to perform the holding operation, the second sample-and-hold unit performs the sampling operation. | 02-12-2009 |
20090072868 | WIDEBAND TRACK-AND-HOLD AMPLIFIER - A wideband track-and-hold amplifier is provided. The wideband track-and-hold amplifier is provided in front of an analog-to-digital converter, receives and samples an analog signal, and transfers the sampled signal to the analog-to-digital converter, wherein an output load unit having an inductance component is connected to an input terminal of the analog-to-digital converter. Therefore, it is possible to compensate for a high capacitance component of an analog-to-digital converter, to increase the bandwidth of an output signal, and to improve system linearity. | 03-19-2009 |
20090102517 | Track-And-Hold Circuit With Adjustable Charge Compensation - A circuit design incorporates charge compensation devices within a Track-and-Hold (T/H) circuit to control channel charge generated by a tracking switch. Calibrating a T/H circuit requires selecting charge compensation devices from an array of similar devices to function within the T/H circuit to absorb charge ejected from the tracking switch. The charge compensation devices can also be pseudorandomly selected to operate within the T/H circuit. Charge compensation devices are used to enhance the performance of bottom-plate sampling systems as well as bootstrapped T/H circuits. | 04-23-2009 |
20090167364 | CURRENT SAMPLING METHOD AND CIRCUIT - A current sampling circuit including a current sampling transistor, a capacitor arrangement between the gate and source of the current sampling transistor and an amplifier provided in a feedback loop between the gate and source of the current sampling transistor. A switch controls the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement. The capacitor arrangement comprises a first capacitor circuit for sampling a gate source voltage in a first sampling phase and a second capacitor circuit, with the first and second capacitor circuits arranged for together sampling the gate source voltage in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled in the first sampling phase. | 07-02-2009 |
20090219057 | Systems and methods for determining an out of band signal - Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock. | 09-03-2009 |
20090219058 | CORRELATED DOUBLE SAMPLING CIRCUIT AND SAMPLE HOLD CIRCUIT - A correlated double sampling circuit has a sampling capacitor equally divided into a plurality of portions. In the correlated double sampling circuit, an input signal is sampled at a plurality of sampling points and an averaging switch is closed to obtain an average value of a plurality of sampling values obtained by sampling. High frequency noise superimposed on the input signal is thus reduced and a difference between the average values of the plurality of sampling values obtained by sampling is output. | 09-03-2009 |
20090219059 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 09-03-2009 |
20090219060 | METHOD AND APPARATUS OF SFDR ENHANCEMENT - A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15 dB. | 09-03-2009 |
20090237120 | SAMPLE-AND-HOLD CIRCUIT AND CCD IMAGE SENSOR - Noise is more effectively reduced in one circuit. When sampling and holding is performed, switching of an ON resistance of MOS transistors (MSH | 09-24-2009 |
20090267653 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - For a semiconductor integrated circuit device such as AFE including a CDS amplifier, in case of excessive signal input to the CDS amplifier, a technique capable of preventing the response characteristic of the CDS amplifier from deteriorating is provided. In the AFE including the CDS amplifier, the CDS amplifier is prevented from becoming saturated by detecting an excessive signal input and triggering the reset of the CDS amplifier. Thereby, no abnormality occurs in the transient response of the CDS amplifier. Specifically, comparison of input signals to the CDS amplifier is performed by a comparator and the CDS amplifier is reset by a reset circuit (by fixing the input terminals of the CDS amplifier to a constant voltage) in case of excessive signal input, so that the CDS amplifier will not amplify excessive signal inputs. | 10-29-2009 |
20100066414 | LEAKAGE COMPENSATION FOR SAMPLE AND HOLD DEVICES - A sample and hold circuit in one aspect includes first and second switches. The first switch can be coupled to receive an input signal and to sample the input signal using a first capacitor. A first leakage current flows between first and second conductive terminals of the first switch and accumulates as a first leakage charge in the first capacitor. A second leakage current flows between the first and second conductive terminals of the second switch and accumulates as a second leakage charge in the second capacitor. An offset circuit produces a compensated sampled value by subtracting a quantity from a signal developed in response to the held sampled signal and charge accumulated through the first switch, wherein the quantity is developed in response to the accumulated leakage charge in the second capacitor. | 03-18-2010 |
20100109710 | SAMPLER BLOCKER PROTECTED AGAINST SWITCHING PARASITES - The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase. | 05-06-2010 |
20100117687 | TRACK AND HOLD CIRCUITS FOR AUDIO SYSTEMS AND OEPRATIONAL METHODS THEREOF - A track and hold circuit includes an operational amplifier having first and second input ends and first and second output ends. A first capacitor has a first end and a second end operably coupled with the first input end and the first output end of the operational amplifier, respectively, wherein the second end of the first capacitor is switchably coupled with a first input voltage (V | 05-13-2010 |
20100164551 | SAMPLE-AND-HOLD (S/H) CIRCUIT - A sample-and-hold circuit ( | 07-01-2010 |
20100194441 | LEAKAGE COMPENSATION FOR SAMPLE AND HOLD DEVICES - A sample and hold circuit with leakage compensation is disclosed. An example sample and hold circuit includes a first switch coupled to sample and hold an input signal value in a first capacitor coupled to the first switch in response to a sample signal. A second switch through which a second leakage current flows to a second capacitor coupled to the second switch is also included. The second leakage current through the second switch to the second capacitor is substantially equal to a first leakage current through the first switch to the first capacitor. An offset circuit that is coupled to the first and second capacitors is also included to produce a compensated sampled value in response to a difference between a quantity representing the held input signal value and charge accumulated in the first capacitor in response to the first leakage current from a quantity representing charge accumulated in the second capacitor in response to the second leakage current. | 08-05-2010 |
20100225360 | Apparatus and Method for Frequency Conversion and Filter Thereof - The present invention relates to an apparatus for frequency conversion, comprising: an analog-to-digital (A/D) converter, receiving and sampling an input signal according to a sampling frequency for producing a first digital signal, and the sampling frequency and the frequency of the input signal having a correspondence; a sign conversion circuit, used for receiving the first digital signal, and performing a sign conversion on the first digital signal and producing a second digital signal; a first switching module, used for selecting one of the first digital signal and the second digital signal as an output signal according to the sampling frequency; a filter, coupled to the first switching module, used for filtering the output signal from the first switching module, and producing a filter signal; and a second switching module, coupled to the filter, used for outputting the filter signal to a first output path or a second output path alternately according to the sampling frequency. Thereby, according to the present invention, by means of the correspondence between the sampling frequency and the frequency of the input signal, the use of a filter and an A/D converter can be saved, and thus reducing circuit area and cost. | 09-09-2010 |
20100237908 | LOW CURRENT COMPARATOR WITH PROGRAMMABLE HYSTERESIS - A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state ( | 09-23-2010 |
20110012644 | SAMPLING CIRCUITS - A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain. | 01-20-2011 |
20110018589 | BOOTSTRAPPED CLOCK GENERATOR AND TRACK-AND-HOLD CIRCUIT INCLUDING THE SAME - A track-and-hold circuit includes a bootstrapped clock generator and a track-and-hold unit. The bootstrapped clock generator receives an input voltage signal and generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than the level of the power supply voltage. The boost capacitor voltage is a voltage that is charged across a boost capacitor included in the bootstrapped clock generator and the sampling control signal is generated based on a clock signal. The track-and-hold unit samples and holds the input voltage signal in response to the sampling control signal to generate a sampled signal. | 01-27-2011 |
20110032003 | OFFSET CANCELLATION FOR SAMPLED-DATA CITCUITS - A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period. | 02-10-2011 |
20110043257 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 02-24-2011 |
20110148473 | SWITCH-BODY PMOS SWITCH WITH SWITCH-BODY DUMMIES - An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. | 06-23-2011 |
20110156759 | SAMPLE AND HOLD CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A sample and hold circuit comprises an input stage amplifier circuit for amplifying an input signal and a hold circuit for holding an output signal of the input stage amplifier circuit, with a sampling clock signal as a trigger, is further provided with a bias current switching circuit for switching a bias current of the input stage amplifier circuit to another circuit that is functionally independent of the sample and hold circuit, in a case where the hold circuit is in a hold period, to supply the bias current to the circuit. | 06-30-2011 |
20110204927 | ELECTRONIC CIRCUIT SYSTEM, TRACK HOLD CIRCUIT MODULE, ELECTRONIC CIRCUIT OPERATION CONTROL METHOD, AND PROGRAM THEREOF - Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased. | 08-25-2011 |
20110309862 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit including: a first data hold circuit configured to hold an input signal from a first input terminal; a second data hold circuit configured to hold the input signal from the first input terminal and an input signal from a second input terminal; a gate circuit configured to input an output signal of the first data hold circuit and an output signal of the second data hold circuit and to output a signal corresponding to the output signals of the first and second data hold circuits when the output signals of the first and second data hold circuits are the same as each other; and a third data hold circuit configured to hold the output signal of either the gate circuit or the second data hold circuit, and outputs the output signal to an output terminal | 12-22-2011 |
20120038390 | GIGABIT-SPEED SLICER LATCH WITH HYSTERESIS OPTIMIZATION - Improved master latch for high-speed slicer providing enhanced input signal sensitivity. A pre-charging circuit injects charge into the sources of the differential pair of a latch that samples the input signal during odd clock cycles. This reduces the gate-to-source voltage of the sampling pair, making them less sensitive to data bits latched by a second parallel master latch in odd clock cycles. The injected charge dissipates before the sampling pair is needed to fully sample the input signal in even clock cycles. The pre-charging circuit includes a current mirror, a current source and a transistor that couples the current source to the current mirror during odd clock cycles. A shunt peaked amplifier with excess peaking boosts the high-frequency content of a differential input signal relative to its low-frequency content. Capacitors cross-couple the gates and drains of the differential sampling pair. These supply an equal but opposite gate current than supplied by the intrinsic gate-to-drain capacitance, thereby reducing net current to the gate, and jitter on the input signal. | 02-16-2012 |
20120092042 | SEMICONDUCTOR DEVICE AND SAMPLE-AND-HOLD CIRCUIT - A semiconductor device includes a MOS transistor switch that controls passage and interruption of a signal by switching between an ON state and an OFF state, a first switch connected between a back gate terminal of the MOS transistor switch and a source terminal of the MOS transistor switch, and a second switch connected between the back gate terminal of the MOS transistor switch and a power supply voltage terminal If the MOS transistor switch is in the ON state, the first switch is in the ON state and the back gate terminal of the MOS transistor switch is connected to the source terminal of the MOS transistor switch. If the MOS transistor switch is in the OFF state, the second switch is in the ON state, and the back gate terminal of the MOS transistor switch is connected to the power supply voltage terminal. | 04-19-2012 |
20120194223 | TIME-INTERLEAVED SAMPLE-AND-HOLD - A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits. | 08-02-2012 |
20120274362 | TRACKING AND HOLD OPERATIONS FOR AN ANALOG-TO-DIGITAL CONVERTER - Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase. | 11-01-2012 |
20120280722 | TRACK AND HOLD CIRCUIT - A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device. | 11-08-2012 |
20120313666 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120313667 | SYSTEM AND METHODS TO IMPROVE THE PERFORMANCE OF SEMICONDUCTOR BASED SAMPLING SYSTEM - Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch. | 12-13-2012 |
20120313668 | INPUT CONFIGURATION FOR ANALOG TO DIGITAL CONVERTER - A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase. | 12-13-2012 |
20130135012 | Positive/Negative Sampling and Holding Circuit - A positive/negative sampling and holding (S/H) circuit is disclosed herein. The positive/negative S/H circuit includes an operational amplifier, a first capacitor, a second capacitor being parallel with the first capacitor and forming an integration circuit with the operational amplifier, and several discharge switches correspondingly connecting discharge paths of the first and the second capacitors to control the first and the second capacitors to output a first sampling signal and a second sampling signal respectively, and herein, the first and the second sampling signals has the same magnitude but opposite voltage polarities. | 05-30-2013 |
20130229206 | Systems and Methods for Compression of High-Frequency Signals - Systems and methods for compressing high-frequency signals are described in certain embodiments herein. According to certain embodiments, a high-frequency signal can be converted into a lower frequency signal so that it can be processed by one or more devices in a lower frequency infrastructure. In certain embodiments, the high-frequency signal can be compressed by certain signal conditioning components and an algorithm executed by a computer processor to at least receive a high-frequency signal, correct the high-frequency signal, determine a number of samples to be taken from the high-frequency signal (i.e., sample the high-frequency signal), store a value associated with the sampled signal, and generate a waveform that includes lower frequency content that may represent the original, high-frequency signal. | 09-05-2013 |
20130285705 | SAMPLE AND HOLD CIRCUIT - A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases. | 10-31-2013 |
20130285706 | INTERPOLATION CIRCUIT AND RECEPTION SYSTEM - An interpolation circuit includes: a first node to receive a first current; a second node to receive a second current; a third node to receive a third current; a first capacitor circuit including: first capacitors; a first switch to couple one end of each of first capacitors to one of first and second nodes; and a first output coupled to the other end of each of first capacitors; a second capacitor circuit including: second capacitors; a second switch to couple one end of each of second capacitors to one of second and third nodes; and a second output node coupled to the other end of each of second capacitors; and a third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch to couple the other end of the third capacitor to one of first and second output nodes. | 10-31-2013 |
20140049291 | NOISE-RESISTANT SAMPLING CIRCUIT AND IMAGE SENSOR - An approach for a sampling circuit to reduce noise in signals (e.g., as received from photo diodes or the like) is provided. In one embodiment of the present invention, there is a sampling circuit comprising: an amplifier, which amplifies charge signals generated at photo diodes and converts them to voltage signals; the first sample and hold circuit, which samples the voltage signal and charges the first capacitor according to the first switching signal, and outputs the stored charge as a reset signal based on a readout signal; the second sample and hold circuit, which samples the signals and charges the second capacitor according to the second switching signal that is non-overlapping to the first switching signal, and outputs the stored charge as a reset signal based on the readout signal; a resistor that acts as a low-pass filter placed in between the first and the second capacitors' common nodes. | 02-20-2014 |
20140253177 | SAMPLING NETWORK - A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches. | 09-11-2014 |
20140292375 | ANALOG ACCUMULATOR - Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit. | 10-02-2014 |
20150130513 | SAMPLING DEVICE WITH TIME-INTERLEAVED OPTICAL CLOCKING - A sampling device comprising a first input port and a second input port, wherein an input-signal is fed to the first input port and wherein an optical clock signal is fed to the second input port. The sampling device comprises a plurality of track and hold units, wherein each of the plurality of track and hold units is connected to the first input port. The plurality of the track and hold units is further connected to the second input port through an optical waveguide in such a manner that the plurality of tack and hold units operate in a time-interleaved mode. | 05-14-2015 |
20160012912 | SAMPLING CIRCUIT | 01-14-2016 |
20160148706 | COMPACT SAMPLE-AND-HOLD DEVICE - The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q | 05-26-2016 |
327095000 | Having feedback | 7 |
20090058473 | ACTIVE PRE-EMPHASIS FOR PASSIVE RC NETWORKS - An approach that provides active pre-emphasis for a passive RC network is described. In one embodiment, there is a circuit that comprises an RC filter including a resistive divider formed from a first resistor and a second resistor and a filtering capacitor. The first resistor is configured to receive an input voltage and the second resistor and filtering capacitor are in parallel and configured to generate a reference voltage that is a percentage of the input voltage. An operational amplifier is coupled to the RC filter. A first multiplexer controlled by a pulse pre-emphasis signal is coupled to the operational amplifier and the RC filter. A second multiplexer controlled by a sample and hold clocking signal has inputs that are coupled to the first multiplexer and ground. | 03-05-2009 |
20090072869 | SAMPLE AND HOLD CIRCUIT AND RELATED DATA SIGNAL DETECTING METHOD UTILIZING SAMPLE AND HOLD CIRCUIT - Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results. | 03-19-2009 |
20100109711 | LOW NOISE CORRELATED DOUBLE SAMPLING AMPLIFIER FOR 4T TECHNOLOGY - A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases. | 05-06-2010 |
20100259302 | CAPACITOR NONLINEARITY CORRECTION - A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals. | 10-14-2010 |
20110309863 | DIFFERENTIAL AMPLIFIER, SAMPLE-AND-HOLD CIRCUIT, AND AMPLIFIER CIRCUIT - To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively. | 12-22-2011 |
20130249601 | SAMPLING CIRCUIT FOR MEASURING REFLECTED VOLTAGE OF TRANSFORMER FOR POWER CONVERTER OPERATED IN DCM AND CCM - A sampling circuit of the power converter according to the present invention comprises an amplifier circuit receiving a reflected voltage for generating a first signal. A first switch and a first capacitor are utilized to generate a second signal in response to the reflected voltage. A sample-signal circuit generates a sample signal in response to the disable of a switching signal. The switching signal is generated in accordance with a feedback signal for regulating an output of the power converter. The feedback signal is generated in accordance with the second signal. The sample signal is utilized to control the first switch for sampling the reflected voltage. The sample signal is disabled once the first signal is lower than the second signal. The sampling circuit precisely samples the reflected voltage of the transformer of the power converter for regulating the output of the power converter. | 09-26-2013 |
20140300389 | Sample and Hold Circuit with Reduced Noise - A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state. | 10-09-2014 |
327096000 | With differential amplifier | 17 |
20080258776 | ANALOG SIGNAL TRANSMISSION CIRCUIT - An analog signal transmission circuit includes a sampling switch supplied with an analog signal, a capacitor connected between an output side terminal of the sampling switch and a low-potential power supply, and a differential amplifier connected to an output side terminal of the sampling switch. The circuit samples the analog signal by turning on/off the sampling switch and outputs a signal achieved by amplifying an accumulation voltage of the capacitor in the differential amplifier. The differential amplifier has a differential input portion including a first transistor connected to a first terminal of the capacitor, a second transistor, a constant current source, and an actuating switch that is connected between the constant current source and the differential input portion. The analog signal transmission circuit further includes a pre-charge circuit that pre-charges a wire between the different input portion and the actuating switch. | 10-23-2008 |
20090066370 | Track and Hold Circuit - Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier. | 03-12-2009 |
20090153198 | LOW-LEAKAGE SWITCH FOR SAMPLE AND HOLD - An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S | 06-18-2009 |
20090201051 | Sample-and-Hold Circuit and Pipeline Ad Converter Using Same - A switched capacitor sample-and-hold circuit using a source grounded input operational amplifier, wherein a feed forward circuit or a feedback circuit is provided in the operational amplifier and connected to the feedback capacitor of the operational amplifier via switches, an input common voltage or a middle point voltage of outputs is detected, and a difference of the same from a reference voltage is previously charged in the feedback capacitor, thereby suppressing fluctuation of an output operation point at the time of amplification of the operational amplifier. | 08-13-2009 |
20090237121 | Correlated double sampling technique - A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier. | 09-24-2009 |
20100219864 | Dual Mode, Single Ended to Fully Differential Converter Structure - A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode. | 09-02-2010 |
20110001518 | OPERATING A SWITCHED-CAPACITOR CIRCUIT WITH REDUCED NOISE - Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal. | 01-06-2011 |
20110050287 | HIGH SPEED TRACK AND HOLD CIRCUIT - Examples of systems and methods are provided for tracking-and-holding an input signal. The system may produce a pair of differential voltage outputs responsive to a pair of differential voltage inputs. The system may couple, in response to a clock signal, an input amplifier circuit to an output circuit or decouple the input amplifier circuit from the output circuit. The system may couple the input amplifier to an electrical ground. The system may track values of a pair of differential voltage outputs when a switching circuit is in a closed position and to hold the values of the pair of differential voltage outputs constant when the switching circuit is in an open position. | 03-03-2011 |
20110074467 | Power Supply Method, Apparatus, and System for a Radio Frequency Power Amplifier - A power supply apparatus for a radio frequency power amplifier (RFPA) is provided, where the output end of a voltage controlled voltage source (VCVS) and the output ends of N current controlled current sources (CCCSs) are coupled in parallel to supply power to the RFPA. The apparatus further includes an n | 03-31-2011 |
20110210764 | Double switched track-and-hold circuit - A double switched track-and-hold circuit includes an input buffer having a first switched amplifier circuit for passing an input signal in a track mode and isolating the input signal from a buffer output in a hold mode, and a track-and-hold core circuit responsive to the input buffer and having a second switched amplifier circuit for tracking the input signal in a track mode and isolating the input signal from a track-and-hold output in a hold mode. The first and second switching amplifier circuits turn off approximately simultaneously during the hold mode to provide enhanced isolation. | 09-01-2011 |
20110279148 | SAMPLE AND HOLD CIRCUIT AND A/D CONVERTER APPARATUS - A sample and hold circuit includes an operational amplifier; a sampling capacitor configured to sample input voltages at a plurality of different timings; an adding/subtracting unit configured to perform an adding or subtracting operation of the input voltages sampled by the sampling capacitor; and an offset voltage removing unit configured to remove an input offset voltage component of the operational amplifier from a voltage obtained by the adding or subtracting operation. The operational amplifier is configured to produce an output by holding the voltage from which the input offset voltage component of the operational amplifier has been removed by the offset voltage removing unit. | 11-17-2011 |
20120169379 | VOLTAGE HOLD CIRCUIT - A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state. | 07-05-2012 |
20120274363 | NOISE CANCELLATION SYSTEM AND METHOD FOR AMPLIFIERS - An architecture of an integrated circuit allows for the canceling of noise sampled on a capacitor in the integrated circuit, after an input signal has already been sampled. Thermal noise correlated with an arbitrary input signal may be canceled after selectively controlling a plurality of switching devices during a sequence of clock phases. An auxiliary capacitor may be used to store a voltage equal to the thermal noise and enable the cancellation of the thermal noise from the sampled signal in conjunction with a noise cancellation unit. | 11-01-2012 |
20130135013 | Multi-stage Sample and Hold Circuit - The present invention discloses a multi-stage sample and hold (S/H) circuit that includes: a first S/H circuit for sampling a sensing signal of a sensor multiple times and accumulating them into a first sampled signal, and outputting the first sampled signal; and a second S/H circuit for receiving the plurality of first sampled signals and accumulating them into a second sampled signal. As a result, when one or more first sampled signals are saturated due to instantaneous noise, the second sampled signal is not saturated, thereby increasing the noise tolerance of the multi-stage S/H circuit. | 05-30-2013 |
20130162299 | Analog sample circuit with switch circuit - Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC). | 06-27-2013 |
20130307587 | SAMPLE AND HOLD CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A sample and hold circuit comprises an input stage amplifier circuit for amplifying an input signal and a hold circuit for holding an output signal of the input stage amplifier circuit, with a sampling clock signal as a trigger, is further provided with a bias current switching circuit for switching a bias current of the input stage amplifier circuit to another circuit that is functionally independent of the sample and hold circuit, in a case where the hold circuit is in a hold period, to supply the bias current to the circuit. | 11-21-2013 |
20160104543 | Multi-Stage Sample and Hold Circuit - A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node. | 04-14-2016 |