Class / Patent application number | Description | Number of patent applications / Date published |
326010000 | Redundant | 34 |
20080218197 | PROGRAMMABLE LOGIC DEVICE HAVING REDUNDANCY WITH LOGIC ELEMENT GRANULARITY - A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the defective logic element to the non-defective logic element. | 09-11-2008 |
20090002015 | ERROR CORRECTING LOGIC SYSTEM - The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system. | 01-01-2009 |
20090058457 | REDUNDANT CRITICAL PATH CIRCUITS TO MEET PERFORMANCE REQUIREMENT - Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational. | 03-05-2009 |
20090066361 | Semiconductor integrated circuit device and storage apparatus having the same - A semiconductor integrated circuit device includes: a first large scale integrated circuit including a plurality of first logical blocks; a programmable second large scale integrated circuit connected the first large scale integrated circuit and including a second logical block; a memory storing data for achieving the purposes of the first logical blocks; and a control unit that, when a failure is detected in any of the first logical blocks during the operation of the first large scale integrated circuit, writes the data for the faulty first logical block stored in the memory to the second logical block, and uses the second logical block in place of the faulty first logical block. | 03-12-2009 |
20090251169 | INTEGRATION OF LBIST INTO ARRAY BISR FLOW - A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality. | 10-08-2009 |
20100060309 | MULTI-ROW BLOCK SUPPORTING ROW LEVEL REDUNDANCY IN A PLD - In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections when a fault occurs. The redundant internal logic connections extend through a row, linking the row above a defective row with a row below the defective row. Elements in a multi-row block are configurable to perform a default function and a function of an element in a neighboring row, if the functions are different. | 03-11-2010 |
20100060310 | Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects - An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect. | 03-11-2010 |
20100164537 | Semiconductor device and method of fabricating the same - Provided is a semiconductor device and a method of fabricating the same. The semiconductor device may include at least one logic circuit and at least one spare circuit. The at least one spare circuit may be that is a substitute for the at least one logic circuit and may not be connected to a power voltage source and/or a ground voltage source. | 07-01-2010 |
20100308858 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SIGNAL PROCESSING APPARATUS - A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width. | 12-09-2010 |
20110169522 | FAULT-TOLERANT MULTI-CHIP MODULE - A multi-chip module (MCM) is described. This MCM includes multiple sites, where a given site in the multiple sites includes multiple chips with proximity connectors that communicate information through proximity communication within the MCM via multiple components associated with the given site. Note that the MCM includes global redundancy and local redundancy at the given site. In particular, the global redundancy involves providing one or more redundant sites in the multiple sites. Furthermore, the local redundancy involves providing one or more redundant chips in the multiple chips and one or more redundant components in the multiple components. | 07-14-2011 |
20130193999 | SEQUENTIAL CIRCUIT WITH CURRENT MODE ERROR DETECTION - A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals. | 08-01-2013 |
20150070048 | VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES - Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit. | 03-12-2015 |
20150295578 | METHOD FOR THE RADIATION HARDENING OF AN ELECTRONIC CIRCUIT BY PARTITIONING - The method relates to a method for the radiation hardening of an electronic circuit by partitioning, said circuit including an odd number K of parallel branches connected to a same primary input I and each including a same series of N modules and N−1 nodes linking two consecutive modules, the K branches together forming a series of N−1 gates respectively consisting of parallel K nodes, and a primary arbiter forming a majority vote from the output signal of the K branches, the method being characterized in that it includes the following steps which are repeated for each one of the gates: determining a reliability of a subcircuit upstream from the gate consisting of the portions of the K branches located between the primary input and the gate, and the insertion of at least one arbiter at the gate forming a majority vote from the output signals of said portions of branches constituting the scanned subcircuit and outputting at least one majority signal to the respective inputs of an additional subcircuit formed by the branch portions downstream from the gate, if the reliability of the scanned subcircuit is less than a reliability set point. | 10-15-2015 |
20150349775 | Radiation Hardened By Design Digital Input/Output Circuits And Related Methods - Embodiments of radiation hardened by design digital input/output circuits are described herein. Other examples and related methods are also disclosed herein. | 12-03-2015 |
326011000 | Voter circuit (e.g., majority logic, etc.) | 7 |
20100026338 | Fault triggerred automatic redundancy scrubber - A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected. | 02-04-2010 |
20100141296 | HARDENED CURRENT MODE LOGIC (CML) VOTER CIRCUIT, SYSTEM AND METHOD - A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened. | 06-10-2010 |
20100315117 | Method of Acquiring a Plurality of Logic Signals, with Confirmation of State Validity - A method of ACM acquisition/confirmation of a plurality of logic signals SI(i) combines a loop for the single confirmation processing for all the sampled signals, with a sequential sampling of these signals. On each sampling, the confirmation loop processes the current sampled signal SI(i), in order to decide on the updating of an output register Qs(i) with the current sampled state S | 12-16-2010 |
20110012638 | METHODS AND CIRCUITRY FOR RECONFIGURABLE SEU/SET TOLERANCE - A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem. | 01-20-2011 |
20110241724 | Semiconductor device, and failure detection system and failure detection method of data hold circuit - A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits. | 10-06-2011 |
20130002288 | Electronic Circuit Arrangement for Processing Binary Input Values - Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X | 01-03-2013 |
20130009664 | (N-1)-OUT-OF-N VOTER MUX WITH ENHANCED DRIVE - This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N−1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths. | 01-10-2013 |
326012000 | With flip-flop | 5 |
20090051385 | Cell with Fixed Output Voltage for Integrated Circuit - The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell ( | 02-26-2009 |
20090189634 | SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS - A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. | 07-30-2009 |
20100264953 | Soft Error Hard Electronic Circuit and Layout - This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection. | 10-21-2010 |
20120139578 | SOFT-ERROR RESISTANT LATCH - A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types. | 06-07-2012 |
20140247068 | METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENTS OR GLITCHES IN DIGITAL ELECTRONIC CIRCUITS - A circuit structure ( | 09-04-2014 |
326013000 | With field effect-transistor | 4 |
20090289657 | SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES - The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective. | 11-26-2009 |
20100176841 | SEU TOLERANT ARBITER - Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter. | 07-15-2010 |
20110193588 | MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT - Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode. | 08-11-2011 |
20140015564 | SINGLE EVENT TRANSIENT AND UPSET MITIGATION FOR SILICON-ON-INSULATOR CMOS TECHNOLOGY - A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE. | 01-16-2014 |
20090289657 | SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES - The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective. | 11-26-2009 |
20100176841 | SEU TOLERANT ARBITER - Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter. | 07-15-2010 |
20110193588 | MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT - Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode. | 08-11-2011 |
20140015564 | SINGLE EVENT TRANSIENT AND UPSET MITIGATION FOR SILICON-ON-INSULATOR CMOS TECHNOLOGY - A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE. | 01-16-2014 |
326013000 | With field-effect transistor | 4 |
20090289657 | SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES - The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective. | 11-26-2009 |
20100176841 | SEU TOLERANT ARBITER - Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter. | 07-15-2010 |
20110193588 | MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT - Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode. | 08-11-2011 |
20140015564 | SINGLE EVENT TRANSIENT AND UPSET MITIGATION FOR SILICON-ON-INSULATOR CMOS TECHNOLOGY - A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE. | 01-16-2014 |
20090289657 | SYSTEMS AND METHODS FOR PROVIDING DEFECT-TOLERANT LOGIC DEVICES - The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective. | 11-26-2009 |
20100176841 | SEU TOLERANT ARBITER - Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter. | 07-15-2010 |
20110193588 | MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT - Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode. | 08-11-2011 |
20140015564 | SINGLE EVENT TRANSIENT AND UPSET MITIGATION FOR SILICON-ON-INSULATOR CMOS TECHNOLOGY - A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE. | 01-16-2014 |