Entries |
Document | Title | Date |
20080218196 | SYSTEM AND METHOD FOR PROTECTING DATA BASED ON GEOGRAPHIC PRESENCE OF A RESTRICTED DEVICE - A method of protecting data stored by an electronic device includes determining an identity of a restricted device. Also determined is the identity of restricted data associated with the restricted device, the restricted data being one or more items of data stored by the electronic device. Data protection for the restricted data to limit access to the restricted data by the restricted device in invoked when geographic presence of the restricted device with respect to the electronic device is detected. | 09-11-2008 |
20080224727 | Logic System for Dpa and/or Side Channel Attach Resistance - DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA-blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed. | 09-18-2008 |
20080252331 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors. | 10-16-2008 |
20080258754 | SECURITY ELEMENT FOR AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT INCLUDING THE SAME, AND METHOD FOR SECURING AN INTEGRATED CIRCUIT - An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has a determined electrical resistance which is used to monitor the validity of the fence. | 10-23-2008 |
20090085601 | SET DOMINANT LATCH WITH SOFT ERROR RESILIENCY - A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the logical value of the storage node does not correspond a logical value of an output node. The logic circuit may be a set dominant latch and a memory circuit may be formed based on the set dominant latch. | 04-02-2009 |
20090085602 | DELIBERATE DESTRUCTION OF INTEGRATED CIRCUITS - A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device. | 04-02-2009 |
20090085603 | FPGA configuration protection and control using hardware watchdog timer - An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received. | 04-02-2009 |
20090102505 | REMOTELY CONFIGURABLE CHIP AND ASSOCIATED METHOD - A chip is provided that includes a plurality of on-chip configurable features having a disabled and an enabled state. The on-chip configurable features are each operable to change from the disabled state to the enabled state upon receipt of a valid enablement configuration from an enabling entity. A method for the chip is provided to disable the plurality of on-chip configurable features before delivery of the chip to a new location. The chip is delivered to a new location where a unique hardware identifier and data for at least one of the on-chip configurable features is retrieved. The unique hardware identifier and the data are transmitted to an enabling entity. The enabling entity sends the enablement configuration to the chip. The chip is programmed with the enablement configuration, which enables the at least one on-chip configurable feature at the new location. | 04-23-2009 |
20090153181 | DATA RETENTION KILL FUNCTION - Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the memory component may include disposing a memory array on a substrate and coupling a control circuit to the memory array. The control circuit may be configured to selectively prevent access to data stored within the memory array upon removal of the memory component from the electronic system. Various additional methods, devices, and systems are also provided. | 06-18-2009 |
20090212813 | ELECTRONIC DEVICE BOARD LEVEL SECURITY - A system may include a printed circuit board, a first component located on the printed circuit board, the first component having a first unique identifier and a processor located on the printed circuit board, the processor including a one time programming section. The processor may acquire the first unique identifier from the first component and store the first unique identifier in the one time programming section during the first time initialization. Upon subsequent initializations, the processor may acquire the first unique identifier from the first component and compare the first unique identifier to the stored first unique identifier. The processor may allow the subsequent initializations to proceed if the first unique identifier matches the stored first unique. The processor may disallow the subsequent initializations from proceeding if the first unique identifier does not match the stored first unique identifier. | 08-27-2009 |
20090212814 | Deliberate Destruction of Integrated Circuits - A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device. | 08-27-2009 |
20090251168 | DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST A LASER ATTACK - An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device. | 10-08-2009 |
20090267636 | Security circuit having an electrical fuse ROM - A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed. | 10-29-2009 |
20090284279 | Integrated Circuit Having Inverse Bit Storage Test - An integrated circuit is provided having a memory storing first and second strings of bit values, each bit value in the second string being the logical inverse of a bit value at a corresponding bit position in the first string, and a processor configured to test whether the bit values of the second string are the inverse of the bit values at respective corresponding bit positions of the first string by combining the corresponding bits of the first and second strings. | 11-19-2009 |
20090302882 | Device forming a logic gate for minimizing the differences in electrical of electro-magnetic behavior in an intergrated circuit manipulating a secret - The invention relates to a logic gate whose consumption is independent from its input data and its logic state. To this end, the device uses logic means forming switches ( | 12-10-2009 |
20090302883 | Device forming a logic gate for detecting a logic error - The invention relates to a device for forming an electric circuit comprising logic means ( | 12-10-2009 |
20100026336 | FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION - An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected. | 02-04-2010 |
20100026337 | Interdependent Microchip Functionality for Defeating Exploitation Attempts - An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects. | 02-04-2010 |
20100045336 | Method and Device for Programmable Power Supply with Configurable Restrictions - The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a number of freeze/programmability levels, each freeze/programmability defining a dedicated access restriction to the programmability of the power supply device. | 02-25-2010 |
20100045337 | Methods, apparatuses, and products for a secure circuit - Methods, systems, apparatuses and products are disclosed for providing security circuits. Exemplary embodiments including semiconductor chips on circuit boards are shown, together with application in a movie stick/movie player pair. | 02-25-2010 |
20100085075 | INTEGRATED CIRCUIT AND METHOD FOR PREVENTING AN UNAUTHORIZED ACCESS TO A DIGITAL VALUE - An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact. | 04-08-2010 |
20100141295 | PROGRAMMABLE LOGIC DEVICE HAVING AN EMBEDDED TEST LOGIC WITH SECURE ACCESS CONTROL - An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device. | 06-10-2010 |
20100244888 | METHOD AND APPARATUS FOR INCREASING SECURITY IN A SYSTEM USING AN INTEGRATED CIRCUIT - An integrated circuit can be made more secure by programming a one time programmable circuit so that different signals are provided on terminals as compared to when the integrated circuit was not secure. Instead, or in addition, the integrated circuit can be made more secure by providing decode circuitry that can be used with the one time programmable circuit to select different internal address maps in response to an address value. The decode circuitry can use a first address map when the integrated circuit is secure, and a different address map when the integrated circuit is non-secure. | 09-30-2010 |
20100264952 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: an inter-equipment authentication section formed on a chip and configured to perform inter-equipment authentication between the inter-equipment authentication section itself and source equipment; a control section formed on the chip and configured to control the inter-equipment authentication, the control section operating when a system clock from an oscillation section is supplied, and being capable of giving instructions to stop the oscillation of the oscillation section; and an oscillation stop canceling section configured to output an oscillation stop canceling signal to restart the oscillation of the oscillation section, based upon whether or not 5 volts of DDC from the source equipment is supplied to an input terminal. The start of the operation of a microcontroller unit on a system on chip is cable of being controlled by the 5 volts of DDC, which are power supply voltage supplied from the source equipment via DDCs. | 10-21-2010 |
20100271066 | CIRCUIT PROTECTING APPARATUS AND ASSOCIATED METHOD, AND CIRCUIT PROTECTING LAYER - A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip. | 10-28-2010 |
20100301896 | PHASE-CHANGE MEMORY SECURITY DEVICE - A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit. | 12-02-2010 |
20110043245 | COMPONENT PROVIDED WITH AN INTEGRATED CIRCUIT COMPRISING A CRYPTOROCESSOR AND METHOD OF INSTALLATION THEREOF - In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic (latchup) thyristor and/or to the activation of a parasitic bipolar transistor, or to design a circuit having this property. If the component is stressed due to the presence of this circuit, it is immediately deactivated, actually preventing the revelation of the secrets thereof. | 02-24-2011 |
20110050279 | LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS - Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed. | 03-03-2011 |
20110062981 | DELIBERATE DESTRUCTION OF INTEGRATED CIRCUITS - A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device. | 03-17-2011 |
20110080190 | METHOD FOR PROTECTING AN INTEGRATED CIRCUIT CHIP AGAINST LASER ATTACKS - A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 μm from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate. | 04-07-2011 |
20110095782 | LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS - Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed. | 04-28-2011 |
20110115521 | DEACTIVATION OF INTEGRATED CIRCUITS - Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated from a substrate, is placed into an electromagnetic field of sufficient power to erase or reprogram the erasable non-volatile memory. The entire integrated circuit is permanently disabled by erasing, altering, or reprogramming the erasable non-volatile memory. In preferred embodiments, the integrated circuit comprises a non-erasable non-volatile memory storing the activation code, and circuitry adapted to permanently disable the integrated circuit when the code in the erasable non-volatile memory does not match the activation code in the non-erasable non-volatile memory. Erasing, altering, or reprogramming the erasable non-volatile memory results in a mismatch of the non-volatile memories, which permanently deactivates the integrated circuit. | 05-19-2011 |
20110148457 | PROTECTING ELECTRONIC SYSTEMS FROM COUNTERFEITING AND REVERSE-ENGINEERING - An exemplary embodiment provides an efficient solution for protecting electronic systems from counterfeiting and reverse-engineering. The exemplary embodiment may determine the operation of an electronic system by control logic. The control logic may be implemented by finite state machines (FSMs). The exemplary embodiment makes the behavior of the FSMs partially reconfigurable and hiding the configuration data in a secure memory device. With the configuration data stored in a secure memory device, the exemplary embodiment obfuscates the behavior of the FSMs both from the standpoint of the foundry as well as from adversaries. | 06-23-2011 |
20110156746 | PROGRAMMABLE LOGIC DEVICE HAVING AN EMBEDDED TEST LOGIC WITH SECURE ACCESS CONTROL - An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device. | 06-30-2011 |
20110181316 | Deactivation of Integrated Circuits - Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated from a substrate, is placed into an electromagnetic field of sufficient power to erase or reprogram the erasable non-volatile memory. The entire integrated circuit is permanently disabled by erasing, altering, or reprogramming the erasable non-volatile memory. In preferred embodiments, the integrated circuit comprises a non-erasable non-volatile memory storing the activation code, and circuitry adapted to permanently disable the integrated circuit when the code in the erasable non-volatile memory does not match the activation code in the non-erasable non-volatile memory. Erasing, altering, or reprogramming the erasable non-volatile memory results in a mismatch of the non-volatile memories, which permanently deactivates the integrated circuit. | 07-28-2011 |
20110193587 | Anti-Tampering Obscurity Using Firmware Power Mirror Compiler - In a preferred embodiment of the invention, a mirror compiler is provided for each protected device or circuit resulting in a program that is embedded into the protected device's source code. The mirror compiler can be configured to have multiple selectable compilation parameters offering the programmer flexible options for mirrored power cancellations. | 08-11-2011 |
20110215829 | IDENTIFICATION OF DEVICES USING PHYSICALLY UNCLONABLE FUNCTIONS - A method of generating a response to a physically unclonable function, said response being uniquely representative of the identity of a device having challengeable memory, the memory comprising a plurality of logical locations each having at least two possible logical states, the method comprising applying a challenge signal to an input of said memory so as to cause each of said logical locations to enter one of said two possible logical states and thereby generate a response pattern of logical states, said response pattern being dependent on said physically unclonable function which is defined by, the physical characteristics of said memory, the method further comprising reading out said response pattern. | 09-08-2011 |
20110227603 | Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures - A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope. | 09-22-2011 |
20110260749 | SYNCHRONOUS LOGIC SYSTEM SECURED AGAINST SIDE-CHANNEL ATTACK - An improvement in the security of a logic system from attacks that observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and method for reducing ability to monitor the relationship between currents in the system and the data in the system by closing the overall clock eye diagram, whilst keeping the eye diagram for connected stages open. The degree of eye closure for connected pipeline stages allows the system to run closer to its maximum operating speed compared to the use of system wide clock jitter, yet the overall closure provides security that is absent from systems with a partially open eye. | 10-27-2011 |
20110267095 | Apparatus and Method for Licensing Programmable Hardware Sub-Designs Using a Host-Identifier - Methods and apparatuses for enforcing terms of a licensing agreement between a plurality of parties involved in a particular hardware design through the use of hardware technologies. According to one embodiment, a hardware sub-design includes a license verification sub-design that is protected from user modification by encryption. In one embodiment, a license is generated based on a trusted host identifier within an external hardware device. In one embodiment, each trusted host identifier is unique, and no two integrated circuits share the same trusted host identifier. In another embodiment, the integrated circuit is a field programmable gate array or an application specific integrated circuit. In one embodiment, a license determines how long the hardware sub-design will operate when the hardware sub-design is implemented within an integrated circuit having a trusted host identifier. | 11-03-2011 |
20110285420 | LOGIC SYSTEM WITH RESISTANCE TO SIDE-CHANNEL ATTACK BY EXHIBITING A CLOSED CLOCK-DATA EYE DIAGRAM - An improvement in the security of a logic system by minimising observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and methods for reducing the ability of an intruder to monitor the relationship between currents in the system and the data in the system through the use of a randomised clock wherein the clock eye diagram is closed and without significant reduction in maximum operating speed compared to the reduction in maximum operating frequency that occurs when using conventional means of additive jitter. A system where the clock eye diagram is completely closed is provably more secure than systems where the clock eye diagram is partially open. | 11-24-2011 |
20110285421 | SYNCHRONOUS LOGIC SYSTEM SECURED AGAINST SIDE-CHANNEL ATTACK - An improvement in the security of a logic system from attacks that observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and method for reducing ability to monitor the relationship between currents in the system and the data in the system by closing the overall clock eye diagram, whilst keeping the eye diagram for connected stages open. The degree of eye closure for connected pipeline stages allows the system to run closer to its maximum operating speed compared to the use of system wide clock jitter, yet the overall closure provides security that is absent from systems with a partially open eye. | 11-24-2011 |
20110291696 | Method for Protecting a Logic Circuit Against External Radiation and Associated Electronic Device - A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times. | 12-01-2011 |
20120081142 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT MODULE TAMPERPROOF MODE PERSONALIZATION - A function of an integrated circuit is selectively disabled by mechanical intervention at a module that contains the integrated circuit, such as drilling a hole through the module, cutting a slot in the module or burning a hole with a laser through the laser. Mechanical destruction of the module at a predetermined spot disrupts a function enable signal that is otherwise provide through wires of the module to a connection with the integrated circuit. Without the function enable signal from the module wires to the integrated circuit connector, the function associated with the function enable signal cannot run on the integrated circuit. | 04-05-2012 |
20120081143 | DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS - A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit. | 04-05-2012 |
20120105099 | Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design - Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks. | 05-03-2012 |
20120139577 | HACKING DETECTING DEVICE, INTEGRATED CIRCUIT AND METHOD OF DETECTING A HACKING ATTEMPT - A hacking detecting device includes a metal line capacitor, a charge providing unit, a charge storing unit and a hacking deciding unit. The metal line capacitor has a first metal line and a second metal line. The charge providing unit periodically charges the metal line capacitor. The charge storing unit accumulates charges periodically stored in the metal line capacitor, and generates an output voltage corresponding to an amount of the accumulated charges. The hacking deciding unit determines whether the metal line capacitor is exposed based on the output voltage of the charge storing unit. | 06-07-2012 |
20120146684 | SWITCH TO PERFORM NON-DESTRUCTIVE AND SECURE DISABLEMENT OF IC FUNCTIONALITY UTILIZING MEMS AND METHOD THEREOF - Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device is in the error state. | 06-14-2012 |
20120182041 | Method for supporting a tie of a chip to an electronic apparatus - A method for supporting a tie of a chip to an electronic apparatus includes generating once a chip-specific characteristic variable in a chip, reading out the chip-specific characteristic variable by the chip, and transmitting characteristic data representing the read-out characteristic variable of the chip to an electronic apparatus. | 07-19-2012 |
20120200313 | APPARATUS FOR CLOCKED POWER LOGIC AGAINST POWER ANALYSIS ATTACK - A logic apparatus secure against a power analysis attack is disclosed. The logic apparatus may include a clocked power logic to recover and reuse at least a part of charges supplied during a single clock operation; a first device block connected to the clocked power logic to remove a parasitic capacitance difference in the clocked power logic, and a second device block to readjust remaining charges in each node of the clocked power logic after a single clock operation. | 08-09-2012 |
20120212253 | METHOD AND SYSTEM FOR IDENTIFYING COUNTERFEIT PROGRAMMABLE LOGIC DEVICES - A method for combating counterfeiting and tampering of integrated circuits includes the steps providing a programmable logic device, the programmable logic device including an arithmetic circuit implemented into the substrate, and constructing an arithmetic feedback oscillator using the arithmetic circuit. The step of constructing the arithmetic feedback oscillator includes incorporating a feedback loop into the arithmetic circuit and feeding output bits back into an input of the arithmetic circuit. The method also includes the step of selecting input values producing repeating values in a lesser order bit of a product of the arithmetic circuit when first and second input are applied to the arithmetic circuit and monitoring the lesser order bit and determining a predicted pattern. | 08-23-2012 |
20120268160 | IMPLEMENTING TEMPORARY DISABLE FUNCTION OF PROTECTED CIRCUITRY BY MODULATING THRESHOLD VOLTAGE OF TIMING SENSITIVE CIRCUIT - A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail. | 10-25-2012 |
20120274350 | SYSTEMS AND METHODS FOR PROVIDING USER-INITIATED LATCH UP TO DESTROY SRAM DATA - Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased. | 11-01-2012 |
20120274351 | METHOD AND APPARATUS FOR SECURING A PROGRAMMABLE DEVICE USING A KILL SWITCH - A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD. | 11-01-2012 |
20120306530 | ELECTRONIC DEVICE BOARD LEVEL SECURITY - A system may include a printed circuit board, a first component located on the printed circuit board, the first component having a first unique identifier and a processor located on the printed circuit board, the processor including a one time programming section. The processor may acquire the first unique identifier from the first component and store the first unique identifier in the one time programming section during the first time initialization. Upon subsequent initializations, the processor may acquire the first unique identifier from the first component and compare the first unique identifier to the stored first unique identifier. The processor may allow the subsequent initializations to proceed if the first unique identifier matches the stored first unique. The processor may disallow the subsequent initializations from proceeding if the first unique identifier does not match the stored first unique identifier. | 12-06-2012 |
20120319724 | SYSTEM AND METHODS FOR GENERATING UNCLONABLE SECURITY KEYS IN INTEGRATED CIRCUITS - A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use. | 12-20-2012 |
20130082733 | SIGNAL PROCESSING SYSTEM - A signal route of a PUF (Physical Uncloneable Function) circuit is configured in each device. The signal route of each device is connected by a connection route to form a transmission route. An arbiter is connected at the end of the transmission route. A signal is transmitted in the transmission route from a device to a device. The arbiter monitors the signal passed through the transmission route, and generates an output signal reflecting a characteristic unique to the transmission route, based on monitoring results. The authentication of identity among a combination of a plurality of devices is enabled by examining the output signal. | 04-04-2013 |
20130106461 | IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF) | 05-02-2013 |
20130141137 | Stacked Physically Uncloneable Function Sense and Respond Module - A physically uncloneable function (PUF) sense and response module fabricated from a stack of integrated circuit chip layers. At least one of the PUF chips in the stack has a unique identifier resulting from random effects of fabrication processes. The PUF chip generates the fingerprint at power-on resulting that in turn is used to generate a private key. The private key generates a public key used to communicate with the outside world. The encrypted data from the outside world is decrypted with the private key. The public key is stored for comparison with pubic keys generated at subsequent power-up operations. If the key changes, tampering is indicated and a predetermined tamper response event is generated such as the erasing of the contents of a memory. | 06-06-2013 |
20130147511 | Offline Device Authentication and Anti-Counterfeiting Using Physically Unclonable Functions - The output of a physically unclonable function (PUF) may be processed to reduce its size. The post-processing result is served as a device intrinsic unclonable identifier and is signed by the device manufacturer to create a certificate stored on board the same device that includes the physically unclonable function. This scheme may not require online verification and complex error correction on PUFs in some cases. | 06-13-2013 |
20130257473 | LONG-LIFE POWER SOURCE, LONG-LIFE EMBEDDED STRUCTURE SENSOR, REMOTE LONG-LIFE FLUID MEASUREMENT AND ANALYSIS SYSTEM, LONG-LIFE OFF-GRID ENCLOSED SPACE PROXIMITY CHANGE DETECTOR, SURFACE-MOUNT ENCRYPTION DEVICE WITH VOLATILE LONG-LIFE KEY STORAGE AND VOLUME INTRUSION RESPONSE, AND PORTABLE ENCRYPTED DATA STORAGE WITH VOLATILE LONG-LIFE KEY STORAGE AND VOLUME INTRUSION RESPONSE - A long-life embedded structure sensor, remote long-life fluid measurement and analysis system, long-life off-grid enclosed space proximity change detector, surface-mount encryption device with volatile long-life key storage and volume intrusion response, and a portable encrypted data storage with volatile long-life key storage and volume intrusion response are provided to be powered by and equipped with a long-life power source that can provide operative power for at least a twenty year duration. | 10-03-2013 |
20130271178 | METHOD AND APPARATUS FOR SECURING A PROGRAMMABLE DEVICE USING A KILL SWITCH - A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may he implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD. | 10-17-2013 |
20130278284 | SEMICONDUCTOR DEVICE AND CONTROL SYSTEM - To enhance the security of a semiconductor device, the semiconductor device has a regulator unit for generating an internal power supply voltage based on a power supply voltage supplied from outside, an internal circuit which operates on the internal power supply voltage, a current detection unit for monitoring a power supply current supplied to the internal circuit, and a control unit for controlling operation of the internal circuit. In the semiconductor device, when the current detection unit detects that the power supply current exceeds a predetermined threshold value, the control unit restricts the operation of the internal circuit. | 10-24-2013 |
20130293259 | HOMOGENEOUS DUAL-RAIL LOGIC FOR DPA ATTACK RESISTIVE SECURE CIRCUIT DESIGN - Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks. | 11-07-2013 |
20130300453 | FUEL DISPENSER INPUT DEVICE TAMPER DETECTION ARRANGEMENT - A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between the connector portion and the switch portion. The flexible circuit assembly is coupled with the printed circuit board at the connector portion. The flexible circuit assembly comprises a plurality of layers each comprising a flexible dielectric substrate and a switch disposed in the switch portion. The switch is in electrical communication with the tamper-response electronics of the printed circuit board via a conductive path. The flexible circuit assembly also comprises a tamper-responsive conductor circuit enclosing the conductive path. The tamper-responsive conductor circuit is in electrical communication with the tamper-response electronics of the printed circuit board. | 11-14-2013 |
20130307578 | TAMPER RESISTANT IC - According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth. | 11-21-2013 |
20130314121 | METHOD AND DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST BACKSIDE ATTACKS - A method for detecting an attack, such as by laser, on an electronic microcircuit from a backside of a substrate includes forming the microcircuit on the semiconductor substrate, the microcircuit comprising a circuit to be protected against attacks, forming photodiodes between components of the circuit to be protected, forming a circuit for comparing a signal supplied by each photodiode with a threshold value, and forming a circuit for activating a detection signal when a signal at output of one of the photodiodes crosses the threshold value. | 11-28-2013 |
20140035613 | IDENTIFICATION CIRCUIT AND METHOD FOR GENERATING AN IDENTIFICATION BIT USING PHYSICAL UNCLONABLE FUNCTIONS - An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal. | 02-06-2014 |
20140077835 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a logic circuit, the logic circuit including an attack detection circuit for checking multi-bit storage. The attack detection circuit includes an error determination circuit capable of detection through a logic operation such as a code theory and a light irradiation detection circuit having light detection elements, and the light detection elements are arranged so that the light irradiation detection circuit can detect errors of the number of bits beyond the detection limit of the error determination circuit. Due to error detection by the error determination circuit and light irradiation detection by the light irradiation detection circuit, the circuits complementarily detect fault attacks from outside. | 03-20-2014 |
20140091831 | ENFORCING PERFORMANCE LONGEVITY ON SEMICONDUCTOR DEVICES - Technologies for enforcing an expiration policy on an electronic engineering sample component includes a one-time programmable fuse to store a manufacture date of the electronic engineering sample component, another one-time programmable fuse to store an expiration date of the electronic engineering sample component, and a component life management engine to compare a current date of the electronic engineering sample component with the expiration date of the electronic engineering sample component. The component life management engine to disable or lock the electronic engineering sample component in response to determining that the current date of the electronic engineering sample component exceeds the expiration date of the electronic engineering sample component. In some embodiments, a computing device may enforce the expiration policy for the electronic engineering sample component. The computing device may also be communicatively coupled to a remote unlock server and may receive authorization to unlock a disabled engineering sample component. | 04-03-2014 |
20140091832 | INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS - An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed. | 04-03-2014 |
20140103957 | REACTIVE MATERIAL FOR INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE - The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate. | 04-17-2014 |
20140111245 | INTEGRATED CIRCUIT DESIGN PROTECTING DEVICE AND METHOD THEREOF - An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device. | 04-24-2014 |
20140145752 | ANTI-DISASSEMBLING DEVICE FOR ELECTRONIC PRODUCTS - An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled. | 05-29-2014 |
20140176182 | SHUT-OFF MECHANISM IN AN INTEGRATED CIRCUIT DEVICE - Described herein are technologies related to self-disabling feature of a integrated circuit device to avoid unauthorized access to stored data information | 06-26-2014 |
20140184266 | METHOD AND APPARATUS FOR CHIP SELF DEACTIVATION - In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have been monitored. | 07-03-2014 |
20140191781 | ACTIVE SHIELD WITH ELECTRICALLY CONFIGURABLE INTERCONNECTIONS - Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself. | 07-10-2014 |
20140218067 | GROUPING OF PHYSICALLY UNCLONABLE FUNCTIONS - A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+ | 08-07-2014 |
20140266296 | RECONFIGURABLE MULTI-PORT PHYSICAL UNCLONABLE FUNCTIONS CIRCUIT - A reconfigurable multi-port physical unclonable functions (RM-PUFs) circuit, including: an input signal interface, a first control circuit module, at least two RM-PUFs circuit units, and an output signal interface. Each RM-PUFs circuit unit includes a second control circuit module, an input module, an output module, and a deviation generation module. The input signal interface is connected to the first control circuit module, the first control circuit module is connected to the RM-PUFs circuit units, and the RM-PUFs circuit units are connected to the output signal interface. | 09-18-2014 |
20140327468 | PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT - Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip. | 11-06-2014 |
20140327469 | PHYSICAL UNCLONABLE FUNCTION GENERATION AND MANAGEMENT - Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states. | 11-06-2014 |
20140340112 | METHODS AND SYSTEMS FOR HARDWARE PIRACY PREVENTION - Provided are methods, systems, and devices for preventing hardware piracy. | 11-20-2014 |
20140354327 | Apparatus and Method for Generating Random Bits - An apparatus for generating random bits includes a plurality of mapping devices. A respective mapping device is configured to map a predefined number of input signals, with the aid of a combinatorial mapping, into a predefined number of output signals. The plurality of mapping devices are concatenated with one another, and at least one combinatorial mapping is configured such that a state change of an input signal of a respective mapping device is mapped on average onto more than one output signal of the respective mapping device. No feedback loop is present such that a state change of at least one feedback output signal of a specific mapping device is fed as a state change of at least one input signal to another mapping device such that one or a plurality of output signals of the specific mapping device is influenced by the state change of the feedback output signal. | 12-04-2014 |
20140375353 | SYSTEMS, PROCESSES AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING LOGIC ENCRYPTION UTILIZING FAULT ANALYSIS - Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit. | 12-25-2014 |
20150008955 | METHOD AND APPARATUS FOR SUPPORTING SELF-DESTRUCTION FUNCTION IN BASEBAND MODEM - A method and an apparatus for supporting a self-destruction function in a baseband modem are provided. A self-destruction method of a baseband modem includes sending a request for supplying power to a self-destruction unit to a power management unit when a command for performing the self-destruction is received from a base station and controlling the self-destruction unit to output a signal corresponding to a specific bit value. The signal output by the self-destruction unit is used to block a clock supplied from a Temperature-Compensated crystal Oscillator (TCXO) to the baseband modem through a logical operation with a signal output by the TCXO. | 01-08-2015 |
20150028917 | Semiconductor Component and an Operating Method for a Protective Circuit Against Light Attacks - A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor. | 01-29-2015 |
20150042375 | FUNCTIONAL TIMING SENSORS - A functional timing sensor includes a setup time violation detecting circuit, a hold time violation detecting circuit, and an interface from the setup time violation detecting circuit and the hold time violation detecting circuit. The interface provides a notification upon detection of a violation by either the setup time violation detecting circuit or the hold time violation detecting circuit. | 02-12-2015 |
20150084670 | SONOS FPGA Architecture Having Fast Data Erase and Disable Feature - A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells. | 03-26-2015 |
20150109022 | SEMICONDUCTOR CHIP AND METHOD FOR GENERATING DIGITAL VALUE USING PROCESS VARIATION - Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to a first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node. | 04-23-2015 |
20150123702 | Method and Apparatus for Authenticating a Semiconductor Die - The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied during semiconductor processing to provide a semiconductor die having devices of varied values. In other aspects, different areas of semiconductor dies are exposed during semiconductor processing to provide semiconductor dies with devices that vary in value from one die to the next. For each semiconductor die, a value generated based on the values of the die's respective devices can be associated with that die thereby enabling subsequent authentication of the semiconductor die. | 05-07-2015 |
20150130505 | CHARGE DISTRIBUTION CONTROL FOR SECURE SYSTEMS - Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block. | 05-14-2015 |
20150130506 | DEFENSE AGAINST COUNTERFEITING USING ANTIFUSES - A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip. | 05-14-2015 |
20150294943 | METHOD FOR MANUFACTURING A DIGITAL CIRCUIT AND DIGITAL CIRCUIT - A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state. | 10-15-2015 |
20150294944 | METHOD FOR MANUFACTURING A DIGITAL CIRCUIT AND DIGITAL CIRCUIT - A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input has a predetermined defined logic state. | 10-15-2015 |
20150303927 | CHIP AND METHOD FOR MANUFACTURING A CHIP - According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area. | 10-22-2015 |
20150304115 | APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE - Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value. | 10-22-2015 |
20150369865 | DETECTION OF FAULT INJECTION ATTACKS USING HIGH-FANOUT NETWORKS - An apparatus for detecting fault injection includes a high-fanout network, which spans an Integrated Circuit (IC), and circuitry. In some embodiments, the high-fanout network is continuously inactive during functional operation of the IC, and the circuitry is configured to sense signal levels at multiple sampling points in the high-fanout network, and to identify a fault injection attempt by detecting, based on the sensed signal levels, a signal abnormality in the high-fanout network. In some embodiments, the circuitry is configured to sense signal levels at multiple sampling points in the high-fanout network, to distinguish, based on the sensed signal levels, between legitimate signal variations and signal abnormalities in the high-fanout network during functional operation of the IC, and to identify a fault injection attempt by detecting a signal abnormality. | 12-24-2015 |
20150379309 | CHARGE DISTRIBUTION CONTROL FOR SECURE SYSTEMS - Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block. | 12-31-2015 |
20160020772 | APPARATUS AND METHOD FOR DETECTING AND PREVENTING LASER INTERROGATION OF AN FPGA INTEGRATED CIRCUIT - A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value. | 01-21-2016 |
20160028394 | FAULT PROTECTION FOR HIGH-FANOUT SIGNAL DISTRIBUTION CIRCUITRY - An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages. | 01-28-2016 |
20160041226 | INTEGRATED CIRCUIT WITH DISTRIBUTED CLOCK TAMPERING DETECTORS - A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored. | 02-11-2016 |
20160049935 | SYSTEMS, PROCESSES AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING LOGIC ENCRYPTION UTILIZING FAULT ANALYSIS - Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit. | 02-18-2016 |
20160173105 | PRINTED CIRCUIT BOARD SECURITY USING EMBEDDED PHOTODETECTOR CIRCUIT | 06-16-2016 |
20160182045 | RELIABILITY OF PHYSICAL UNCLONABLE FUNCTION CIRCUITS | 06-23-2016 |
20160204781 | SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS | 07-14-2016 |
20180025996 | PROTECTED INTEGRATED CIRCUIT | 01-25-2018 |
20220138351 | Detecting Security Vulnerabilities Introduced Between Versions of a Hardware Design - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying security vulnerabilities introduced by transformations to a hardware design. One of the methods includes obtaining a security model for an initial electronic hardware design and a modified electronic hardware design. An analysis process is performed on the initial representation and on the modified representation of the electronic hardware design according to the security model. If the modified electronic hardware design introduced a security vulnerability relative to the initial electronic hardware design, information representing the introduced security vulnerability is provided. | 05-05-2022 |