Entries |
Document | Title | Date |
20080197509 | Semiconductor package having stacked semiconductor chips - A semiconductor package including: a package substrate on the surface of which plural connection terminals are provided; a semiconductor chip on the surface of which plural bonding pads are provided; plural bonding wires that connect between the plural connection terminals and the plural bonding pads; a resin formed to fill a gap between the bonding wires and the surface of the semiconductor chip; and a semiconductor chip provided on the bonding wires via a film-shaped resin, wherein at least three of the plural bonding wires are formed at substantially the same heights and higher than other bonding wires. | 08-21-2008 |
20080203581 | INTEGRATED CIRCUIT - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal path being coupled to the first signal path, and a second substrate on the second interface layer. In one embodiment, the second substrate includes an electronic device, the electronic device being coupled to the second signal path of the second interface layer. | 08-28-2008 |
20080203582 | SEMICONDUCTOR DEVICE - A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced. | 08-28-2008 |
20080203583 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production. After the semiconductor chips are formed at wafer level, only the semiconductor chips having the excellent operation characteristic through the test are selectively bonded to the multilayer thin film structure, to provide the high quality package products in which the fault rate is maximally reduced. The light, thin, short and small BGA package according to the present invention enables small and slim communication devices, displayers and other diverse electronic devices, to be contributed to the increase of the competitiveness of the products to which the BGA package is applied. | 08-28-2008 |
20080203584 | Stacked-type semiconductor package - Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path. | 08-28-2008 |
20080211110 | SEMICONDUCTOR APPARATUS AND MOBILE APPARATUS - A semiconductor apparatus includes: a wiring board; a first semiconductor device mounted on the wiring board; a second semiconductor device which is stacked on the first semiconductor device and a projection part projects from the outer edge of the first semiconductor device; and a sealing resin layer which seals each semiconductor device. And the second semiconductor device has thereon a first analog cell, and a second analog cell which reaches a higher temperature than the first analog cell, and the second analog cell is arranged so as to include the projection part of the second semiconductor device. | 09-04-2008 |
20080224322 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a semiconductor device having a stacked layer structure and its manufacturing method that bring high yield and reliability. Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. As described above, a process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form. | 09-18-2008 |
20080230920 | Wire-Bonded Semiconductor Component with Reinforced Inner Connection Metallization - A semiconductor component comprising a semiconductor chip ( | 09-25-2008 |
20080230921 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a first semiconductor chip; a multilayer wiring which is formed on the first semiconductor chip and which is connected to the first semiconductor chip; a second semiconductor chip connected to the first semiconductor chip by way of the multilayer wiring; a sealing material which seals the second semiconductor chip; and projecting plugs which are connected to the multilayer wiring and whose extremities become exposed on the sealing material. | 09-25-2008 |
20080230922 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A technique for mounting a plurality of electronic parts on one surface of a wiring substrate is provided. A semiconductor device comprises a wiring substrate having connection pads disposed outside a parts mount; a plurality of electronic parts with the first surface having a plurality of electrodes and the second surface fixing; a first underlying insulation layer provided between the connecting pads and the electrodes; a first metal layer formed overlaid on the first underlying insulation layer and providing connections between the connecting pads and the electrodes; a second underlying insulation layer having electrically insulating properties, provided between the respective electrodes of adjacent electronic parts; a second metal layer formed overlaid on the second underlying insulation layer and providing connections between the respective electrodes of adjacent electronic parts; and a first surface insulation layer covering the first metal layer and a second surface insulation layer covering the second metal layer. | 09-25-2008 |
20080230923 | CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE - A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes. | 09-25-2008 |
20080237887 | SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND - A semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad. | 10-02-2008 |
20080237888 | Multichip semiconductor device, chip therefor and method of formation thereof - A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug. | 10-02-2008 |
20080237889 | Semiconductor package, method of fabricating the same, and semiconductor package mold - Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and the MSP, and a semiconductor package mold for fabricating the semiconductor package. The semiconductor package may include a first semiconductor chip package having a first substrate including a first surface having a center portion on which a first semiconductor chip is mounted, and at least one first boundary portion on which a plurality of conductive connection pad groups are formed, and a molding member including a body that covers the first semiconductor chip, and at least one extension that extends from the body towards a corner portion of the first surface of the first substrate, wherein the extension extends while avoiding the conductive connection pad group. The semiconductor package may further include a second semiconductor chip package stacked on the first semiconductor chip package, the second semiconductor chip including a second substrate on which at least one second semiconductor chip that is electrically connected to the conductive connection pad group may be mounted. | 10-02-2008 |
20080246162 | Stack package, a method of manufacturing the stack package, and a digital device having the stack package - A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips. | 10-09-2008 |
20080251934 | Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices - Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure. | 10-16-2008 |
20080251935 | Low shrinkage polyester thermosetting resins - The invention is based on the discovery that a certain polyester compounds are useful as b-stageable adhesives for the microelectonic packaging industry. The polyester compounds described herein contain ring-opening or ring-forming polymerizable moieties and therefore exhibit little to no shrinkage upon cure. In addition, there are provided well-defined b-stageable adhesives useful in stacked die assemblies. In particular, there are provided assemblies wherein the b-stageable adhesive encapsulates a portion of the wiring members contained within the bondline gap between the stacked die. | 10-16-2008 |
20080251936 | SEMICONDUCTOR DEVICE - The generation of a wire bonding defect is reduced in the semiconductor device in which semiconductor chips are laminated. A wiring substrate, the first memory chip by which face-up mounting is done via the first filmy adhesive on the wiring substrate, the second memory chip by which face-up mounting is done via the second filmy adhesive on the first memory chip, and the microcomputer chip by which face-up mounting is done via the third filmy adhesive on the second memory chip are included. Since the third filmy adhesive adhered to the microcomputer chip of the highest stage is the thinnest, at the time of wire bonding of the microcomputer chip, the influence to the ultrasonic wave and load of wire bonding by softening of a filmy adhesive which takes place with the heat can be reduced, and lowering of wire bonding property can be suppressed. | 10-16-2008 |
20080251937 | Stackable semiconductor device and manufacturing method thereof - A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided. | 10-16-2008 |
20080251938 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURE - A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection. | 10-16-2008 |
20080251939 | CHIP STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region. | 10-16-2008 |
20080251940 | CHIP PACKAGE - A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers. | 10-16-2008 |
20080251941 | Vertical system integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 10-16-2008 |
20080258312 | SEMICONDUCTOR DEVICE - The present invention enhances the reliability of a semiconductor device. The semiconductor device includes a package substrate having a dry resist film which covers some conductive portions out of a plurality of conductive portions formed on a main surface and a back surface and is formed of a film, a semiconductor chip which is mounted over the package substrate, conductive wires which electrically connect the semiconductor chip with the package substrate, a die-bonding film which is arranged between the main surface of the package substrate and the semiconductor chip, a plurality of solder bumps which are formed on the back surface of the package substrate, and a sealing body which is made of resin. By forming the dry resist film made of a film on the main surface and the back surface of the package substrate, it is possible to suppress the warping of the package substrate and hence, the occurrence of package cracks at the time of reflow mounting can be prevented thus enhancing the reliability of the semiconductor device. | 10-23-2008 |
20080265430 | Semiconductor Device an Process for Fabricating the Same - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 10-30-2008 |
20080265431 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the package are provided. The semiconductor package comprises: a mounting substrate including a bond finger; at least one semiconductor chip disposed on the mounting substrate, the semiconductor chip including a bonding pad; a first molding member disposed on the mounting substrate so as to cover the bond finger and the bonding pad, the first molding member including an interconnection path disposed inside the first molding member so as to connect the bond finger to the bonding pad; a conductive element disposed in the interconnection path; and a second molding member overlying the first molding member. The interconnection path can be formed by a laser process. The conductive element can be formed by conductive nanoparticles or metal wires. | 10-30-2008 |
20080265432 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE MULTI-CHIP PACKAGE - A multi-chip package includes a mounting substrate, a first semiconductor chip, a second semiconductor chip, a reinforcing member, conductive wires and an encapsulant. The first semiconductor chip is disposed on the mounting substrate. The second semiconductor chip is disposed on the first semiconductor chip. An end portion of the second semiconductor chip protrudes from a side portion of the first semiconductor chip. A reinforcing member is disposed on an overlapping region of the second semiconductor chip where the second semiconductor chip overlaps with the side portion of the first semiconductor chip such that the reinforcing member decreases downward bending of the second semiconductor chip from the side portion of the first semiconductor chip. The conductive wires electrically connect the first and second semiconductor chips to the mounting substrate. The encapsulant is disposed on the mounting substrate to cover the first and second semiconductor chips and the conductive wires. | 10-30-2008 |
20080265433 | INTERPOSER, SEMICONDUCTOR CHIP MOUNTED SUB-BOARD, AND SEMICONDUCTOR PACKAGE - A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. | 10-30-2008 |
20080265434 | SEMICONDUCTOR DEVICE HAVING A SEALING RESIN AND METHOD OF MANUFACTURING THE SAME - The semiconductor device | 10-30-2008 |
20080277800 | Semiconductor package and method of forming the same - Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip. | 11-13-2008 |
20080277801 | Semiconductor component and production method - A semiconductor device includes a first die, a substrate, and a first interconnect. The first die includes a first isolation region and a first contact at least partially overlapping the first isolation region. The substrate includes a second contact. The first interconnect couples the first contact to the second contact. The first interconnect is defined by a via through the first isolation region. | 11-13-2008 |
20080284043 | Base Semiconductor Component For a Semiconductor Component Stack and Method For the Production Thereof - A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same time to contact areas of the semiconductor chip and also to stack contact areas. The stack contact areas simultaneously form the upper side of the base semiconductor component and have an arrangement pattern corresponding to an arrangement pattern of external contacts of a semiconductor component to be stacked. | 11-20-2008 |
20080284044 | Capillary underfill of stacked wafers - A plurality of wafers are aligned and stacked on a thermally variable rotary table, the table and stack are rotated, and an underfill material is disposed and cured between wafers in the stack, bonding the wafers. Corresponding wafer portions of the plurality of wafers in the stack may be singulated from the stack, and may comprise semiconductor device packages either individually or when coupled with a substrate. | 11-20-2008 |
20080296779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aimed at providing a semiconductor device improved in reliability of bonding and yield of products, even when semiconductor chips having through electrodes are used, the semiconductor device of the present invention has a substrate; a stack placed on the substrate, and composed of a plurality of semiconductor chips (first semiconductor chip and second semiconductor chip), each having through electrodes, stacked while placing bumps connected to the through electrodes in between; and a reinforcing chip (semiconductor chip) provided on the stack specifically on the surface thereof opposite to the substrate-side surface, or between the substrate and the stack, wherein thickness of the reinforcing chip is larger than the thickest semiconductor chip out of the plurality of semiconductor chips. | 12-04-2008 |
20080303172 | METHOD FOR STACKING SEMICONDUCTOR CHIPS AND SEMICONDUCTOR CHIP STACK PRODUCED BY THE METHOD - Apparatus for packaging two chips includes, in some embodiments, a first chip having at least one elevation and at least one cutout on a bottom thereof. It also includes a second chip having at least one elevation and at least one cutout on a top thereof. In some embodiments disclosed, the elevations and cutouts of the first chip and the second chip are configured to allow the elevations to be intermeshed with the cutouts when the chips are stacked with the bottom of the first chip engaging the top of the second chip. | 12-11-2008 |
20080303173 | SEMICONDUCTOR DEVICE, A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A TESTING METHOD OF THE SAME - A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester. | 12-11-2008 |
20080303174 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 12-11-2008 |
20080303175 | Electronic circuit package - An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor | 12-11-2008 |
20080308946 | SEMICONDUCTOR ASSEMBLIES, STACKED SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES AND STACKED SEMICONDUCTOR DEVICES - Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns. | 12-18-2008 |
20080308947 | Die offset die to die bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate. | 12-18-2008 |
20080308948 | WAFER-TO-WAFER ALIGNMENTS - Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10 | 12-18-2008 |
20080315432 | Electrical Shielding in Stacked Dies by Using Conductive Die Dttach Adhesive - In example embodiment, there is an integrated circuit (IC) device ( | 12-25-2008 |
20080315433 | SELF-ALIGNED WAFER OR CHIP STRUCTURE, SELF-ALIGNED STACKED STRUCTURE AND METHODS FOR FABIRCATING THE SAME - A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface. | 12-25-2008 |
20080315434 | WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS - An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board). | 12-25-2008 |
20080315435 | METHODS FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE - An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and ten wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner. | 12-25-2008 |
20090001597 | SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT ELECTRICALLY CONNECTING A FRONT AND BACKSIDE THEREOF AND A METHOD OF MANUFACTURE THEREFOR - The disclosure provides a semiconductor device and method of manufacture. The method for manufacturing the semiconductor device includes providing a substrate having circuitry located thereover. The surface of the substrate is subjected to a first anisotropic etch, the first anisotropic etch forming an opening that extends only partially into the substrate. An opposing surface of the substrate is subjected to a second anisotropic etch, the second anisotropic etch forming an opposing opening that extends only partially into the substrate. Additionally, a first conductive layer is formed in electrical contact with the circuitry and lining sidewalls of the opening. A second conductive layer is formed along at least a portion of the second opposing surface and lining sidewalls of the opposing opening. The first conductive layer and the second conductive layer electrically contact one another. | 01-01-2009 |
20090001598 | Formation of Through Via before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 01-01-2009 |
20090001599 | DIE ATTACHMENT, DIE STACKING, AND WIRE EMBEDDING USING FILM - Systems, methods, and/or devices that facilitate stacking dies in a multi-die stack using film over wire and attaching a die to a substrate are presented. Film over wire (FOW) techniques can be employed to facilitate stacking dies that are the same or similar in size such that the wires bonded onto the lower die can be embedded in film used to attach the two dies. FOW techniques can also be employed to embed a smaller die and wires attached thereto in film underneath a larger die stacked on top of the lower die such that the larger die can be supported by the film in areas where the larger die would otherwise overhang. Die attach film can be utilized to facilitate attaching a die to a substrate such that all areas between the die and substrate are filled thereby reducing or eliminating delamination. | 01-01-2009 |
20090001600 | ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE AND METHODS OF FORMING THE SAME - An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die. | 01-01-2009 |
20090001601 | MEMORY ARRAY ON MORE THAN ONE DIE - For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed. | 01-01-2009 |
20090001602 | STACK PACKAGE THAT PREVENTS WARPING AND CRACKING OF A WAFER AND SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME - A stack package and a method for manufacturing the same. The stack package includes first and second semiconductor chips placed such that surfaces thereof, on which bonding pads are formed, face each other; a plurality of through-silicon vias formed in the first and second semiconductor chips; and a plurality of redistribution layers formed on the surfaces of the first and second semiconductor chips to connect the through-silicon vias to the corresponding bonding pad, wherein the redistribution layers of the first and second semiconductor chips contact each other. By forming the stack package in this manner, it is possible to prevent pick-up error and cracks from forming during the manufacturing process, and therefore the stack package can be reliable formed. | 01-01-2009 |
20090008793 | SEMICONDUCTOR DEVICE - A description is given of a device comprising a first semiconductor chip, a molding compound layer embedding the first semiconductor chip, a first electrically conductive layer applied to the molding compound layer, a through hole arranged in the molding compound layer, and a solder material filling the through hole. | 01-08-2009 |
20090008794 | Thickness Indicators for Wafer Thinning - A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set. | 01-08-2009 |
20090008795 | Stackable microelectronic device carriers, stacked device carriers and methods of making the same - A method of manufacturing a microelectronic package. The method includes the steps of attaching at least one microelectronic element to a tape having upper terminals projecting upwardly from an upper surface of a dielectric layer, so that top surfaces of the terminals are disposed coplanar with or above a top surface of the microelectronic element after the attaching step, electrically connecting the microelectronic element to at least some of the upper terminals; and further includes the step of applying an encapsulant to cover at least a portion of the upper surface of the dielectric layer, leaving the upper terminals surfaces of the terminals exposed. | 01-08-2009 |
20090008796 | COPPER ON ORGANIC SOLDERABILITY PRESERVATIVE (OSP) INTERCONNECT - Provided is a semiconductor package, and a method for constructing the same, including a first substrate, a first semiconductor chip attached to the first substrate, and a first copper wire. At least one of the first substrate and the first semiconductor chip has an Organic Solderability Preservative (OSP) material coated on at least a portion of one surface, and the first copper wire is wire bonded through the OSP material to the first substrate and the first semiconductor chip. | 01-08-2009 |
20090008797 | BOND PAD REROUTING ELEMENT, REROUTED SEMICONDUCTOR DEVICES INCLUDING THE REROUTING ELEMENT, AND ASSEMBLIES INCLUDING THE REROUTED SEMICONDUCTOR DEVICES - A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements. | 01-08-2009 |
20090008798 | SEMICONDUCTOR DEVICE SUITABLE FOR A STACKED STRUCTURE - A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate. | 01-08-2009 |
20090008799 | Dual mirror chips, wafer including the dual mirror chips, multi-chip packages, methods of fabricating the dual mirror chip, the wafer, and multichip packages, and a method for testing the dual mirror chips - Example embodiments provide a dual mirror chip, a wafer including the dual mirror chip, multi-chip packages and methods of fabricating the same. Example embodiments also provide a method of testing the dual mirror chip. According to example embodiments, a dual mirror chip may include a first type chip with a first output pad portion on a first side of the first type chip and a first input pad portion on a second side of the first type chip. The dual mirror chip may also include a second type chip to the side of the first type chip. The second type chip may include a second input pad portion on a first side of the second type chip and a second output pad portion on a second side of the second type chip. The dual mirror chip may also include at least one conductive line connecting the input pad portions. | 01-08-2009 |
20090014889 | Method for producing chip stacks, and associated chip stacks - The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is sawed to produce a plurality of singulated chip stacks. | 01-15-2009 |
20090014890 | MULTI-CHIP SEMICONDUCTOR DEVICE - An interposer has an opening in the central portion. A plurality of first electrode terminals are formed on the front surface near the opening of the interposer, a plurality of second electrode terminals are formed on the front surface of the peripheral portion thereof and corresponding ones of the plurality of first and second electrode terminals are electrically connected to one another via a plurality of wirings. A plurality of bump electrodes is formed on the front surface of a child chip. A plurality of bump electrodes containing a plurality of bump electrodes for connection with the exterior are formed on the front surface of a parent chip. The front surfaces of the parent chip and child chip are set to face each other with the interposer disposed therebetween and the bump electrodes are electrically connected to one another in the opening of the interposer. | 01-15-2009 |
20090014891 | Three-dimensional die-stacking package structure and method for manufacturing the same - This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice. | 01-15-2009 |
20090014892 | INTEGRATED CIRCUIT DEVICE - Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position. | 01-15-2009 |
20090014893 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER - An integrated circuit package in package system includes: providing a substrate having a first wire-bonded die with an active side mounted above; connecting the active side of the first wire-bonded die to the substrate with a bond-wire; mounting a wire-in-film adhesive having an isolation barrier over the first wire-bonded die; and encapsulating the first wire-bonded die, the bond-wires, and the wire-in-film adhesive with an encapsulation. | 01-15-2009 |
20090014894 | STACKED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element. | 01-15-2009 |
20090014895 | Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip - An interposer chip in accordance includes an insulating layer, conductive patterns and a dummy pattern. The conductive patterns are formed on the insulating layer. The dummy pattern is formed on the insulating layer to suppress a bending of the insulating layer. Further, the dummy pattern can have first isolating grooves formed along peripherals of the conductive patterns to isolate the dummy pattern from the conductive patterns. Thus, the interposer chip is not vulnerable to being bent. Further, an electrical short between the conductive patterns through the dummy pattern caused by particles is substantially avoided. | 01-15-2009 |
20090020885 | Semiconductor device and method of manufacturing the same - One embodiment in accordance with the invention can include a semiconductor device that includes a first substrate, a projection portion that has a first semiconductor chip mounted on the first substrate, a second substrate that is provided on the first substrate and is electrically coupled to the first substrate, and a second semiconductor chip that is mounted on the second substrate. An opening portion is formed by the second substrate. The projection portion is arranged in the opening portion. | 01-22-2009 |
20090020886 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Embodiments relate to a semiconductor device, which adopts no wiring or contact for electric connection of a plurality of chips, achieving improved fabrication efficiency and reducing fabrication costs thereof, and a method of fabricating the same. A System In Package (SIP) semiconductor device includes a plurality of first and second semiconductor chips each having a predetermined internal circuit and being bonded opposite each other, wherein the first and second semiconductor chips include, respectively, trenches formed in the centers thereof to have a predetermined depth. First and second metal electrodes are formed in inner bottom surfaces of the respective trenches to apply current to the respective internal circuits of the first and second semiconductor chips. A liquid-phase conductive material fills in a predetermined volume of the trenches for selective conduction of the first and second metal electrodes. A plurality of bonding portions formed in surfaces of the first and second semiconductor chips to correspond to each other for coupling of the first and second semiconductor chips. | 01-22-2009 |
20090020887 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - In a semiconductor apparatus in which plural semiconductor elements are stacked, metal wires whose one ends are connected to electrode terminals of the semiconductor elements are extended to the side surfaces of the semiconductor elements in an abutment state and the metal wires extended to the side surfaces of the semiconductor elements are bonded to a side surface wiring formed on side surfaces of the semiconductor elements by a conductive paste containing conductive particles. | 01-22-2009 |
20090020888 | CIRCUIT MODULE AND ELECTRICAL COMPONENT - In an electrical component including a solid-state circuit portion and a substrate connecting portion, the solid-state circuit portion includes: a supporting surface faced to and supported by the substrate connecting portion; and an opposing surface which is widened outside the supporting surface and which has an area enough to be opposed to another solid-state circuit portion. This structure makes it possible to arrange, on a circuit board, a plurality of the electrical components in a staggered manner in a height direction. | 01-22-2009 |
20090020889 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A plurality of quadrilateral-shaped semiconductor elements are stacked on the one surface of a circuit substrate. A side surface wiring for making electrical connection between each of the electrode terminals of the semiconductor elements and a pad formed on the circuit substrate is formed by applying a conductive paste containing conductive particles. A metal wire whose one end is connected to the electrode terminal is extended along a tapered surface formed by cutting off an edge of the electrode terminal surface on which the electrode terminal is formed among edges formed along each of the sides of the semiconductor element. At least a part of the metal wire extended from each of the electrode terminals of the semiconductor elements to the tapered surface is electrically connected to the side surface wiring. | 01-22-2009 |
20090026628 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES - A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. A plurality of metal lines is deposited on the top of the first chip, and the metal lines are isolated from circuitry in the first chip. Wire bonds connect pads on the second chip to metal lines on the first chip. Additional wired bonds connect the metal lines on the first chip to terminals on the substrate. Conductive through-silicon vias or solder bumps may replace the wire bonds, and additional chips may be included in the package. | 01-29-2009 |
20090026629 | SEMICONDUCTOR PACKAGE HAVING A STACKED WAFER LEVEL PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region. | 01-29-2009 |
20090026630 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention provides a semiconductor device capable of preventing chip cracks in a manufacturing process as much as possible, wherein the semiconductor device includes: a substrate main body provided with an inner surface internal to the semiconductor device and an outer surface external to the semiconductor device opposed to each other; an external wiring pattern having a pattern for non-external terminals covered with an insulating material and a pattern for external terminals electrically conductive to the outside formed at least on the outer surface of the substrate main body using a conductive material and electrically connected to each other; an insulating film for covering the pattern for non-external terminals of the external wiring pattern; a metal-plated layer adapted to constitute external terminals in conjunction with the pattern for external terminals and formed on the pattern for external terminals of the external wiring pattern, so as to reduce or eliminate a difference in step with respect to the insulating film; a semiconductor chip mounted on the inner surface of the substrate main body; and a molding resin for molding the inner surface of the substrate main body along with the semiconductor chip. | 01-29-2009 |
20090026631 | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board - An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device ( | 01-29-2009 |
20090026632 | CHIP-TO-CHIP PACKAGE AND PROCESS THEREOF - A wafer treating method for making adhesive chips is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform an adhesive film having B-stage property which has a glass transition temperature between −40 and 175 degree C., for example. After positioning the wafer, the wafer is singulated to form a plurality of chips with adhesive for chip-to-chip stacking, chip-to-substrate or chip-to-lead frame attaching. | 01-29-2009 |
20090032969 | Arrangement of Integrated Circuit Dice and Method for Fabricating Same - An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess. | 02-05-2009 |
20090032970 | STACKING OF INTEGRATED CIRCUITS USING GLASSY METAL BONDING - Techniques associated with stacking integrated circuits using glassy metal bonding are generally described. In one example, an apparatus includes a first integrated circuit having one or more bonding pads and a second integrated circuit having one or more bonding pads, the second integrated circuit being electrically and mechanically coupled with the first integrated circuit by one or more joints formed between the one or more bonding pads of the first and second integrated circuit using a bulk metallic glass bonding material, wherein the bulk metallic glass material provides a low temperature and low pressure bonding solution to reduce delamination or wherein the bulk metallic glass provides reduced intermetallic compound to increase joint reliability, or suitable combinations thereof. | 02-05-2009 |
20090032971 | Die Stacking Apparatus and Method - Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die. | 02-05-2009 |
20090032972 | SEMICONDUCTOR DEVICE - A stacked-type semiconductor device includes a plurality of semiconductor elements stacked on a wiring board. Electrode pads of these semiconductor elements are electrically connected to connection pads of the wiring board via metal wires respectively. The long-looped metal wires connected to the upper semiconductor element are fixed by a wire fixing resin portion to the short-looped metal wires connected to the lower semiconductor element. The wire fixing resin portion is filled at least between the metal wires. The stacked semiconductor elements are sealed by a sealing resin layer together with the metal wires. | 02-05-2009 |
20090032973 | Semiconductor stack package having wiring extension part which has hole for wiring - A semiconductor stack package includes a first printed wiring board; a plurality of semiconductor chips stacked on the first printed wiring board, wherein among the semiconductor chips, the uppermost semiconductor chip has an electrode pad for providing power supply, a ground pad for providing grounding, and a signal pad for signal transmission in a center area on the upper surface of the chip; connection lands formed on the first printed wiring board on the outside of the stacked semiconductor chips; a wiring extension part which is formed on the uppermost semiconductor chip, and has wiring circuits extending from the center to the periphery thereof, wherein at least one of the electrode pad and the ground pad is electrically connected to one end of one of the wiring circuits; and a wire for connecting the other end of the relevant wiring circuit of the wiring extension part and one of the connection lands on the first printed wiring board. | 02-05-2009 |
20090039523 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 02-12-2009 |
20090039524 | METHODS AND APPARATUS TO SUPPORT AN OVERHANGING REGION OF A STACKED DIE - Methods and apparatus to support an overhanging region of stacked die are disclosed. A disclosed method comprises bonding a first die onto a substrate, placing a support element on the substrate; and bonding a second die onto the first die, wherein the second die overhangs at least one edge of the first die and the support element is positioned to limit bending of the second die. | 02-12-2009 |
20090039525 | Method of Welding Together at Least Two Stacked Members - In this soldering method, a laser is directed onto an end face of the stack in such a manner that the laser heats the stack. At least one parameter of the laser is adjusted to a value that is the image by means of a mathematical model of at least one thermal characteristic of the stack. The parameter of the laser is a parameter selected from an irradiation duration, a surface area of the end face of the stack that is irradiated by the laser, and an irradiating power of the laser. | 02-12-2009 |
20090039526 | PACKAGE AND THE METHOD FOR MAKING THE SAME, AND A STACKED PACKAGE - The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement. | 02-12-2009 |
20090039527 | Sensor-type package and method for fabricating the same - A sensor-type package and a method for fabricating the same are provided. A wafer having a plurality of semiconductor chips is provided, wherein a plurality of holes are formed on a first surface of each of the semiconductor chips, and a plurality of metallic pillars formed in the holes and a plurality of bond pads connected to the metallic pillars form through silicon vias (TSVs). A groove is formed on a second surface of each of the semiconductor chips to expose the metallic pillars. A plurality of sensor chips having TSVs are stacked in the grooves of the semiconductor chips and electrically connected to the exposed metallic pillars. A transparent cover is mounted onto the second surfaces of the semiconductor chips to cover the grooves. A plurality of conductive components are implanted on the bond pads of the semiconductor chips. The wafer is cut along borders among the semiconductor chips. | 02-12-2009 |
20090039528 | Wafer level stacked packages with individual chip selection - A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads. | 02-12-2009 |
20090045523 | Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking - A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking. | 02-19-2009 |
20090045524 | Microelectronic package - A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips. | 02-19-2009 |
20090045525 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element is provided with electrode pads which are arranged on a front surface of an element main body, an insulating protection film which covers the front surface of the element main body excepting its outer peripheral area while exposing the electrode pads, and an insulating adhesive layer which is formed to cover a back surface, a sidewall surface and a corner between the front surface and the sidewall surface of the element main body. A plurality of semiconductor elements are stacked on a circuit substrate. The semiconductor elements are adhered via the insulating adhesive layer. | 02-19-2009 |
20090045526 | Stacked memory without unbalanced temperature distributions - A stacked memory without unbalanced temperature distributions is disclosed. According to one aspect of the invention, a through electrode in each layer is connected one after the other such that regions to be activated in neighboring layers do not overlap in a vertical direction. According to another aspect of the invention, each layer comprises an activation region distribution circuit for outputting an activation signal to, among the regions of the layer, a region having an address different from an address of a region to be activated in a layer adjacent to the layer in question. | 02-19-2009 |
20090045527 | Multi-substrate region-based package and method for fabricating the same - A multi-substrate region-based package and a method for fabricating the same are provided. An active surface of a chip is divided into a plurality of functional regions, and each of the functional regions is electrically connected to a corresponding substrate via bonding wires. Each of the functional regions has a separate system, and the circuit layout thereof is not limited by the substrate or other systems but can be flexibly and independently designed, thereby allowing the package to be made smaller and thinner. Each set of the functional region and its corresponding substrate functions as an independent unit, such that the substrates are not affected by each other, thereby providing good compatibility, improved reliability and reduced packaging area. | 02-19-2009 |
20090051043 | DIE STACKING IN MULTI-DIE STACKS USING DIE SUPPORT MECHANISMS - Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die. | 02-26-2009 |
20090051044 | Wafer-level packaged structure and method for making the same - A wafer-level packaging method is shown below: providing an un-cut wafer having a front side and a back side. A plurality of cutting lines is formed on the front side of the wafer so as to define the positions of each chip module such as a wireless module. The next step is providing an extendible film attached onto the back side of the wafer. Next is dicing the wafer along the cutting line to separate each chip module and expending the extendible film so that a gap is formed between each chip module. At last, filling a packaging compound onto the front side and the lateral side of the chip module produces a packaged structure. As mentioned above, the structure is employed for protecting the external surface of the chip. | 02-26-2009 |
20090051045 | Semiconductor package apparatus - A semiconductor package apparatus comprises: at least one semiconductor chip; and a circuit board on which the semiconductor chip is installed, wherein at least one conductive plane for improving power and/or ground characteristics is positioned on a side of the semiconductor chip. In this manner, fabrication cost for the semiconductor package apparatus can be mitigated, and power and/or ground characteristics can be improved so as to readily control impedance of signal lines. As a result, reliability of the operation of the semiconductor package apparatus can be improved, and noise and malfunction can be prevented. | 02-26-2009 |
20090051046 | Semiconductor device and manufacturing method for the same - A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained. | 02-26-2009 |
20090057914 | MULTIPLE CHIP SEMICONDUCTOR DEVICE - A semiconductor device has first and second semiconductor chips comprising electronic circuit elements located at an inner part of the chip and first connection terminals located on an upper surface of the inner part of the chip. One of the chips has second connection terminals located at a peripheral part of the chip. The first and second semiconductor chips are mounted one on top of the other to form the device connected together by the first connection terminals of the first and second semiconductor chips, and wherein the second connection terminals of the first semiconductor chip provide external connections to the device. The invention enables SoC resources to be increased based on the System-in-Package (SiP) approach by duplication identical chip components into a single package. | 03-05-2009 |
20090057915 | SEMICONDUCTOR DEVICE - The operation stability of a SiP (semiconductor device) using a stacked packaging method for stacking a microcomputer IC chip over a driver IC chip is improved. In the SiP using the stacked packaging method for stacking the microcomputer IC chip over the driver IC chip, circuits sensitive to heat or noise, such as an analog to digital conversion circuit, a digital to analog conversion circuit, a sense amplifier circuit of a memory (RAM or ROM), and a power supply circuit of a microcomputer IC chip are prevented from two-dimensionally overlapping with a driver circuit of the lower-side driver IC chip. Since this can reduce, during the operation, the effect of heat or noise, which the circuits sensitive to heat or noise of the microcomputer IC chip receive from the driver circuit of the lower-side driver IC chip, the operation stability of the SiP (semiconductor device) using the stacked packaging method can be improved. | 03-05-2009 |
20090057916 | SEMICONDUCTOR PACKAGE AND APPARATUS USING THE SAME - A semiconductor package is provided. The semiconductor package comprises a substrate having a top surface and a bottom surface, a first semiconductor chip having a plurality of bonding pad regions electrically connected to the substrate by a plurality of first bonding wires, a spacer tape covering the active surface of the first semiconductor chip excluding the plurality of bonding pad regions, and a second semiconductor chip mounted on the active surface of the first semiconductor chip with the spacer interposed. | 03-05-2009 |
20090057917 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device. The semiconductor device includes: a board, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first front face, a first back face, and first external connection terminals provided on the first front face. The first semiconductor chip is mounted on the board via the first external connection terminals by flip-chip bonding. The second semiconductor chip has a second front face, a second back face, and second external connection terminals. The second semiconductor chip is mounted on the first semiconductor chip. The second front face has a contact region contacting the first back face of the first semiconductor chip. The second external connection terminals are provided on the second front face except the contact region. The second semiconductor chip is mounted on the board via the second external connection terminals by flip-chip bonding. | 03-05-2009 |
20090057918 | STACK-TYPE SEMICONDUCTOR PACKAGE, METHOD OF FORMING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME - A method of forming a stack-type semiconductor package includes preparing a lower printed circuit board including a plurality of interconnections and a plurality of ball lands for connection on an upper surface thereof. One or more first chips, which are electrically connected to the plurality of interconnections and sequentially stacked, are mounted on the lower printed circuit board. A lower molded resin compound is formed on the lower printed circuit board to cover the first chips, and is formed to have via holes exposing the ball lands for connection. An upper chip package, under which solder balls are formed, is aligned so that the solder balls correspond to the via holes of the lower molded resin compound, respectively. The solder balls are reflown to form connection conductors filling the via holes. A stack-type semiconductor package structure and an electronic system including the same are also provided. | 03-05-2009 |
20090057919 | Multiple chips bonded to packaging structure with low noise and multiple selectable functions - The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps. | 03-05-2009 |
20090065948 | Package structure for multiple die stack - A die module and method for assembling such a die module is provided. For example, present embodiments include providing a substrate and coupling a first sub-stack to the substrate, wherein the first sub-stack includes two or more die arranged in a first shingle stack configuration relative to one another such that an upper portion of each die in the first sub-stack is accessible, the first shingle stack configuration having a first skew. Further, present embodiments include stacking a second sub-stack on top of the first sub-stack, wherein the second sub-stack includes two or more die arranged in a second shingle stack configuration relative to one another such that an upper portion of each die in the second sub-stack is accessible, the second shingle stack configuration having a second skew that is different than the first skew. | 03-12-2009 |
20090065949 | Semiconductor package and semiconductor module having the same - A semiconductor package can include a semiconductor chip, an insulating substrate, first bond fingers, and pads. The insulating substrate can be attached to edge portions of the semiconductor chip. The first bond fingers can be arranged on edge portions of an upper surface of the insulating substrate. Further, the first bond fingers can be electrically connected to the semiconductor chip. The pads can be arranged on a central portion of the upper surface of the insulating substrate. Further, the pads can be electrically connected to the first bond fingers. Thus, types of stackable devices that can be mounted on or in the semiconductor package need not be restricted. | 03-12-2009 |
20090065950 | STACK CHIP AND STACK CHIP PACKAGE HAVING THE SAME - Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip. | 03-12-2009 |
20090072412 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE ENCAPSULATION HAVING RECESS - An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess. | 03-19-2009 |
20090072413 | SEMICONDUCTOR DEVICE - A semiconductor device and method is disclosed. One embodiment provides a substrate and a first semiconductor chip applied over the substrate. A first electrically conductive layer is applied over the substrate and the first semiconductor chip. A first electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the first electrically insulating layer. | 03-19-2009 |
20090072414 | BONDING METHOD OF SEMICONDUCTOR AND LAMINATED STRUCTURE FABRICATED THEREBY - A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression. | 03-19-2009 |
20090079088 | SEMICONDUCTOR DEVICE WITH CONDUCTIVE DIE ATTACH MATERIAL - A semiconductor device includes a carrier such as a lead frame, a semiconductor die and an attachment member affixing the semiconductor die to the carrier. The attachment device includes an electrically conductive organic material. | 03-26-2009 |
20090079089 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements. | 03-26-2009 |
20090079090 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips are disclosed. One embodiment provides an array of first semiconductor chips, covering the array of the first semiconductor chips with a mold material, and placing an array of second semiconductor chips over the array of the first semiconductor chips. The thicknesses of the second semiconductor chips is reduced. The array of the first semiconductor chips are singulated by dividing the mold material. | 03-26-2009 |
20090079091 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER - An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array over the first integrated circuit die; and singulating a base package from the base package substrate sheet and the interposer array by cutting the access opening generally through the center. | 03-26-2009 |
20090079092 | Stacked Dual-Die Packages, Methods of Making, and Systems Incorporating Said Packages - A semiconductor die package. It includes a substrate having a first surface and a second surface, a first semiconductor die having its front surface facing the first surface of the substrate, a conductive adhesive disposed between the first semiconductor die and the first surface of the substrate, and a second semiconductor die located on the first semiconductor die. The front surface of second semiconductor die faces away from the first semiconductor die, and the back surface faces toward the first semiconductor die. A plurality of conductive structures electrically couple regions at the front surface of the second semiconductor die to conductive regions at the first surface of the substrate. | 03-26-2009 |
20090085220 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING - A semiconductor component and a method of manufacturing is disclosed. One embodiment provides a semiconductor chip with a chip pad and a support pad and a substrate with a substrate pad. The support pad is connected by wire bonding to the chip pad and the support pad. | 04-02-2009 |
20090085221 | Multi-host interface controller with USB PHY/analog functions integrated in a single package - In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die. | 04-02-2009 |
20090085222 | ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF - There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed. | 04-02-2009 |
20090085223 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements. | 04-02-2009 |
20090085224 | STACK-TYPE SEMICONDUCTOR PACKAGE - Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced. | 04-02-2009 |
20090085225 | Semiconductor packages having interposers, electronic products employing the same, and methods of manufacturing the same - A semiconductor package and methods for manufacturing the same are provided. The semiconductor package includes a substrate, first and second semiconductor chips stacked on the substrate. An interposer is disposed between the first and second semiconductor chips. The interposer has a non-planar top surface. | 04-02-2009 |
20090091041 | STACKED TYPE CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A stacked type chip package structure including a package structure, a corresponding substrate, and a number of second bumps is provided. The package structure includes a first chip, a second chip, a number of first bumps, and a first underfill. The first chip is disposed above the second chip. The first bumps are disposed between the first chip and the second chip for electrically connecting the first chip and the second chip. The first underfill is used to fill between the first chip and the second chip and encapsulates the first bumps. The package structure is disposed above the corresponding substrate in a reverse manner, such that the first chip is disposed between the second chip and the corresponding substrate. The second bumps are disposed between the second chip and the corresponding substrate, such that the second chip is electrically connected to the corresponding substrate through the second bumps. | 04-09-2009 |
20090091042 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE HAVING RELIEVED ACTIVE REGION - An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the shaped cross-section of the relief region. | 04-09-2009 |
20090091043 | Die offset die to die bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate. | 04-09-2009 |
20090096110 | METHOD FOR MANUFACTURING A STACKED SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE - A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate. | 04-16-2009 |
20090096111 | Semiconductor device and method of manufacturing the same - In a semiconductor device, a first semiconductor chip is stacked on a wiring substrate and has first electrode pads disposed at predetermined positions on an upper surface thereof. A second semiconductor chip is stacked on the first semiconductor chip through an insulating member in an offset manner so that the first electrode pads are exposed. Support members support a back surface of a protruding portion of the second semiconductor chip through the insulating member. | 04-16-2009 |
20090096112 | INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM - An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted. | 04-16-2009 |
20090102060 | Wafer Level Stacked Die Packaging - A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad. | 04-23-2009 |
20090102061 | Self-Aligned Wafer Level Integration System - A polymer-based, self-aligned wafer-level heterogeneous integration system, SAWLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. | 04-23-2009 |
20090108467 | DEVICE WITH A PLURALITY OF SEMICONDUCTOR CHIPS - A device with a plurality of semiconductor chips is disclosed. One embodiment provides a substrate. A first semiconductor chip is mounted over the substrate. A second semiconductor chip is mounted over the first semiconductor chip. A first electrically conducting element electrically couples the second semiconductor chip to the substrate and a mold material covers the first electrically conducting element only partially. | 04-30-2009 |
20090108468 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A thorough portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meets. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed int he recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode. | 04-30-2009 |
20090108469 | CHIP STACK PACKAGE - A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities. | 04-30-2009 |
20090108470 | SEMICONDUCTOR DEVICE - A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it. | 04-30-2009 |
20090115069 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip package having a molding layer is provided. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer. The semiconductor chip comprises a backside surface, side surfaces, and an active surface having a plurality of chip pads disposed thereon. The molding layer substantially covers the backside surface, the side surfaces, and the active surface of the semiconductor chip and defines at least one opening exposing a portion of the backside surface of the semiconductor chip. A multi-chip package including the semiconductor chip package and a method of manufacturing the semiconductor chip package are also provided. | 05-07-2009 |
20090115070 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device includes a semiconductor chip | 05-07-2009 |
20090121361 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device has a first semiconductor chip | 05-14-2009 |
20090127715 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSION - A mountable integrated circuit package system includes: mounting a first integrated circuit device over a carrier; mounting a second integrated circuit device over the first integrated circuit device includes: attaching the second integrated circuit device to a first substrate side of a substrate, and connecting a first electrical interconnect between the second integrated circuit device and a second substrate side of the substrate through an opening in the substrate. The mountable integrated circuit package system further including: forming a package encapsulation over the first integrated circuit device and the carrier with the substrate partially exposed. | 05-21-2009 |
20090127716 | INTEGRATED CIRCUIT CHIP COMPONENT, MULTI-CHIP MODULE, THEIR INTEGRATION STRUCTURE, AND THEIR FABRICATION METHOD - A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers. | 05-21-2009 |
20090127717 | Semiconductor module - A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die. | 05-21-2009 |
20090134527 | STRUCTURE OF THREE-DIMENSIONAL STACKED DICE WITH VERTICAL ELECTRICAL SELF-INTERCONNECTIONS AND METHOD FOR MANUFACTURING THE SAME - This invention provides a structure of three-dimensional stacked dice with vertical electrical self-interconnections and a method for manufacturing the same. A respective electrical conductive layer is formed in a buried layer of each of the stacked dice, and being extended and exposed to a sidewall of the respective die. An electroless plating process is performed to deposit metal on exposed portions of the respective electrical conductive layers. The metal isotropically grows along the sidewalls of the stacked dice to form a vertical electrical conductive wire connecting the respective conductive layers. The vertical electrical self-interconnections of the three dimensional stacked dice are established. | 05-28-2009 |
20090134528 | SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - Provided are a semiconductor package, an electronic device including the semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes semiconductor chips mounted on a carrier, a first insulating layer sealing the semiconductor chips, first via-holes which are formed in the first insulating layer and expose a portion of each of the semiconductor chips, a first conductive pattern which is filled in the first via-holes and electrically connected to each of the semiconductor chips, and an external terminal which is electrically connected to the first conductive pattern. The semiconductor package is manufactured by performing an encapsulating process and a via-hole process. | 05-28-2009 |
20090140440 | MULTI-CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME - A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty. | 06-04-2009 |
20090146314 | Semiconductor Device - A semiconductor device includes a first wiring board having a semiconductor element connection pad; a semiconductor element connected to the semiconductor element connection pad; and a second wiring board facing the semiconductor element and the first wiring board, the second wiring board being electrically connect to the first wiring board. The semiconductor element includes an electrode configured to electrically connect a first surface of the semiconductor element and a second surface of the semiconductor element to each other. The first surface of the semiconductor element faces the first wiring board. The second surface of the semiconductor element faces the second wiring board. The first wiring board and the second wiring board are electrically connected to each other via the electrode. | 06-11-2009 |
20090146315 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM AND METHOD OF MANUFACTURE THEREOF - An integrated circuit package-on-package stacking system includes: providing a first integrated circuit package, mounting a metalized interposer substrate over the first integrated circuit package, attaching a stiffener integrated with the metalized interposer substrate and having dimensions within package extents, and attaching a second integrated circuit package on the metalized interposer substrate adjacent the stiffener. | 06-11-2009 |
20090152738 | INTEGRATED CIRCUIT PACKAGE HAVING BOTTOM-SIDE STIFFENER - Embodiments of a bottom-side stiffening element are disclosed. The stiffening element may be disposed between an integrated circuit package and an underlying circuit board. In some embodiments, the stiffening element is attached to the underlying circuit board. Other embodiments are described and claimed. | 06-18-2009 |
20090160065 | Reconstituted Wafer Level Stacking - A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique. | 06-25-2009 |
20090160066 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND FABRICATION METHOD THEREOF - Semiconductor elements and methods for fabricating semiconductor elements that allow semiconductor elements having the same function to utilize different packaging methods. An exemplary semiconductor element includes a first semiconductor element portion, including an internal circuit, electrodes electrically connected to the internal circuit, and a first insulating layer covering the internal circuit while exposing the electrodes; and a second semiconductor element portion electrically connected to the electrodes and formed on the first insulating layer, the second semiconductor element portion including a wiring layer having a first pad and a second pad, and a second insulating layer configured to cover either one of the first pad or the second pad while exposing the other one of the first pad and the second pad. | 06-25-2009 |
20090166885 | INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS - An integrated circuit package system comprising: providing an integrated circuit die; forming a top paddle over the integrated circuit die wherein the top paddle has planar dimensions smaller than planar dimensions of the integrated circuit die; forming leads adjacent the top paddle; attaching first connectors to the integrated circuit die and the top paddle; attaching second connectors to the integrated circuit die and the leads; and forming an encapsulant over the first connectors, the second connectors, the integrated circuit die, and the top paddle. | 07-02-2009 |
20090166886 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION - A mountable integrated circuit package system comprising: mounting a first integrated circuit device over a package carrier; mounting an interposer including a central aperture over the package carrier, an intra-stack interconnect connected between the interposer and the package carrier, and the first integrated circuit device within the central aperture; and forming an intra-stack encapsulation over the package carrier and surrounding the interposer. | 07-02-2009 |
20090166887 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 07-02-2009 |
20090166888 | 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die ( | 07-02-2009 |
20090166889 | PACKAGED INTEGRATED CIRCUITS HAVING SURFACE MOUNT DEVICES AND METHODS TO FORM PACKAGED INTEGRATED CIRCUITS - Packaged integrated circuits having surface mount devices and methods to form the same are disclosed. A disclosed method comprises attaching an integrated circuit to a first side of a substrate, forming one or more first conductive elements on the substrate, attaching a surface mount device to a second side of the substrate via the first conductive elements, forming one or more second conductive elements on the second side of the substrate. | 07-02-2009 |
20090174081 | COMBINATION SUBSTRATE - A combination substrate includes a first substrate having multiple wiring board mounting pads for installing a printed wiring board and multiple connection pads on the opposite side of the wiring board mounting pads, a second substrate having multiple package substrate mounting pads for loading one or more package substrates and multiple connection pads on the opposite side of the package substrate mounting pads, a resin component filling a space between the first substrate and the second substrate, and multiple component loading pads positioned to load an electronic component between the first substrate and the second substrate and formed on one of the first substrate and the second substrate. The connection pads of the second substrate are electrically connected to the connection pads of the first substrate. | 07-09-2009 |
20090174082 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 07-09-2009 |
20090184430 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE INCLUDING SEMICONDUCTOR DEVICES - Semiconductor device | 07-23-2009 |
20090189291 | MULTI-CHIP MODULE - A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying over the front side of the first semiconductor chip. The second metal structure includes multiple external contact elements attached over the front side of the second semiconductor chip. At least two of the multiple external contact elements are electrically connected to the front side of the second semiconductor chip. | 07-30-2009 |
20090189292 | Integrated Circuit, Semiconductor Module and Method for Manufacturing a Semiconductor Module - Embodiments of the invention relate to a semiconductor, a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, an integrated circuit includes a plurality of connection pads on at least one side of the integrated circuit, which connection pads can be coupled electrically conductingly by means of a respective bond wire, wherein in at least an edge area on the side of the integrated circuit, on which the connection pads are arranged, a support frame portion is arranged which is configured such that bond wires adjacent to each other can be supported on the support frame portion at a distance from each other. | 07-30-2009 |
20090189293 | Semiconductor device - A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device. | 07-30-2009 |
20090189294 | LARGE AREA INTEGRATION OF QUARTZ RESONATORS WITH ELECTRONICS - Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration of arrays of quartz devices of different frequencies with the same electronics. | 07-30-2009 |
20090206492 | Semiconductor device - A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced. | 08-20-2009 |
20090212442 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PENETRABLE FILM ADHESIVE - An integrated circuit package system including: providing a wire bonded die with an active side and a bond wire connected thereto; forming a penetrable film adhesive on the active side and partially encapsulating the bond wire; mounting an interposer, having a first functional side facing up away from the wire bonded die and a second functional side facing down toward the wire bonded die and having exposed conductors, over the wire bonded die; providing a substrate and connecting the first functional side by the exposed conductor with an electrical interconnect to the substrate; and encapsulating the wire bonded die, and the penetrable film adhesive with an encapsulation. | 08-27-2009 |
20090218700 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 09-03-2009 |
20090230564 | CHIP STRUCTURE AND STACKED CHIP PACKAGE AS WELL AS METHOD FOR MANUFACTURING CHIP STRUCTURES - A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals. | 09-17-2009 |
20090230565 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip. | 09-17-2009 |
20090236751 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE FOR DIE OVERHANG - An integrated circuit package system including: providing a substrate having a support mounted thereover; mounting an integrated circuit die above the substrate; mounting a wire-bonded die offset above the integrated circuit die creating an overhang supported by the support; connecting the wire-bonded die to the substrate with bond wires; and encapsulating the integrated circuit die, the wire-bonded die and the bond wires with an encapsulation. | 09-24-2009 |
20090236752 | PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS - A package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates. | 09-24-2009 |
20090236753 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES - An integrated circuit package system includes: providing a lower interposer substrate with lower exposed conductors; attaching a die over the lower interposer substrate; applying a stack encapsulant over the die and the lower interposer substrate having the lower exposed conductors partially exposed adjacent the stack encapsulant; and attaching an upper interposer substrate having upper exposed conductors over the stack encapsulant and with the upper exposed conductors substantially exposed. | 09-24-2009 |
20090236754 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING MODULE - An integrated circuit package system includes: providing a module substrate having dimension predetermined for attachment adjacent a device; attaching a module die adjacent the module substrate; and applying a module molding material cantilevered from the module substrate and over the module die. | 09-24-2009 |
20090236755 | CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface. | 09-24-2009 |
20090250822 | MULTI-CHIP STACK PACKAGE - A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip. | 10-08-2009 |
20090256267 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH CENTRAL BOND WIRES - An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base substrate partially covering the central opening; attaching external conductive interconnections to a base bottom surface of the base substrate; and molding an encapsulant leaving the external conductive interconnections partially exposed. | 10-15-2009 |
20090261480 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME - An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a first field of the floor of the blind hole, and may also promote wetting of a solder material of the solder connection. Wetting may be impeded on a second field of the floor of the blind hole. The second contact pad may be arranged above a surface of a further substrate, wherein the surface of the further substrate may be oriented perpendicularly to the floor of the blind hole in the substrate. | 10-22-2009 |
20090267238 | BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CIRCUITS - A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers. | 10-29-2009 |
20090273094 | INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM - An integrated circuit package on package system including: forming a first substrate assembly; forming a second substrate, having an auxiliary access port, supported by the first substrate assembly; exposing an integrated circuit die through the auxiliary access port; and coupling an external integrated circuit on the second substrate. | 11-05-2009 |
20090273095 | Rectangular-Shaped Controlled Collapse Chip Connection - A rectangular-shaped controlled collapse chip connection (C | 11-05-2009 |
20090273096 | High Density Memory Device Manufacturing Using Isolated Step Pads - An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding wires that extend up the stack between the electrically isolated step pads. A memory devices includes stacked memory IC die, wherein “shared” signal transmission paths are formed by associated bonding wires that link corresponding contact pads of each memory die, and dedicated select/control signals are transmitted to each memory die by separate transmission paths formed in part by associated electrically isolated step pads. Substrate space overhung by the stack is used for passive components and IC dies. Memory controller die may be mounted on the stack and connected by dedicated transmission paths utilizing the electrically isolated step pads. | 11-05-2009 |
20090278262 | Multi-chip package including component supporting die overhang and system including same - A microelectronic package and a system including the package. The package includes: a substrate; a stack of dice electrically and mechanically bonded to the substrate, the stack including a second level die and a first level die between the substrate and the second level die, the second level die defining an overhang; and a component disposed between the substrate and the overhang of the second level die and adapted to support the overhang on the substrate. | 11-12-2009 |
20090283916 | CHIP STRUCTURE AND METHOD OF REWORKING CHIP - A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip has a defect. The second module of the second chip has a defect. The first module having a defect of the first chip is opened with the second module of the first chip, and the second module having a defect of the second chip is opened with the first module of the second chip. The first and second chips are stacked, and the second module of the first chip is electrically connects with the first module of the second chip. | 11-19-2009 |
20090283917 | SYSTEMS AND METHODS FOR VERTICAL STACKED SEMICONDUCTOR DEVICES - Systems and methods fabricate a vertically stacked multi-chip semiconductor device assembly. An exemplary assembly is fabricated by forming a first semiconductor device in a first semiconductor device layer with a first connector located at a first surface of the first semiconductor device layer; forming a second semiconductor device in a second semiconductor device layer with a second connector located at an interior surface of the second semiconductor device layer; forming a via in the first semiconductor device layer extending from the first surface to an opposing second surface of the first semiconductor device layer corresponding to the location of the second connector; and joining the second surface of the first semiconductor device layer and the interior surface of the second semiconductor device layer, wherein the via at the second surface of the first semiconductor device layer is coupled to the second connector of the second semiconductor device. | 11-19-2009 |
20090283918 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE - A semiconductor chip package structure is described. The semiconductor chip package structure comprises a first chip, which is operated through a first power connection, having a central region and a marginal region. The first chip comprises a plurality of first and second power bonding pads disposed in a marginal region on the top of the first chip. A first power ring and a second power ring are disposed on the first chip, wherein the first and second power rings are respectively electrically connected to the first and second power bonding pads. A second chip, which is operated through a second power connection, is mounted on the central region of the first chip, wherein the second chip comprises a plurality of power bonding pads thereon. A plurality of second bonding wires are electrically connected to the power bonding pads and the second power bonding pads, respectively. | 11-19-2009 |
20090294990 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 12-03-2009 |
20090302483 | STACKED DIE PACKAGE - The invention provides a stacked die package. The package includes a lead frame having a plurality of the leads and a stack of dice disposed thereon, in which the upper die may be electrically connected to the leads via at least one transit area on the lower die to transfer a power signal or a ground signal. | 12-10-2009 |
20090302484 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die. | 12-10-2009 |
20090309235 | Method and Apparatus for Wafer Level Integration Using Tapered Vias - A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer. | 12-17-2009 |
20090309236 | Package on Package Structure with thin film Interposing Layer - The invention relates to microelectronic semiconductor device assemblies having vertically stacked semiconductor device layers. In a disclosed example of a preferred embodiment, a semiconductor device includes a base substrate, an interposing layer, and a second semiconductor device. The interposing layer features a thin insulating film with numerous electrical contacts on its surfaces for electrically coupling with electrical contacts on the adjacent layers. The interposing layer further includes electrical contacts for coupling with one or more non-adjacent layers. Particular examples of preferred embodiments of the invention disclose the use of polyimide film for the interposing layer material and metal studs for non-adjacent layer contacts. | 12-17-2009 |
20090309237 | SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS - A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips. A first die is attached to the die attach paddle. The die is wire bonded to the first plurality of leads and the second plurality of leads. The die is encapsulated. | 12-17-2009 |
20090315189 | Layered chip package and method of manufacturing same - A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes. | 12-24-2009 |
20090321947 | SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. | 12-31-2009 |
20090321948 | METHOD FOR STACKING DEVICES - A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process. | 12-31-2009 |
20090321949 | BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20090321950 | STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING - A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication. | 12-31-2009 |
20090321951 | STACKED WIRE BONDED SEMICONDUCTOR PACKAGE WITH LOW PROFILE BOND LINE - A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes. | 12-31-2009 |
20090321952 | WIRE ON WIRE STITCH BONDING IN A SEMICONDUCTOR DEVICE - A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first semiconductor die may be electrically coupled to the substrate with a plurality of stitches in a forward ball bonding process. The second semiconductor die may in turn be electrically coupled to the first semiconductor die using a second set of stitches bonded between the die bond pads of the first and second semiconductor die. The second set of stitches may each include a lead end having a stitch ball that is bonded to the bond pads of the second semiconductor die. The tail end of each stitch in the second set of stitches may be wedge bonded directly to lead end of a stitch in the first set of stitches. | 12-31-2009 |
20090321953 | CIRCUIT SUBSTRATE HAVING CIRCUIT WIRE FORMED OF CONDUCTIVE POLARIZATION PARTICLES, METHOD OF MANUFACTURING THE CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE CIRCUIT WIRE - A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit. | 12-31-2009 |
20090321954 | STACKED SEMICONDUCTOR PACKAGE ELECTRICALLY CONNECTING SEMICONDUCTOR CHIPS USING OUTER SURFACES THEREOF AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same. The stacked semiconductor package includes a semiconductor chip module having two or more semiconductor chips which are stacked in the shape of steps. Each of the semiconductor chips includes pads located on an upper surface thereof and an inclined side surface connected with the upper surface. Connection patterns are formed in the shape of lines on the inclined side surfaces and the upper surfaces of the semiconductor chips to electrically connect pads of the semiconductor chips. | 12-31-2009 |
20090321955 | Securing integrated circuit dice to substrates - A conductive material may be jet dispensed (i.e. jet sprayed) on an integrated circuit die and a bond pad to form a conformal electrical connection on and between the bond pad and the die. In some cases, a smaller package footprint and/or height may result. | 12-31-2009 |
20090321956 | Layered chip package and method of manufacturing same - A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces. | 12-31-2009 |
20090321957 | Layered chip package and method of manufacturing same - A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals. | 12-31-2009 |
20090321958 | SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF - Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device. | 12-31-2009 |
20090321959 | Chip Arrangement and Method of Manufacturing a Chip Arrangement - A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side. | 12-31-2009 |
20090321960 | SEMICONDUCTOR MEMORY DEVICE - A plurality of semiconductor memory chips are stacked on a first main surface of a wiring board, and an interposer chip is stacked on the plurality of semiconductor chips, and a semiconductor controller chip is stacked on the interposer chip. The plurality of semiconductor memory chips are independently and electrically connected with inner connecting terminals formed on the wiring board, respectively, and independently controlled by the semiconductor controller chip which is electrically connected with another inner connecting terminals formed on the wiring board via the interposer chip. | 12-31-2009 |
20100007032 | FLIP CHIP SEMICONDUCTOR DEVICE HAVING WORKPIECE ADHESION PROMOTER LAYER FOR IMPROVED UNDERFILL ADHESION - A semiconductor device assembly ( | 01-14-2010 |
20100013106 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane. | 01-21-2010 |
20100013107 | INTERCONNECT STRUCTURES FOR INTEGRATION OF MULTI-LAYERED INTEGRATED CIRCUIT DEVICES AND METHODS FOR FORMING THE SAME - Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed. | 01-21-2010 |
20100013108 | STACKED PACKAGES AND MICROELECTRONIC ASSEMBLIES INCORPORATING THE SAME - A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position. | 01-21-2010 |
20100019391 | Semiconductor Device - This application relates to a semiconductor device comprising a first chip comprising a first electrode on a first face of the first chip, and a second chip attached to the first electrode, wherein the second chip comprises a transformer comprising a first winding and a second winding. | 01-28-2010 |
20100019392 | STACKED DIE PACKAGE HAVING REDUCED HEIGHT AND METHOD OF MAKING SAME - A stacked die package is disclosed. The stacked die package includes a wire-bond die that is electrically coupled to other components via one or more wire bonds and a flip-chip die that is coupled to the top surface of the wire-bond die via one or more solder joints. The wire-bond die is formed underneath the flip-chip die. A space defined by the height of the loops of the one or more wire-bonds overlap a space defined by the thickness of one or more solder joints. | 01-28-2010 |
20100019393 | PACKAGING STRUCTURE FOR INTEGRATION OF MICROELECTRONICS AND MEMS DEVICES BY 3D STACKING AND METHOD FOR MANUFACTURING THE SAME - A packaging structure for integration of microelectronics and MEMS devices by 3D stacking is disclosed, which comprises: an ASIC unit, comprising a first substrate and a circuit layout formed on a surface of the first substrate, wherein a cavity is formed on the other surface and at least a through hole is formed on the ASIC unit; and a MEMS unit, comprising a second substrate and a micro sensor disposed on the second substrate; wherein the micro sensor is disposed in the cavity and there is a conductive material filling the through hole so that the ASIC unit and the MEMS unit can be electrically connected to each other when the ASIC unit is attached onto the MEMS unit. | 01-28-2010 |
20100025861 | Hybrid-Level Three-Dimensional Mask-Programmable Read-Only Memory - A hybrid-level three-dimensional mask-programmable read-only memory (HL-3DMPROM) includes a plurality of memory sets. Within each memory set, a plurality of vertically stacked memory levels are interleaved and all adjacent memory levels share address-selection lines; between adjacent memory sets, memory levels are separated by an inter-level dielectric and do not share any address-selection lines. | 02-04-2010 |
20100032847 | METHOD FOR FORMING A PACKAGE-ON-PACKAGE STRUCTURE - A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the first semiconductor package to a surface. The surface is adapted for receiving the first semiconductor package. The method further involves the step of reducing the thickness of the at least one encapsulation layer to a predetermined thickness. The at least one encapsulation layer having a portion distal the surface removed. More specifically, the thickness of the at least one encapsulation layer is reduced for providing a predetermined clearance from a second semiconductor package attachable to the first semiconductor package. The clearance is the distance between the at least one encapsulation layer of the first semiconductor package and a side of the second semiconductor package opposing thereto. | 02-11-2010 |
20100038801 | Corrosion Control of Stacked Integrated Circuits - A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity. | 02-18-2010 |
20100038802 | STACKED SEMICONDUCTOR DEVICE AND METHOD - A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection layer; forming a second passivation layer over the second metal connection layer; forming a second bondpad in the second passivation layer to form a second bondpad layer; forming at least one of a first conductive adhesive layer over the first bondpad layer and a second conductive adhesive layer over the second bondpad layer; and stacking the second wafer on the first wafer by bonding respective faces of the second bondpad layer with the first bondpad layer via the at least one of the first conductive adhesive layer and the second conductive adhesive layer. | 02-18-2010 |
20100044877 | ELECTRONIC DEVICE HAVING A CHIP STACK - An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads. | 02-25-2010 |
20100044878 | INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING CAVITY - An integrated circuit package system includes providing a carrier having a first side and a second side; mounting an integrated circuit over the carrier with the first side facing the integrated circuit; attaching an external interconnect to the second side; and forming an encapsulation over the integrated circuit and around the external interconnect with the external interconnect exposed from the encapsulation and with the encapsulation and the second side forming a cavity. | 02-25-2010 |
20100044879 | Layered chip package and method of manufacturing same - A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes. | 02-25-2010 |
20100044880 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes a multilayer wiring substrate having a plurality of inner wiring layers and a semiconductor chip mounted on the multilayer wiring substrate. The multilayer wiring substrate has a groove formed in the bottom surface. The groove does not reach the lowermost of the inner wiring layers. | 02-25-2010 |
20100044881 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes: a first semiconductor element; a second semiconductor element mounted on an upper surface of the first semiconductor element via an adhesive layer; a mold resin body for overmolding the first semiconductor element and the second semiconductor element; and a first spherical filler having a diameter smaller than an average thickness of the adhesive layer and a second spherical filler having a diameter larger than the average thickness of the adhesive layer, the first or second spherical filler being dispersed in the mold resin body. The mold resin body does not contain a spherical filler which has a diameter substantially equal to the average thickness of the adhesive layer. | 02-25-2010 |
20100052186 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at one side or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications. | 03-04-2010 |
20100052187 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns. | 03-04-2010 |
20100059897 | INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate. | 03-11-2010 |
20100059898 | SIGNAL DELIVERY IN STACKED DEVICE - Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice. | 03-11-2010 |
20100072630 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE SEGMENT SPACER - An integrated circuit package system includes attaching an adhesive segment spacer to an interposer assembly; mounting an integrated circuit over a carrier; mounting the interposer assembly over the integrated circuit with the adhesive segment spacer exposing an inner region of the integrated circuit and covering a periphery of the integrated circuit; and forming an encapsulation over the integrated circuit, the interposer assembly, and the adhesive segment spacer with the interposer assembly exposed with a recess in the encapsulation. | 03-25-2010 |
20100078828 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE - An integrated circuit package system includes: providing a mountable structure having a contact pad and an inner pad; mounting an integrated circuit device having a linear through channel over the mountable structure with the linear through channel traversing between an integrated circuit device first side and an integrated circuit device second side; and connecting the linear through channel exposed on the integrated circuit device second side to the inner pad. | 04-01-2010 |
20100078829 | STACKED DEVICE CONDUCTIVE PATH CONNECTIVITY - Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack. | 04-01-2010 |
20100078830 | ADHESIVE TAPE AND SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an adhesive tape for electrically connecting semiconductor chips in a chip-on-chip type semiconductor device. The adhesive tape comprising: (A) 10 to 50 wt % of film forming resin; (B) 30 to 80 wt % of curable resin; and (C) 1 to 20 wt % of curing agent having flux activity. | 04-01-2010 |
20100084771 | FLEXIBLE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads. | 04-08-2010 |
20100090350 | MULTI-CHIP PACKAGE SYSTEM INCORPORATING AN INTERNAL STACKING MODULE WITH SUPPORT PROTRUSIONS - The present invention provides a multi-chip package system that includes: providing a package substrate; attaching a base semiconductor die to the package substrate; connecting an interconnect between the base semiconductor die and the package substrate; and encapsulating at least portions of the package substrate, the base semiconductor die, and the interconnect with an encapsulant defining a support protrusion adjacent to the interconnect and substantially perpendicular to the package substrate, a cavity bounded by the support protrusion, and a gap linking the cavity to the edge of the encapsulant. | 04-15-2010 |
20100090351 | ELECTRO COMPONENT PACKAGE - An electro component package is disclosed. The electro component package in accordance with an embodiment of the present invention includes a first package substrate having a first chip mounted on an upper surface thereof, the first chip having a through-via formed therein; a second package substrate being separated from the first package substrate and having a second chip mounted on an upper surface thereof; and a connection substrate having one end connected with an upper surface of the first chip and the other end connected with an upper surface of the second chip, the connection substrate electrically connecting the first chip with the second chip. | 04-15-2010 |
20100096761 | SEMICONDUCTOR SUBSTRATE FOR BUILD-UP PACKAGES - The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies. | 04-22-2010 |
20100102457 | Hybrid Semiconductor Chip Package - Various apparatus and method of packaging semiconductor chips are disclosed. In one aspect, a method of manufacturing is provided that includes placing a semiconductor chip package into a mold. The semiconductor chip package includes a substrate that has a side and a first semiconductor chip coupled to the side in spaced apart relation to define a space between the first semiconductor chip and the side. A second semiconductor chip is mounted on the first semiconductor chip. At least one conductor wire is electrically coupled to the second semiconductor chip and the substrate. A molding material is introduced into the mold to flow into the space and establish an underfill and encapsulate the first semiconductor chip and the second semiconductor chip. | 04-29-2010 |
20100117242 | TECHNIQUE FOR PACKAGING MULTIPLE INTEGRATED CIRCUITS - A semiconductor device includes an intermediate substrate having a first surface and a second surface, a first die attached to the first surface of the intermediate substrate. The first die has a first active surface, and the first active surface faces the intermediate substrate. A second die is attached to the second surface of the intermediate substrate, has a second active surface, faces the intermediate substrate, and is coupled to the first die through an electrically conductive material in the intermediate substrate. An organic material encapsulates at least an edge of the intermediate substrate. There is also a method of forming the semiconductor device. | 05-13-2010 |
20100117243 | METHOD AND APPARATUS FOR STACKED DIE PACKAGE WITH INSULATED WIRE BONDS - A semiconductor package has a substrate with a plurality of contact pads. A first semiconductor die is mounted to the substrate. First wire bonds are formed between each of the center-row contact pads of the first semiconductor die and the substrate contact pads. The first wire bonds include an electrically insulative coating formed over the shaft that covers a portion of a surface of a bumped end of the first wire bonds. An epoxy material is deposited over the first semiconductor die. A second semiconductor die is mounted to the epoxy material. Second wire bonds are formed between each of the center-row contact pads of the second semiconductor die and the substrate contact pads. The second wire bonds include an electrically insulative coating formed over the shaft of the second wire bonds that covers a portion of a surface of a bumped end of the second wire bonds. | 05-13-2010 |
20100123257 | Flexible and Stackable Semiconductor Die Packages, Systems Using the Same, and Methods of Making the Same - Disclosed are semiconductor die packages, systems, and methods therefor. An exemplary package comprises a patterned conductive layer having a first surface, a second surface, and a first thickness between its first and second surfaces; a semiconductor die disposed over the first surface of the patterned conductive layer and electrically coupled thereto; a plurality of conductive bodies disposed at the second surface of the patterned conductive layer and electrically coupled thereto, each conductive body having a thickness that is greater than the first thickness; and a body of electrically insulating material disposed on the semiconductor die and a portion of the first surface of the patterned conductive layer. A further embodiment farther comprises a second semiconductor die disposed over the second surface of the patterned conductive layer and electrically coupled thereto. | 05-20-2010 |
20100127407 | Two-sided substrateless multichip module and method of manufacturing same - A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one die. At least one topside interconnect layer is coupled to a top surface of the at least one die. One or more embedded electrical connections is configured to provide an electrical interconnection between the at least one bottomside interconnect layer and the at least one die and/or the at least bottomside interconnect layer and the at least one topside interconnect layer and/or the at least one topside interconnect layer and the at least one die, wherein the at least one bottomside interconnect layer includes one or more electrical contacts on a bottom surface of the multichip module and the at least topside interconnect layer includes one or more electrical contacts on a top surface of the multichip module. | 05-27-2010 |
20100133703 | Semiconductor Chip Laminate and Adhesive Composition for Semiconductor Chip Lamination - A semiconductor chip laminate comprises a plurality of semiconductor chips and an adhesive layer through which the plurality of semiconductor chips are laminated, wherein the adhesive layer is composed of an adhesive composition comprising an acrylic polymer (A); an epoxy resin (B); a thermal curing agent (C); and a certain organic phosphine compound (D) as a thermal curing accelerator, and the content of the organic phosphine compound (D) relative to 100 parts by weight in total of the epoxy resin (B) and the thermal curing agent (C) is 0.001 to 15 parts by weight. | 06-03-2010 |
20100140809 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A PROTRUSION ON AN INNER STACKING MODULE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an inner stacking module die; encapsulating the inner stacking module die with an inner stacking module encapsulation to form an inner stacking module, the inner stacking module encapsulation having an inner stacking module protrusion having a planar protrusion surface; and encapsulating at least part of the inner stacking module encapsulation with an encapsulation having a flat top coplanar with the planar protrusion surface or fully encapsulating the inner stacking module encapsulation. | 06-10-2010 |
20100140810 | CHIP PACKAGE WITH COPLANARITY CONTROLLING FEATURE - A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate. | 06-10-2010 |
20100140811 | SEMICONDUCTOR DIE INTERCONNECT FORMED BY AEROSOL APPLICATION OF ELECTRICALLY CONDUCTIVE MATERIAL - An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet. | 06-10-2010 |
20100148371 | Via First Plus Via Last Technique for IC Interconnects - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias. | 06-17-2010 |
20100148372 | INTEGRATED CIRCUIT PACKAGE HAVING REDUCED INTERCONNECTS - A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package. | 06-17-2010 |
20100155964 | Adhesive Tape, Semiconductor Package and Electronics - An adhesive tape electrically connecting conductive members contains a resin, a solder powder and a curing agent having flux activity, wherein the solder powder and the curing agent having flux activity are contained in the resin. | 06-24-2010 |
20100164124 | METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING - A method and apparatus are provided for multi-chip packaging. A multi-chip package ( | 07-01-2010 |
20100171227 | METHOD OF PRODUCING A VIA IN A RECONSTITUTED SUBSTRATE - A method of producing an electronic connection device, including: a) formation, in a plane of a support substrate, of at least one first contact element and, in a direction approximately perpendicular to the plane, of at least one second contact element having a first end in electrical contact with the first contact element or elements and a second end, the second contact element or elements including one or more metal tracks standing up along the direction perpendicular to the surface of the substrate; b) then positioning at least one electrical or electronic component in contact with the first contact element or elements; and c) encapsulation of the component(s) and of the first and second contact elements, at least the second end or ends of the second contact element or elements being flush with the surface of the encapsulating material. | 07-08-2010 |
20100181686 | Semiconductor Device - A semiconductor device | 07-22-2010 |
20100207277 | SEMICONDUCTOR COMPONENT HAVING A STACK OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING THE SAME - A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another. | 08-19-2010 |
20100207278 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias. | 08-19-2010 |
20100219537 | SEMICONDUCTOR DEVICE - A first semiconductor chip and a second semiconductor chip which form a stack are mounted on a module substrate by deflecting a centre position of the semiconductor chips from the module substrate. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is shorter, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are directly connected with a wire. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is longer, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are combined with the corresponding bonding lead on the module substrate with a wire. | 09-02-2010 |
20100230825 | Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies - In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size. | 09-16-2010 |
20100230826 | INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND PACKAGING METHOD THEREOF - An integrated circuit (IC) package assembly includes a substrate including a plurality of golden fingers, a bonding pad integrally formed with the substrate, an IC fixed on the bonding pad, and a plurality of bonding wires. The IC includes a plurality of connecting pads. A width and a length of the IC are greater than a width and a length of the bonding pad. The plurality of bonding wires electrically connect the plurality of connecting pads to the plurality of golden fingers. | 09-16-2010 |
20100230827 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip that is mounted face-down on a substrate, a second semiconductor chip that is mounted face-up on the first semiconductor chip, and a dummy chip that is interposed between the first semiconductor chip and the second semiconductor chip. The dummy chip is made from a homogenous material comprising silicon or an alloy containing an atomic percentage majority of silicon. | 09-16-2010 |
20100244276 | THREE-DIMENSIONAL ELECTRONICS PACKAGE - An electronics package | 09-30-2010 |
20100252936 | SEMICONDUCTOR MODULE AND PORTABLE DEVICES - A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate. | 10-07-2010 |
20100252937 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SAME - An electronic device includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first electronic component, a first sealing resin, and a first multilayer interconnection structure including a first interconnection pattern directly connected to a first electrode pad of the first electronic component. The second semiconductor device includes a second electronic component, a second sealing resin, and a second multilayer interconnection structure including a second interconnection pattern directly connected to a second electrode pad of the second electronic component. The first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device. The first interconnection pattern and the second interconnection pattern are connected through a through electrode provided through the adhesive layer and the second sealing resin. | 10-07-2010 |
20100258949 | Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly - A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements. | 10-14-2010 |
20100258950 | PACKAGE WITH SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT MOUNTED THEREIN AND METHOD FOR MANUFACTURING SUCH PACKAGE - A multichip package includes a first chip and a second chip coupled with the first chip. The first chip includes a first base with a semiconductor device mounted on one side of the first base, a first electrical connection unit, a first bonding ring surrounding the semiconductor device, a first insulating layer formed on the other side of the first base and a first external bonding portion formed on the first insulating layer. The first external bonding portion is electrically connected to the first electrical connection unit. The second chip includes an integrated circuit corresponding to the semiconductor device, a second electrical connection unit fusing with the first electrical connection unit, and a second bonding ring fusing with the first bonding ring in order to form a hermetic cavity surrounding the semiconductor device, the integrated circuit, the first electrical connection unit and the second electrical connection unit. | 10-14-2010 |
20100258951 | ASSEMBLING SUBSTRATES THAT CAN FORM 3-D STRUCTURES - A system is described that connects the surface of a first substrate to the edge of a second substrate. The surfaces of additional substrates can be placed on the remaining edges of the second substrate to form a 3-D structure. Rigid support substrates can be connected to the first substrate to provide support for the first and additional substrates. The second substrate can be used to carry heat, fluids, electrical power or signals between first and additional substrates besides providing a mechanical support. | 10-14-2010 |
20100264551 | THREE DIMENSIONAL INTEGRATED CIRCUIT INTEGRATION USING DIELECTRIC BONDING FIRST AND THROUGH VIA FORMATION LAST - A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material. | 10-21-2010 |
20100270688 | MULTI-CHIP STACKED PACKAGE - A multi-chip stacked package primarily comprises a chip carrier, a first chip disposed on the chip carrier, a plurality of die-attaching bars, a second chip stacked on the first chip by the adhesion of the die-attaching bars, and a plurality of bonding wires electrically connecting the first chip to the chip carrier. The die-attaching bars are formed on the first chip in a specific pattern and have an adhesive surface away from the first chip for adhering the second chip. The bonding wires have a loop height lower than the adhesive surface in a manner that specific sections of the bonding wires are embedded in the corresponding die-attaching bar from the adhesive surface. Accordingly, the die-attaching bars can modify and fasten the bonding wires in advance to avoid collapse and deformation of the bonding wires during stacking of the second chip and encapsulating processes. | 10-28-2010 |
20100270689 | Semiconductor packages and electronic systems including the same - Provided are semiconductor packages and electronic systems including the same. A substrate is provided. A plurality of semiconductor chips may be stacked the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad. | 10-28-2010 |
20100283160 | Panelized Backside Processing for Thin Semiconductors - A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors. | 11-11-2010 |
20100289156 | SEMICONDUCTOR DEVICE - According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area. | 11-18-2010 |
20100295189 | METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS - A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional. | 11-25-2010 |
20100301496 | Structure and Method for Power Field Effect Transistor - A packaged semiconductor device has a metal plate ( | 12-02-2010 |
20100308473 | METHOD FOR MAKING AN ELECTRICALLY CONDUCTING MECHANICAL INTERCONNECTION MEMBER - A method of fabricating an electrically conductive mechanical interconnection element ( | 12-09-2010 |
20100314780 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers - A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die. | 12-16-2010 |
20100320619 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: attaching a lower integrated circuit, having a first through via, over a substrate with the first through via coupled to the substrate; mounting a pre-formed interposer, having an interposer through via and an integrated passive device, over the lower integrated circuit with the interposer through via coupled to the first through via; attaching an upper integrated circuit, having a second through via, over the pre-formed interposer; and forming an encapsulation over the upper integrated circuit and the pre-formed interposer. | 12-23-2010 |
20100320620 | ADHESIVE FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE USING THE ADHESIVE FILM - An adhesive film for a semiconductor containing an (A) ester (meth)acrylate copolymer and a (B) thermoplastic resin other than the ester (meth)acrylate copolymer, and composed so as to satisfy the following formula (1) for two hours from 10 minutes after starting measurement, in which γ represents an amount of shearing strain produced upon undergoing a shearing stress of 3000 Pa at a frequency of 1 Hz and a temperature of 175° C. on parallel plates of 20 mm in diameter, exhibits superior filling performance in surface unevenness of a substrate through an encapsulating material sealing process, despite that semiconductor chips are stacked in multiple layers in the semiconductor device and hence a wire bonding process imposes a longer thermal history. | 12-23-2010 |
20100320621 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing of an integrated circuit package-in-package system includes: mounting a first integrated circuit device over a substrate; mounting an integrated circuit package system having an inner encapsulation over the first integrated circuit device with a first offset; mounting a second integrated circuit device over the first integrated circuit device and adjacent to the integrated circuit package system; connecting the integrated circuit package system and the substrate; and forming a package encapsulation as a cover for the first integrated circuit device, the integrated circuit package system, and the second integrated circuit device. | 12-23-2010 |
20100327460 | CAPACTIVE CONNECTORS WITH ENHANCED CAPACITIVE COUPLING - A single-chip module (SCM) and a multi-chip module (MCM) that includes at least two instances of the SCM are described. The SCM includes a pad disposed on a substrate. This pad has a top surface that includes a pattern of features. A given feature in the pattern of features has a height that extends above a minimum thickness of the pad, thereby increasing a capacitance associated with the pad relative to a configuration in which the top surface is planar. Furthermore, pads disposed on the two instances of the SCM in the MCM may each have a corresponding pattern of features that increases the capacitive coupling between the pads relative to a configuration in which the top surfaces of either or both of the pads are planar. Note that the pads may be aligned such that features in the patterns of features on these pads are interdigited with each other. | 12-30-2010 |
20100327461 | Electrical interconnect for die stacked in zig-zag configuration - A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate. | 12-30-2010 |
20100327462 | METHODS FOR WAFER-LEVEL PACKAGING OF MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED USING SUCH METHODS - Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other. | 12-30-2010 |
20100327463 | STACKED STRUCTURES AND METHODS OF FABRICATING STACKED STRUCTURES - A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure. | 12-30-2010 |
20100327464 | Layered chip package - A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. | 12-30-2010 |
20110006441 | RESIN VARNISH USED FOR ADHESIVE FILM FOR SEMICONDUCTOR ELEMENT, ADHESIVE FILM FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - The object of the present invention can be achieved by an adhesive film for semiconductor element, including: a (meth) acrylic ester copolymer (A); and a silica (B), wherein the (meth) acrylic ester copolymer (A) has a hydroxyl group and a carboxylic group, or has an epoxy group, and has a weight-average molecular weight of 100,000 to 1,000,000, wherein the silica (B) has mean particle diameter of 1 to 100 nm, and wherein none of a thermosetting resin and a curing agent (C) is contained in non-volatile components, or total contents of the thermosetting resin and the curing agent (C) in the non-volatile components is equal to or lower than 5 wt %. | 01-13-2011 |
20110012270 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system. | 01-20-2011 |
20110024917 | MULTI-DIE PACKAGE - A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die. | 02-03-2011 |
20110024918 | STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements. | 02-03-2011 |
20110031633 | AIR CHANNEL INTERCONNECTS FOR 3-D INTEGRATION - A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure. | 02-10-2011 |
20110031634 | Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die - In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path. | 02-10-2011 |
20110031635 | Stacked Integrated Circuit Device - A device having stacked integrated circuit (IC) chips is provided. The chips and other wires are connected through circuit contacts and notches or apertures. The notches or apertures are filled with a conductive material. Thus, flexibility of circuit layout is achieved with easy fabrication and enhanced reliability. | 02-10-2011 |
20110042829 | IC Interconnect - A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias. | 02-24-2011 |
20110057327 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip. | 03-10-2011 |
20110057328 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed. | 03-10-2011 |
20110062596 | SEMICONDUCTOR CHIP STACKED STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of making a semiconductor chip stacked structure includes dicing a semiconductor wafer into semiconductor chips, the semiconductor chips respectively having a first surface and a second surface opposite thereto, the semiconductor chips having integrated circuits and pads on the first surfaces, arranging the semiconductor chips at intervals on a film having adhesive property, connecting the pads through joining members, sealing with resin the joining members and surfaces of the semiconductor chips excluding the second surfaces to produce a chip sealing structure, dividing the chip sealing structure to produce separate chip sealing structures having ends of the joining members exposed at surfaces thereof, removing the film to expose the second surfaces, stacking the chip sealing structures one over another and connecting the exposed ends of the joining members through a bonding wire to produce a chip stacked structure, and mounting the chip stacked structure on a wiring substrate. | 03-17-2011 |
20110062597 | PACKAGE STRUCTURES - A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die. | 03-17-2011 |
20110062598 | STACKED-DIE PACKAGE INCLUDING SUBSTRATE-GROUND COUPLING - Method and apparatus are provided for semiconductor device packages. In an example, an apparatus can include a first semiconductor device, a ground pad situated on an uppermost portion of the first semiconductor device and configured to electrically couple portions of the first semiconductor device to aground potential, and a second semiconductor device having at least a portion in electrical communication with an uppermost face of the first semiconductor device through a first electrically-conductive adhesive. In an example, the first electrically-conductive adhesive can be electrically coupled to the ground bond pad on the first semiconductor device. | 03-17-2011 |
20110068479 | ASSEMBLY OF MULTI-CHIP MODULES USING SACRIFICIAL FEATURES - A multi-chip module (MCM) is described. This MCM includes two substrates, having facing surfaces, which are mechanically coupled. Disposed on a surface of a first of these substrates, there is a negative feature, which is recessed below this surface. A positive feature in the MCM, which includes an assembly material other than a bulk material in the substrates, at least in part mates with the negative feature. For example, the positive feature may be disposed on the surface of the other substrate. Alternatively, prior to assembly of the MCM, the positive feature may be a separate component from the substrates (such as a micro-sphere). Note that the assembly material has a bulk modulus that is less than a bulk modulus of the material in the substrates. Furthermore, at least a portion of the positive feature may have been sacrificed when the mechanical coupling was established. | 03-24-2011 |
20110068480 | SEMICONDUCTOR DEVICE AND ADHESIVE SHEET - The present invention provides a semiconductor device which comprises a substrate, a first semiconductor chip on a substrate, a second semiconductor chip on the first semiconductor chip, and an adhesive sheet between the first and second semiconductor chips. The second semiconductor chip has a mirrored back surface, and the adhesive sheet contains a metal impurity ion trapping agent. | 03-24-2011 |
20110068481 | PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other. | 03-24-2011 |
20110079923 | Vertically Stackable Dies Having Chip Identifier Structures - A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact. | 04-07-2011 |
20110079924 | Vertically Stackable Dies Having Chip Identifier Structures - A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through vias that are each hard wired to an external electrical contact. | 04-07-2011 |
20110084403 | PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT - Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad. | 04-14-2011 |
20110084404 | Semiconductor device - One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit. | 04-14-2011 |
20110084405 | STACKING SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - In a stacking semiconductor device in which a first-layer and a second-layer semiconductor devices are stacked and bonded with a solder, warpage occurs due to a difference in thermal expansion coefficient of constituent members or a difference in elastic modulus of individual members. Therefore, between the first-layer and the second-layer semiconductor devices are provided an external connection terminal of solder and a thermosetting resin, and the stacking semiconductor device is heated at 150 to 180° C., which are the temperatures of preheating for reflow of the solder, for 30 to 90 seconds. Thereby the warpage of the first-layer semiconductor device is reduced and the thermosetting resin is cured completely in this state. Then, the temperature is raised to a reflow temperature of the solder and solder bonding using the external connection terminal is performed. Thereby, the bonding reliability of a solder-bonded portion of the stacking semiconductor device is considerably improved. | 04-14-2011 |
20110089575 | MULTICHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes at least one semiconductor chip mounted to a circuit board and separated from the circuit board by a predetermined distance. A support located between the circuit board and the first semiconductor chip supports the first semiconductor chip. The support has first and second ends fixed with respect to the circuit board and a center portion between the first and second ends to contact the first semiconductor chip. | 04-21-2011 |
20110089576 | PAD LAYOUT STRUCTURE OF A DRIVER IC CHIP - A pad layout structure of a driver IC chip to be mounted to a liquid crystal display panel. The pad layout structure includes power pad sections placed at respective four corners of the driver IC chip and each having a first power pad for supplying first power to the driver IC chip, a second power pad for supplying second power to the driver IC chip, a third power pad for supplying third power to the driver IC chip and a fourth power pad for supplying fourth power to the driver IC chip. | 04-21-2011 |
20110095440 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 04-28-2011 |
20110108995 | SPIRAL STAIRCASE SHAPED STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads. | 05-12-2011 |
20110115098 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure. | 05-19-2011 |
20110140283 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACKABLE PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base assembly having a cavity and a through conductor adjacent to the cavity; connecting a first device to the base assembly with the first device within the cavity; connecting a second device to the base assembly with the second device within the cavity; and connecting an interposer substrate having an exposed external side over the through conductor with the exposed external side facing away from the through conductor and exposed to ambient. | 06-16-2011 |
20110140284 | OPTOELECTRONIC COMPONENT - An optoelectronic component includes a carrier with a mounting side and having at least one functional element, at least one substrateless optoelectronic semiconductor chip with a top and an opposed bottom and is electrically conductive by way of the top and the bottom, wherein the bottom faces the mounting side and the semiconductor chip is mounted on the mounting side, and at least one structured electrical contact film located on the top. | 06-16-2011 |
20110140285 | Semiconductor Device - A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer. | 06-16-2011 |
20110140286 | MULTILAYER WIRING SUBSTRATE MOUNTED WITH ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - A multilayer wiring substrate mounted with an electronic component includes an electronic component, a core material layer having a first opening for accommodating the electronic component, a resin layer which is formed on one surface of the core material layer and which has a second opening greater than the first opening, a supporting layer which is formed on the other surface of the core material layer and which supports the electronic component, a plurality of connection conductor sections which are provided around the first opening and within the second opening on the one surface of the core material layer, bonding wires for electrically connecting the electronic component to the connection conductor sections, and a sealing resin filled into the first and second openings in order to seal the electronic component and the bonding wires. | 06-16-2011 |
20110147949 | HYBRID INTEGRATED CIRCUIT DEVICE - An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die. | 06-23-2011 |
20110156275 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT AND METHOD FOR MANUFACTURE THEREOF - A method for manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect. | 06-30-2011 |
20110163458 | Method for manufacturing electronic device and electronic device - An electronic device is disclosed which can suppress the formation of voids in a region below an overhanging portion of a first semiconductor device overhanging a support member. The support member is disposed over a package substrate. The first semiconductor device is disposed over the support member and, when seen in plan, at least a part of the first semiconductor device overhangs the support member. A first resin layer fills up a space below the first semiconductor device in at least a part of the overhanging portion of the first semiconductor device around the support member. The first resin layer is in contact with the support member. A second resin layer seals the first semiconductor device and the support member. | 07-07-2011 |
20110163459 | METHOD FOR MANUFACTURING A STACKED SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE - A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate. | 07-07-2011 |
20110180937 | STACKED PACKAGE OF SEMICONDUCTOR DEVICE - Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside. | 07-28-2011 |
20110187005 | Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material - A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die. | 08-04-2011 |
20110221072 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier. | 09-15-2011 |
20110221073 | Layered chip package with wiring on the side surfaces - A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number. | 09-15-2011 |
20110233789 | ADHESIVE-BONDED SUBSTRATES IN A MULTI-CHIP MODULE - A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces. | 09-29-2011 |
20110233790 | Sacrificial Material to Facilitate Thin Die Attach - A sacrificial material applied to a thin die prior to die attach provides stability to the thin die and inhibits warpage of the thin die as heat is applied to the die and substrate during die attach. The sacrificial material may be a material that sublimates at a temperature near the reflow temperature of interconnects on the thin die. A die attach process deposits the sacrificial material on the die, attaches the die to a substrate, and applies a first temperature to reflow the interconnects. At the first temperature, the sacrificial material maintains substantially the same thickness. A second temperature is applied to sublimate the sacrificial material leaving a clean surface for the later packaging processes. Examples of the sacrificial material include polypropylene carbonate and polyethylene carbonate. | 09-29-2011 |
20110233791 | METHOD FOR PERFORMING PARALLEL STOCHASTIC ASSEMBLY - A method of positioning at least 2 chips simultaneously on a substrate by parallel stochastic assembly in a first liquid is disclosed. In one aspect, the chips are directed to target sites on the substrate within the first liquid. The target sites are covered with a second liquid. The second liquid and the first liquid are immiscible. The chips are attracting the first liquid. A predetermined surface is chosen or treated on each chip such that it is selectively attracted by the second liquid and attracting the first liquid. | 09-29-2011 |
20110248410 | STACK PACKAGES USING RECONSTITUTED WAFERS - A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads. | 10-13-2011 |
20110248411 | INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM - An integrated circuit package in package system includes: a base integrated circuit package with a base lead substantially coplanar with a base die paddle and having a portion with a substantially planar base surface; an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface; a package-stacking layer over the base integrated circuit package; and the extended-lead integrated circuit package over the base integrated circuit package including: an end portion of the extended lead, directly on the package-stacking layer, and the extended lead exposed by and extending away from the bottom of the side of an extended-lead encapsulation and bending downwards toward the direction of the package stacking layer with the substantially planar lead-end surface coplanar with the substantially planar base surface. | 10-13-2011 |
20110254175 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads; | 10-20-2011 |
20110260336 | WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized. | 10-27-2011 |
20110260337 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor chip | 10-27-2011 |
20110272824 | Semiconductor Device and Method of Forming Channels in Back Surface of FO-WLCSP for Heat Dissipation - A semiconductor device has semiconductor die mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. A channel is formed in a back surface of the die, either while in wafer form or after mounting to the carrier. The channel corresponds to a specific heat generating area of the die. The channel can be straight or curved or crossing pattern. The carrier is removed. An interconnect structure is formed over the encapsulant and die. The semiconductor die are singulated through the encapsulant. A TIM and heat sink are formed over the channel and encapsulant. Alternatively, a conformal plating layer can be formed over the channel and encapsulant. A conductive via can be formed through the encapsulant, and TSV formed through the die. The die with channels can be mounted over a second semiconductor die which is mounted to the interconnect structure. | 11-10-2011 |
20110272825 | STACKED DIE ASSEMBLY HAVING REDUCED STRESS ELECTRICAL INTERCONNECTS - Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure. | 11-10-2011 |
20110278739 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased. | 11-17-2011 |
20110278740 | SCALABLE TRANSFER-JOIN BONDING LOCK-AND-KEY STRUCTURES - Scalable transfer-join bonding techniques are provided. In one aspect, a transfer-join bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one metal pad embedded in an insulator and at least one via in the insulator over the metal pad. The via has tapered sidewalls. A second bonding structure is provided having at least one copper stud tapered to complement the tapered sidewalls of the via, such that the via and the copper stud fit together like a lock-and-key. The first bonding structure is bonded to the second bonding structure by way of a metal-to-metal bonding between the metal pad and the copper stud. A transfer join bonded structure is also provided. | 11-17-2011 |
20110278741 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 11-17-2011 |
20110291294 | Multi-Chip Package - A multi-chip package may include a first semiconductor package, a second semiconductor package and an interposer chip. The second semiconductor package may be arranged over the first semiconductor package. The interposer chip may be interposed between the first semiconductor package and the second semiconductor package. The interposer chip may have a receiving groove configured to receive the first semiconductor package. Thus, electrical connection reliability between the first semiconductor package and the second semiconductor package may be improved under a condition that the connecting terminals may have small sizes. | 12-01-2011 |
20110291295 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, pluralities of first and second external electrodes formed in two end portions of one surface of the substrate, a first semiconductor chip mounted on the other surface of the substrate, the first semiconductor chip having an electrode pad row formed in one end portion of one surface of the first semiconductor chip and electrically connected to the first external electrodes, the first semiconductor chip being disposed so that the one end portion of the first semiconductor chip is positioned on an end portion on which the first external electrodes of the substrate are formed, and a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip having an electrode pad row formed in one end portion of one surface of the second semiconductor chip and electrically connected to the second external electrode, the second semiconductor chip being disposed so that the one end portion of the second semiconductor chip is positioned on an end portion on which the second external electrodes of the substrate are formed. | 12-01-2011 |
20110291296 | PACKAGE STACKING THROUGH ROTATION - A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second bond windows, and first and second sets of package contacts exposed at diagonally opposite corner regions of the top face, wherein the first and second sets conductively connected to the chip contacts. There is also a microelectronic element adjacent to the bottom face of the dielectric element, as well as bond wires extending through the first and second bond windows to conductively connect the microelectronic element to the chip contacts. | 12-01-2011 |
20110291297 | MICROELECTRONIC PACKAGES HAVING CAVITIES FOR RECEIVING MICROELECTRONIC ELEMENTS - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 12-01-2011 |
20110309525 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE - An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate is provided, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip provided adjacent to the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip. | 12-22-2011 |
20110309526 | Printed Circuit Board And Semiconductor Package Including The Same - A semiconductor package may include a base substrate, a solder resist layer on the base substrate, a first semiconductor chip mounted on the base substrate, and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip may include at least one end portion protruding from the first semiconductor chip. The solder resist layer may include and a recess portion. The recess portion may be formed in the solder resist layer at a position corresponding to the at least one end portion of the second semiconductor chip. | 12-22-2011 |
20110316172 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor package that includes: a wiring board; a first semiconductor chip mounted on the wiring board; a second semiconductor chip mounted on the first semiconductor chip, wherein a size of second semiconductor chip is larger than that of the first semiconductor chip when viewed from a thickness direction of the semiconductor package; an insulating resin provided between the wiring board and the second semiconductor chip and between the wiring board and the first semiconductor chip so as to cover the first semiconductor chip; a base disposed on the wiring board to face a surface of the second semiconductor chip, wherein the insulating resin is provided between the base and the second semiconductor chip so as to cover the base. | 12-29-2011 |
20120001347 | SEMICONDUCTOR PACKAGE HAVING A STACKED STRUCTURE - A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system. | 01-05-2012 |
20120001348 | WAFER STACKED PACKAGE WAVING BERTICAL HEAT EMISSION PATH AND METHOD OF FABRICATING THE SAME - A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips. | 01-05-2012 |
20120013024 | Layered Chip Package and Method of Manufacturing Same - A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip. | 01-19-2012 |
20120013025 | Layered Chip Package and Method of Manufacturing Same - A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip. The plurality of wires include a plurality of common wires and a plurality of layer-dependent wires. In at least one of the layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires. | 01-19-2012 |
20120013026 | STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips. | 01-19-2012 |
20120013027 | SEMICONDUCTOR AND A METHOD OF MANUFACTURING THE SAME - A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips. | 01-19-2012 |
20120013028 | STACKED MICROELECTRONIC PACKAGES HAVING AT LEAST TWO STACKED MICROELECTRONIC ELEMENTS ADJACENT ONE ANOTHER - A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element. | 01-19-2012 |
20120025396 | SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING - A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package. | 02-02-2012 |
20120025397 | Semiconductor Chip Layout - A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays. | 02-02-2012 |
20120025398 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed. | 02-02-2012 |
20120032347 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product. | 02-09-2012 |
20120032348 | THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 02-09-2012 |
20120032349 | METHOD OF FABRICATING STACKED ASSEMBLY INCLUDING PLURALITY OF STACKED MICROELECTRONIC ELEMENTS - A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads. | 02-09-2012 |
20120038059 | STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK - A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond. | 02-16-2012 |
20120038060 | STACKING METHOD AND STACKING CARRIER - A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation. | 02-16-2012 |
20120038061 | SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. | 02-16-2012 |
20120038062 | STACKED SEMICONDUCTOR PACKAGE AND STACKING METHOD THEREOF - A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips. | 02-16-2012 |
20120038063 | REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD - Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer. | 02-16-2012 |
20120038064 | Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die - A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads. | 02-16-2012 |
20120043668 | STACKED SEMICONDUCTOR CHIPS WITH THERMAL MANAGEMENT - A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture. | 02-23-2012 |
20120043669 | STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT CIRCUIT BOARD - A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip. | 02-23-2012 |
20120043670 | Semiconductor Module System Having Stacked Components With Encapsulated Through Wire Interconnects (TWI) - A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire. | 02-23-2012 |
20120043671 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY CARD - A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region. | 02-23-2012 |
20120056333 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion. | 03-08-2012 |
20120056334 | Semiconductor Device and Method of Forming Pre-Molded Substrate to Reduce Warpage During Die Mounting - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting. | 03-08-2012 |
20120056335 | MULTI-CHIP PACKAGE WITH OFFSET DIE STACKING - A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed. | 03-08-2012 |
20120061852 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 03-15-2012 |
20120068361 | STACKED MULTI-DIE PACKAGES WITH IMPEDANCE CONTROL - A microelectronic assembly may include microelectronic devices arranged in a stack and having device contacts exposed at respective front surfaces. Signal conductors having substantial portions extending above the front surface of the respective microelectronic devices connect the device contacts with signal contacts of an underlying interconnection element. A rear surface of a microelectronic device of the stack overlying an adjacent microelectronic device of the stack is spaced a predetermined distance above and extends at least generally parallel to the substantial portions of the signal conductors connected to the adjacent device, such that a desired impedance may be achieved for the signal conductors connected to the adjacent device. | 03-22-2012 |
20120074588 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier. | 03-29-2012 |
20120074589 | CORNER STRUCTURE FOR IC DIE - One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip. | 03-29-2012 |
20120074590 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided. | 03-29-2012 |
20120074591 | THIN WAFER SUPPORT ASSEMBLY - A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that existing handling tools can accommodate transporting and processing the assembly without compromising the profile of the thin target wafer. | 03-29-2012 |
20120074592 | WAFER-LEVEL PACKAGING METHOD USING COMPOSITE MATERIAL AS A BASE - An electronic package that includes a composite material base. In one embodiment the electronic package is an expanded wafer-level package. The composite material base is composed of woven strands and polymer material. In one embodiment the composite material base is composed of woven fiberglass strands and an epoxy material. In various embodiments the package includes an electronic circuitry layer on one or another face of the composite material base. In other embodiments conductive vias connect the circuitry layers, including a redistribution layer. In yet another embodiment an electronic package is mounted on the composite material base and electrically couples to the circuit of the expanded wafer-level package. The package having the composite material base is mechanically stronger and can be made thinner than a package that relies on an encapsulant material for structure, and resists cracking. | 03-29-2012 |
20120074593 | CHIP STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME - A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate. | 03-29-2012 |
20120074594 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprising a support plate, a semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes, a first insulation layer covering the circuit element surface of the semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes, a second insulation layer covering an upper part of the support plate and side parts of the semiconductor element, and wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes. | 03-29-2012 |
20120074595 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate on which a first semiconductor chip is mounted, a second substrate spaced apart from the first substrate and on which a second semiconductor chip is mounted, first pads disposed on the first substrate, second pads disposed on the second substrate to be opposite to the first pads, and connection patterns electrically connecting the opposite first and second pads to each other, respectively. The first pads are disposed asymmetrically with respect to the central axis of the first substrate. | 03-29-2012 |
20120080806 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first package including a first substrate and at least one first semiconductor chip mounted on the first substrate, a redistribution wiring layer provided on the first package and including a connection pad, a bonding pad electrically connected to the connection pad and a dummy bonding pad electrically connected to the bonding pad, a second package stacked on the first package via the redistribution wiring layer and electrically connected to the connection pad of the redistribution wiring layer by a first connection member, a bonding wire electrically connecting the bonding pad to the first substrate, and a dummy bonding wire electrically connecting the dummy bonding pad to the first substrate. | 04-05-2012 |
20120080807 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 04-05-2012 |
20120091595 | Layered Integrated Circuit Apparatus - A device having layered integrated circuit (IC) chips is provided. The chip comprises notches, conductive area, apertures, and routing pool. A conductive material is set in the apertures. The second chip is layered on the first chip. The notches of the second chip are corresponding to the first conducting area of the first chip. A conductive material is also set in the notch between the conductive area of the first chip and the notches of the second chip. Thus, a system is integrated by layering the first chip and the second chip for enhancing flexibility and reliability of circuit layout. | 04-19-2012 |
20120091596 | CHIP-TO-CHIP MULTI-SIGNALING COMMUNICATION SYSTEM WITH COMMON CONDUCTIVE LAYER - A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer. | 04-19-2012 |
20120091597 | STACKED SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE INCLUDING THE STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side. | 04-19-2012 |
20120104631 | SEMICONDUCTOR MODULE - A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die. | 05-03-2012 |
20120112365 | Semiconductor Packages and Methods For Producing The Same - In one embodiment, a semiconductor package includes an isolating container having a recess, which forms an inner membrane portion and an outer rim portion. The rim portion is thicker than the membrane portion. The package includes a semiconductor chip disposed in the recess and a backplane disposed under the membrane portion of the isolating container. | 05-10-2012 |
20120112366 | Power Electronic Module - The invention relates to a power electronic module comprising a plurality of bridge arms mounted in parallel and a plurality of output terminals (BS) connected to the middle points of said bridge arms, characterized in that it comprises at least two semi-conductor chips (P | 05-10-2012 |
20120119385 | Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies - Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly. | 05-17-2012 |
20120119386 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate which includes a first chip area and a second chip area. An insulation film is formed over the substrate. An electrical circuit is formed in the first chip area and is electrically independent from any component in another chip area. The electrical circuit includes an electrical element and an interconnect on the substrate and in the insulation film. Boundary patterns are formed in the insulation film between the first and second chip areas, are electrically independent from the electrical circuit, and have a gap therebetween. One of the boundary patterns surrounds the first chip area. | 05-17-2012 |
20120119387 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 05-17-2012 |
20120126427 | MEMORY DEVICE, LAMINATED SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip. | 05-24-2012 |
20120126428 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate base side and a substrate stack side; mounting an integrated circuit over the substrate stack side; attaching a stack connector to the substrate stack side; forming an encapsulation over the stack connector and the integrated circuit; attaching an external connector to the substrate base side; attaching an adhesive tape to the external connector having spacing between the adhesive tape and the substrate base side; cutting a step portion in the encapsulation to expose the stack connector; cutting a singulation kerf in the package substrate having exit damage on the substrate base side; and removing the adhesive tape. | 05-24-2012 |
20120126429 | Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die - A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires. | 05-24-2012 |
20120126430 | Apparatus and Methods for 3-D Stacking of Thinned Die - Thinned die are attached to a flexible substrate and the die-substrate assembly is formed (wound) around multiple horizontal fingers of a heat removal buss structure such that the substrate below each die is in contact with one of the fingers. The fingers connect to a vertical support member that provides stability and a means of connecting the heat removal buss structure to the ambient. | 05-24-2012 |
20120126431 | SEMICONDUCTOR PACKAGE - A semiconductor package having improved EMI and crosstalk characteristics is provided. The semiconductor package includes a semiconductor package including a substrate, at least one first semiconductor chip formed on a top surface of the substrate and electrically connected to the substrate, and at least one second semiconductor chip formed on a top surface of the first semiconductor chip and electrically connected to the first semiconductor chip, wherein first and second conductive layers are formed on the top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the first conductive layer and the second conductive layer are connected to a ground portion. | 05-24-2012 |
20120133053 | SURFACE MOUNT SEMICONDUCTOR DEVICE - A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material. | 05-31-2012 |
20120133054 | DETECTOR ARRAY WITH A THROUGH-VIA INTERPOSER - A method for forming a sensor stack is presented. The method includes providing a substrate having a first side and a second side. Furthermore, the method includes disposing an integrated circuit having a first side and a second side on the first side of the substrate, where the integrated circuit comprises a first plurality of contact pads disposed on the first side of the integrated circuit. The method also includes providing a sensor array having a plurality of sensor elements, wherein each of the sensor elements has a first side and a second side, and wherein the sensor array comprises a second plurality of contact pads disposed on the second side of the sensor array. Furthermore, the method includes disposing an interposer having one or more interposer elements and one or more through vias disposed therethrough between the one or more sensor elements of the sensor array and the integrated circuit to raise the sensor array away from the first side of the integrated circuit such that a plane of the one or more sensor elements is locally normal to a sensor stack normal, wherein the interposer is configured to operationally couple the second side of the sensor elements in the sensor array to the first side of the integrated circuit. In addition, the method includes operationally coupling the first plurality of contact pads on the first side of the integrated circuit to a second plurality of contact pads on the second side of the sensor array to form a tileable sensor stack. | 05-31-2012 |
20120133055 | Semiconductor chip and semiconductor device - A semiconductor chip capable of realizing reduction in cost when the semiconductor chip is mounted over a package substrate, miniaturization of the package substrate, and optimization of an interconnect pattern. The semiconductor chip includes a first electrode pad group provided in the semiconductor chip, and comprised of at least one electrode pad, and a second electrode pad group provided in the semiconductor chip, and comprised of at least one other electrode pad capable of outputting a signal identical to a signal outputted by the one electrode pad. Further, either the one electrode pad of the first electrode pad group, or the one other electrode pad of the second electrode pad group, closer in distance to one other electrode pad of one other semiconductor chip is coupled to the one other electrode pad of the one other semiconductor chip. | 05-31-2012 |
20120133056 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS AND SEMICONDUCTOR DEVICE FABRICATING METHOD - There is provided a semiconductor device which includes a primary semiconductor chip | 05-31-2012 |
20120146240 | SEMICONDUCTOR DEVICE - To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding. | 06-14-2012 |
20120146241 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP CONDUCTORS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a base device having a base circuit connector directly on the component side; attaching conformal interconnects, having the same pre-deformation height from the component side, directly on the component side and offset from the base device; and attaching a stack substrate having stack interconnects directly on the conformal interconnects, portions of the stack interconnects covered by the conformal interconnects having different deformation heights from the component side. | 06-14-2012 |
20120146242 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member. | 06-14-2012 |
20120146243 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER - An integrated circuit packaging system comprising: a base package substrate; a first integrated circuit die attached over the base package substrate; and an interposer having a recessed edge and a corner that extends to a singulation edge, the interposer mounted over the first integrated circuit die, the interposer having a recess gap between the recessed edge and the singulation edge. | 06-14-2012 |
20120146244 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion. | 06-14-2012 |
20120146245 | SEMICONDUCTOR DEVICE - A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips. | 06-14-2012 |
20120153504 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a substrate ( | 06-21-2012 |
20120153505 | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die. | 06-21-2012 |
20120168964 | Probe Card and Method of Testing a Semiconductor Device - A probe card includes a main circuit board electrically connected to a tester in order to test a plurality of unpackaged sets of chips, a frame provided on the main circuit board and including a plurality of sockets for respectively receiving the unpackaged sets of chips, probe blocks respectively provided in the sockets and including a plurality of probes electrically connected to input/output terminals of the unpackaged sets of chips, and a cover plate positioned over the frame and including a plurality of pressure members for pressurizing the unpackaged sets of chips in the sockets. | 07-05-2012 |
20120168965 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires. | 07-05-2012 |
20120168966 | STACKED-CHIP DEVICE - A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip. | 07-05-2012 |
20120181706 | POWER SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first power chip has a first surface and a second surface opposing to the first surface. A first control electrode and a first main power electrode are disposed on the first surface, and a second main power electrode is disposed on the second surface. The second surface is disposed on the carrier, and electrically connected to the carrier through the second main power electrode. The second power chip has a third surface and a fourth surface opposing to the third surface. A third main power electrode is disposed on the third surface, and a fourth main power electrode is disposed on the fourth surface. The fourth surface is disposed on the first power chip. The first conductive sheet is electrically connected to the first main power electrode and the fourth main power electrode. The second conductive sheet is electrically connected to the third main power electrode. The third conductive sheet is electrically connected to the first control electrode. At least a part of the first control electrode is non-covered by the second power chip along a projection direction, which is perpendicular to the carrier. | 07-19-2012 |
20120187574 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory device has a laminated chip package and a controller plate. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller plate. A plurality of opposing wiring electrodes are formed at an opposing surface of the controller plate. A plurality of outside wiring electrodes are formed on the rear side of the opposing surface. Connection electrodes connecting the opposing wiring electrodes and the outside wiring electrodes are formed on the side surface of the controller plate. The interposed chip has a plurality of interposed wiring electrodes. The plurality of interposed wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of the plurality of opposing wiring electrodes. The controller plate is laid on the interposed chip. | 07-26-2012 |
20120187575 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes a plurality of common electrodes electrically connected to the plurality of common lines, and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to. | 07-26-2012 |
20120187576 | Three-Dimensional Integrated Circuits with Protection Layers - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 07-26-2012 |
20120187577 | Direct Edge Connection for Multi-Chip Integrated Circuits - The present invention allows for direct chip-to-chip connections using the shortest possible signal path. | 07-26-2012 |
20120199987 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES, AND RELATED STRUCTURES - Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example. | 08-09-2012 |
20120199988 | METHOD OF MANUFACTURING ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND APPARATUS FOR MANUFACTURING ELECTRONIC DEVICE - Disclosed is a method of manufacturing an electronic device, that includes obtaining a stack of the first electronic component and the second electronic component, while placing a resin layer which contains a flux-active compound and a thermosetting resin, between the first terminals and the second terminals; bonding the first terminals and the second terminals with solder, by heating the stack at a temperature not lower than the melting point of solder layers on the first terminals, while pressurizing the stack using a fluid; and curing the resin layer. The duration from the point of time immediately after the start of heating of the stack, up to the point of time when the temperature of the stack reaches the melting point of the solder layers, is set to 5 seconds or longer, and 15 minutes or shorter. | 08-09-2012 |
20120211899 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND POWER SUPPLY UNIT - A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating. | 08-23-2012 |
20120217654 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a wafer comprising a chip that passes a test and a chip that does not pass a test, one or more first stacked chips that are stacked over the chip that passes a test, and one or more second stacked chips that are stacked over the chip that does not pass a test, wherein the second stacked chips comprise at least one between an chip that does not pass a test and a dummy chip. | 08-30-2012 |
20120217655 | ELECTRONIC DEVICE FOR HIGH POWER APPLICATIONS - An electronic device includes a first semi-conductor die, a second semi-conductor die and an electrically conductive element. The electrically conductive element includes a first electrically conductive part interposed at least partially between the first semi-conductor die and the second semi-conductor die, wherein said first part is electrically coupled to the first semi-conductor die. The electrically conductive element further includes a second electrically conductive part electrically coupled to the first part, wherein said second part extends from at least part of the first part. The first part is an electrically conductive strap between the dice, and the second part is clip extending from at least part of the strap. | 08-30-2012 |
20120217656 | Semiconductor Package Including Multiple Chips And Separate Groups of Leads - Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package. | 08-30-2012 |
20120217657 | MULTI-CHIP MODULE PACKAGE - A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers. | 08-30-2012 |
20120217658 | MULTI-STACK SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The invention relates to a multi-stack semiconductor integrated circuit device where communication between semiconductor chips can be efficiently carried out by bypassing a number of chips. Each semiconductor chip that forms a multi-stack semiconductor integrated circuit device having a stack structure where four or more semiconductor chips having the same shape are stacked on top of each other is provided with: a first coil for transmission/reception for communication between chips over a long distance; and a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of the above-described first coil for transmission/reception. | 08-30-2012 |
20120223441 | STACKED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas. | 09-06-2012 |
20120223442 | Method for Manufacturing an Electronic Device - During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots. | 09-06-2012 |
20120228782 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE, ELECTRONIC DEVICE, METHOD FOR MANUFACTURING ELECTRONIC DEVICE PACKAGE AND ELECTRONIC DEVICE PACKAGE - Disclosed is a method for manufacturing an electronic device, the method including: placing an electronic component on a substrate | 09-13-2012 |
20120235307 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity. | 09-20-2012 |
20120235308 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased. | 09-20-2012 |
20120241979 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STEP MOLD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate. | 09-27-2012 |
20120241980 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COLLAPSED MULTI-INTEGRATION PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate. | 09-27-2012 |
20120241981 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed herein is a semiconductor device including: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of the first laminate; a functional element disposed in at least one of the first laminate and the second laminate; and an air gap penetrating an interface between the first laminate and the second laminate, the air gap being disposed on an outside of a circuit formation region including the functional element in at least one of the first laminate and the second laminate as viewed from a direction perpendicular to the principal surfaces of the first laminate and the second laminate. | 09-27-2012 |
20120241982 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 09-27-2012 |
20120248628 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device includes a control element provided above a main surface of a substrate through a first adhesion layer, a second adhesion layer provided to cover the control element a first semiconductor chip provided on the second adhesion layer, a bottom surface area of the first semiconductor chip being larger than a top surface area of the control element, and at least one side of an outer edge of the control element projecting to an outside of an outer edge of the first semiconductor chip. | 10-04-2012 |
20120248629 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit. | 10-04-2012 |
20120256321 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width. | 10-11-2012 |
20120261837 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip. | 10-18-2012 |
20120261838 | MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME - A multi-chip package includes a substrate ( | 10-18-2012 |
20120267796 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES - A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture. | 10-25-2012 |
20120267797 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. | 10-25-2012 |
20120267798 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly is disclosed that comprises a substrate having first and second openings, a first microelectronic element and a second microelectronic element in a face-down position. The first element has an active surface facing the front surface of the substrate and bond pads aligned with the first opening, a rear surface remote therefrom, and an edge extending between the front and rear surfaces. The second microelectronic element has a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, and bond pads at the front surface of the second microelectronic element aligned with the second opening. | 10-25-2012 |
20120267799 | PACKAGE STRUCTURES - A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die. | 10-25-2012 |
20120267800 | Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Level Chip Scale Package - A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer. | 10-25-2012 |
20120273970 | SEMICONDUCTOR DEVICE - Miniaturization and acceleration of the operating speed of a System In Package (SIP) type semiconductor device in which a memory chip and a microcomputer chip are mounted over a wiring board are promoted. When mounting a microcomputer chip and a memory chip over an upper surface of a wiring board, the memory chip is disposed such that second conductive pads of the wiring board arranged along a first chip side (a side along which data system electrode pads are arranged) of the memory chip are positioned, in the plan view, in a region between an extended line of a third chip side of the microcomputer chip and an extended line of a fourth chip side of the microcomputer chip. Thus, a length of a data system wiring for coupling a data system electrode pad of the microcomputer chip with the data system electrode pad of the memory chip is minimized. | 11-01-2012 |
20120273971 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device that comprises a wiring substrate, at least two semiconductor chips mounted on the wiring substrate, and at least one reinforcing substrate disposed so as to straddle at least portions of the two semiconductor chips. | 11-01-2012 |
20120273972 | SEMICONDUCTOR DEVICE - Mounting a power supply ring-shaped conductor and a ground ring-shaped conductor within the innermost circumferential ring-shaped area enclosing the semiconductor chip and within the ring-shaped region adjacent to the outer side of this innermost circumferential ring-shaped region when mounting the semiconductor chip on the substrate package, makes the chip more resistant to noise but also conversely causes the problem of increased cost and size for the entire semiconductor device. The power supply pad and ground pad are here clustered in the outermost ring-shaped area on the semiconductor chip. The power supply terminal and ground terminal are clustered on the innermost ring-shaped region enclosing the semiconductor chip. This placement reduces the size and manufacturing cost of the overall semiconductor device. | 11-01-2012 |
20120280404 | STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR - A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate. | 11-08-2012 |
20120280405 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACURING THE SAME - Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface. | 11-08-2012 |
20120280406 | SEMICONDUCTOR DEVICE - A semiconductor device has a three dimensional multi-chip structure including a plurality of chips stacked one on another. The three dimensional multi-chip structure includes a first chip, and a second chip being adjacent to the first chip on an upper or lower side of the first chip, and larger than the first chip. A through electrode is formed in at least one of the first chip or the second chip. The first chip is electrically connected to the second chip via the through electrode. A resin is provided on a surface of the second chip closer to the first chip in a portion of the second chip located outside the first chip. | 11-08-2012 |
20120286432 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; providing a first integrated circuit having a first integrated circuit inactive side and a first integrated circuit active side; coupling a second integrated circuit, having a second integrated circuit inactive side and a second integrated circuit active side, to the first integrated circuit in an active-to-active configuration; attaching the first integrated circuit over the base carrier; attaching a redistribution structure over the first integrated circuit; and forming a base encapsulation over the redistribution structure, the base encapsulation having a recess partially exposing the redistribution structure. | 11-15-2012 |
20120292787 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate. | 11-22-2012 |
20120292788 | Chip stacking - Methods and systems are provided to utilize and manufacture a stacked chip assembly. Microelectronic or optoelectronic chips of any dimensions are directly stacked onto each other. The chips can be of substantially identical sizes. To enable forming the stacked chip assembly, trenches are laser micro-machined onto the bottom surface of a chip to accommodate the bond wedge/ball and wire path of the chip beneath it. Consequently, chips can be tightly integrated without a gap and without having to reserve space for the bond wedges/balls. | 11-22-2012 |
20120299197 | SEMICONDUCTOR PACKAGES - Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter. | 11-29-2012 |
20120299198 | INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS - High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed. | 11-29-2012 |
20120299199 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 11-29-2012 |
20120299200 | 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER - A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer. | 11-29-2012 |
20120306102 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base package carrier; mounting an interposer over the base package carrier; forming a base package encapsulation over the base package carrier and the interposer with the base package encapsulation having a cavity for exposing the interposer; and forming a support recess in the base package encapsulation between a non-horizontal edge of the base package encapsulation and the cavity. | 12-06-2012 |
20120306103 | STACKED ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed. | 12-06-2012 |
20120313259 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines. | 12-13-2012 |
20120313260 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion. | 12-13-2012 |
20120313261 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure. | 12-13-2012 |
20120313262 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device includes a plurality of first electrodes provided on a first printed wiring board and columnar electrodes provided on the first electrodes. The stacked semiconductor device also includes a plurality of second electrodes provided on a second printed wiring board and a plurality of solder electrodes. The columnar electrodes are formed of a material having a melting point higher than that of the solder electrodes, and the height of the columnar electrodes is set to increase as a distance between the first electrodes and the solder electrodes increases. This avoids connection failure without reducing joinability between two stacked semiconductor devices. | 12-13-2012 |
20120313263 | Three-Dimensional Multichip Module - A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips. | 12-13-2012 |
20120319300 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a projection formed along a perimeter of a first surface of the substrate; mounting an integrated circuit over the first surface; forming a protruding interconnect over the first surface between the projection and the integrated circuit; and forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection. | 12-20-2012 |
20120326331 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit. | 12-27-2012 |
20120326332 | SEMICONDUCTOR DEVICE WITH ENCAPSULATED ELECTRICAL CONNECTION ELEMENTS AND FABRICATION PROCESS THEREOF - An integrated-circuit chip and external electrical connection elements are arranged on a first side of a substrate to form an assembly that is placed within a mold. The mold includes first and second opposed planar faces with a molding film made of a deformable material on the first planar face. The molding film is pressed against end faces of the external electrical connection elements. Encapsulating material then fills the mold cavity producing a semiconductor device that, when removed from the mold, includes electrical connection elements that are peripherally coated by the encapsulating material and have exposed end faces. An additional semiconductor device may be mounted over and in electrical connection with the electrical connection elements through the exposed end faces. | 12-27-2012 |
20120326333 | SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT - A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality. | 12-27-2012 |
20130001802 | SEMICONDUCTOR DEVICE INCLUDING INSULATING RESIN FILM PROVIDED IN A SPACE BETWEEN SEMICONDUCTOR CHIPS - A semiconductor device includes a first semiconductor, a second semiconductor, and an insulating resin. The first semiconductor chip includes first and second electrodes formed on first and second surfaces thereof, respectively. The second semiconductor chip includes a third electrode formed on a third surface thereof. The insulating resin film includes a flux activator. The insulating resin film is provided a space between the first and the second semiconductor chips. | 01-03-2013 |
20130009326 | MANUFACTURING METHOD OF CHIP PACKAGE WITH COPLANARITY CONTROLLING FEATURE - A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate. | 01-10-2013 |
20130015589 | CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKSAANM Liao; Chih-ChinAACI Changhua CountyAACO TWAAGP Liao; Chih-Chin Changhua County TWAANM Chiu; Chin-TienAACI Taichung CityAACO TWAAGP Chiu; Chin-Tien Taichung City TWAANM Yu; CheemanAACI FremontAAST CAAACO USAAGP Yu; Cheeman Fremont CA USAANM Upadhyayula; Suresh KumarAACI San JoseAAST CAAACO USAAGP Upadhyayula; Suresh Kumar San Jose CA USAANM Li; Wen ChengAACI Taichung CityAACO TWAAGP Li; Wen Cheng Taichung City TWAANM Lu; ZhongAACI ShanghaiAACO CNAAGP Lu; Zhong Shanghai CN - A multi-die semiconductor device is disclosed. The device may include one or more first-sized die on a substrate and one or more second-sized die affixed over the one or more first-sized die. The second-sized die may have a larger footprint than the first-sized die. An internal molding compound may be provided on the substrate having a footprint the same size as the second-sized die. The second-sized die may be supported on the internal molding compound. Thereafter, the first and second-sized die and the internal molding compound may be encapsulated in an external molding compound. | 01-17-2013 |
20130020723 | COMPOSITE LAYERED CHIP PACKAGE - A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring. | 01-24-2013 |
20130026655 | CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A chip package structure includes a substrate in which a plurality of grooves are formed, an adhesive layer disposed on the substrate, and a plurality of chips attached to the adhesive layer. In addition, a method of fabricating the chip package structure includes forming a plurality of grooves in the substrate, dispensing a die attach material on a plurality of chip attaching regions between the plurality of grooves, and attaching a plurality of chips respectively on the plurality of chip attaching regions. | 01-31-2013 |
20130026656 | SEMICONDUCTOR PACKAGES AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad. | 01-31-2013 |
20130032952 | Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die - A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die. | 02-07-2013 |
20130032953 | METHOD OF MANUFACTURING A PLURALITY OF ELECTRONIC ASSEMBLIES - A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively. | 02-07-2013 |
20130032954 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed. | 02-07-2013 |
20130043601 | UNIVERSAL PRINTED CIRCUIT BOARD AND MEMORY CARD INCLUDING THE SAME - Disclosed is a memory card which includes a universal PCB including a first pad group and a second pad group, the first and second pad groups being connected to each other via one or more PCB wires, a first semiconductor chip electrically connected with at least one pad of the first pad group via a first bonding wire, and a second semiconductor chip electrically connected with at least one pad of the second pad groups via a second bonding wire, wherein the first bonding wire or the second bonding wire is changed according to a combination of the first and second semiconductor chips without a change in the PCB wires. | 02-21-2013 |
20130043602 | METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER - A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic. | 02-21-2013 |
20130049227 | PACKAGE STACKS AND METHOD OF MANUFACTURING THE SAME - A package stack includes a first package, a second package, first solder balls and a molding member. The first package includes a first package substrate, a first semiconductor chip on the first package substrate and connecting pads. The second package includes a second package substrate and a second semiconductor chip on the second package substrate. The second package is disposed over the first package. The first solder balls are in contact with the connecting pads and a bottom of a peripheral portion of the second package substrate. The molding member covers an upper surface of the second package substrate and the second semiconductor chip. A portion of the molding member overlapping the first solder balls has a thickness smaller than a thickness of another portion of the molding member. | 02-28-2013 |
20130049228 | SEMICONDUCTOR PACKAGE HAVING SUPPORTING PLATE AND METHOD OF FORMING THE SAME - A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate. | 02-28-2013 |
20130049229 | SEMICONDUCTOR CHIP DEVICE WITH SOLDER DIFFUSION PROTECTION - Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance. | 02-28-2013 |
20130049230 | STACKING METHOD AND STACKING CARRIER - A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation. | 02-28-2013 |
20130056880 | SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME - An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die. | 03-07-2013 |
20130056881 | Discrete Three-Dimensional Memory - The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%. | 03-07-2013 |
20130056882 | SEMICONDUCTOR PACKAGE HAVING SUPPORT MEMBER - Semiconductor packages including a substrate, a plurality of first semiconductor chips stacked on the substrate, a second semiconductor chip interposed between the substrate and a lowermost semiconductor chip among the first semiconductor chips, and a supporting member disposed between the substrate and the lowermost semiconductor chip among the first semiconductor chips to support the first semiconductor chips, may be provided. The supporting member may include a passive element such as a capacitor, a resistor, or an inductor. By including the supporting member, the semiconductor packages may achieve a smaller planar size and have an improved tolerance for subsequent interconnections. | 03-07-2013 |
20130062780 | CHIP STACKING STRUCTURE - A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process. | 03-14-2013 |
20130062781 | CHIP ARRANGEMENT AND METHOD FOR PRODUCING A CHIP ARRANGEMENT - A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region. | 03-14-2013 |
20130062782 | STACKED SEMICONDUCTOR DEVICES AND FABRICATION METHOD/EQUIPMENT FOR THE SAME - After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips. | 03-14-2013 |
20130062783 | CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions. | 03-14-2013 |
20130062784 | MULTI-CHIP PACKAGES PROVIDING REDUCED SIGNAL SKEW AND RELATED METHODS OF OPERATION - A packaged integrated circuit device includes a substrate, and a conductive pad and a chip stack on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the chips to respective conductive pads on ones of the chips above and below the one of the chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the chips in the chip stack, and the secondary conductive lines may be configured to transmit the signal from the one of the chips to the ones of the chips thereabove and therebelow at a same time. | 03-14-2013 |
20130069247 | APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS - An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die. | 03-21-2013 |
20130069248 | BONDING METHOD FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT THEREOF - The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit. | 03-21-2013 |
20130069249 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 03-21-2013 |
20130075935 | COMPOSITE LAYERED CHIP PACKAGE - A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other. | 03-28-2013 |
20130075936 | Semiconductor Device and Method of Forming Interconnect Substration for FO-WLCSP - A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement. | 03-28-2013 |
20130082403 | Wirelessly Communicating Among Vertically Arranged Integrated Circuits (ICs) in a Semiconductor Package - Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit. | 04-04-2013 |
20130082404 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region. | 04-04-2013 |
20130087929 | Semiconductor Packages And Electronic Systems Including The Same - Provided are semiconductor packages and electronic systems including the same. A first memory chip may be stacked on a first portion of a substrate. A controller chip may be stacked on a second portion of the substrate, which is different from the first portion. At least one first bonding wire may directly connect the first memory chip with the controller chip. At least one second bonding wire may directly connect the first memory chip with the substrate, and may be electrically connected with the at least one first bonding wire. | 04-11-2013 |
20130093101 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device is provided. The semiconductor device includes a package substrate; a first semiconductor chip mounted on the package substrate and adapted to include a plurality of first bonding pads arranged in a first order on an upper surface; a second semiconductor chip arranged on the first semiconductor chip and adapted to include a plurality of second bonding pads arranged in the first order on an upper surface; and first bonding wires configured to connect each of the plurality of first bonding pads and the plurality of second bonding pads. | 04-18-2013 |
20130093102 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Semiconductor packages are provided. The semiconductor package includes a package substrate. A semiconductor chip structure is mounted on the package substrate and includes a plurality of semiconductor chips. A molding member covers the semiconductor chip structure and the package substrate. The plurality of semiconductor chips are vertically stacked and stepped toward one direction. A thickness of an uppermost semiconductor chip of the plurality of semiconductor chips is greater than an average thickness of the other semiconductor chips thereunder. Related methods are also provided. | 04-18-2013 |
20130093103 | Layered Semiconductor Package - Provided is a layered semiconductor package. The present invention comprises: a substrate having a first connection pad and a second connection pad on the upper surface thereof; a first cascade chip-layered body mounted on the substrate in which a plurality of first semiconductor chips are layered in a stepped form so as to expose a first bonding pad to the outside; at least one spacer layered on the upper surface of the uppermost semiconductor chip of the first chip-layered body so as to expose a bonding pad of the uppermost semiconductor chip; a second cascade chip-layered body mounted on the upper surface of the spacer in which a plurality of second semiconductor chips are layered in a stepped form so as to expose a second bonding pad to the outside; a first conductive wire for electrically connecting the first bonding pad of the first semiconductor chip and the first connection pad of the substrate; and a second conductive wire for electrically connecting the second bonding pad of the second semiconductor chip and the second connection pad of the substrate. | 04-18-2013 |
20130099391 | CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP - A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop. | 04-25-2013 |
20130099392 | Support mounted electrically interconnected die assembly - Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder. | 04-25-2013 |
20130099393 | Stacked Semiconductor Package - Provided is a stacked semiconductor package. The present invention includes: a substrate having first and second connective pads provided on an upper surface thereof; a first cascade chip laminate which is loaded on the substrate and in which a plurality of first semiconductor chips are stacked in multiple stages to externally expose a first bonding pad wire-bonded through the first connective pad and a first conductive wire; a second cascade chip laminate in which a plurality of second semiconductor chips are stacked in the multiple stages to externally expose a second bonding pad wire-bonded through the second connective pad and a second conductive wire to an area corresponding to the first bonding pad; and a joint part for joining the first cascade chip laminate and the second cascade chip laminate. | 04-25-2013 |
20130105991 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105992 | SEMICONDUCTOR COMPONENT HAVING A STACK OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING THE SAME | 05-02-2013 |
20130113114 | Device Including Two Power Semiconductor Chips and Manufacturing Thereof - A device includes a first power semiconductor chip having a first face and a second face opposite to the first face with a first contact pad arranged on the first face. The first contact pad is an external contact pad. The device further includes a first contact clip attached to the second face of the first power semiconductor chip. A second power semiconductor chip is attached to the first contact clip, and a second contact clip is attached to the second power semiconductor chip. | 05-09-2013 |
20130113115 | SYSTEM IN PACKAGE PROCESS FLOW - A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate. | 05-09-2013 |
20130113116 | Contact and Method of Formation - A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example. | 05-09-2013 |
20130113117 | Wireless Communication Devices With In-Package Integrated Passive Components - Embodiments of the present disclosure can be used to both reduce the size and cost and improve the performance and power consumption of next generation wireless communication devices. In particular, embodiments enable board and semiconductor substrate area savings by using the fabrication package (which encapsulates the semiconductor substrate) as a design element in the design of next generation wireless communication devices. Specifically, embodiments use the substrate of the fabrication package to integrate into it components of the wireless radio transceiver (which are conventionally integrated into the semiconductor substrate) and other discrete components of the communication device (which are conventionally placed on the board of the device). As such, reduced board and semiconductor area can be realized. | 05-09-2013 |
20130119561 | SEMICONDUCTOR DEVICE - To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding. | 05-16-2013 |
20130127069 | MATRICES FOR RAPID ALIGNMENT OF GRAPHITIC STRUCTURES FOR STACKED CHIP COOLING APPLICATIONS - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip and a second chip electrically and mechanically coupled by a grid of connectors. The chip stack includes a thermal interface material (TIM) between the first chip and the second chip. The TIM includes nanofibers aligned parallel to mating surfaces of the first and second chips, and a thermosetting polymer that when heated, will reduce the viscosity of the TIM to allow for optimal alignment of the carbon nanofibers. The method includes adding at least one thermosetting polymer to the TIM, dispersing nanofibers into the TIM, and heating the TIM until the thermosetting polymer un-crosslinks. The method further includes applying a magnetic field to align the graphite nanofibers and cooling the TIM until the thermosetting polymer re-crosslinks. | 05-23-2013 |
20130127070 | Stacked Seminconductor Package - Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate including at least one contact pad; an external chip laminate which includes a plurality of semiconductor chips mounted on the substrate, and which is stacked in multi-steps such that the ends at one side of the plurality of semiconductor chips alternately protrude in opposite directions to expose bonding pads which are formed on the up-face surface; at least one internal chip which is disposed in a mounting space formed between the external chip laminate and substrate so as to be electrically connected to the substrate; and a conductive wire electrically connecting the bonding pad of the semiconductor chip and the contact pad of the substrate. | 05-23-2013 |
20130134604 | METHOD FOR CREATING AND PACKAGING THREE DIMENSIONAL STACKS OF BIOCHIPS CONTAINING MICROELECTRO-MECHANICAL SYSTEMS - Systems and methods of the present disclosure provide for three-dimensional stacks of microelectromechanical (MEMS) systems, such as sensors. The stacks may be encapsulated and sealed, and can be positioned within biological tissue, for example to monitor biological signals within the volume of the sensor, provide stimulating signals to a brain, and so forth. | 05-30-2013 |
20130134605 | SEMICONDUCTOR ASSEMBLIES, STACKED SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES AND STACKED SEMICONDUCTOR DEVICES - Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns. | 05-30-2013 |
20130147062 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected. | 06-13-2013 |
20130147063 | METHODS OF FABRICATING FAN-OUT WAFER LEVEL PACKAGES AND PACKAGES FORMED BY THE METHODS - A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip. | 06-13-2013 |
20130147064 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. | 06-13-2013 |
20130154115 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion. | 06-20-2013 |
20130154116 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PERIMETER ANTIWARPAGE STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system comprising: providing a package carrier; mounting an integrated circuit to the package carrier; and forming a perimeter antiwarpage structure on and along a perimeter of the package carrier. | 06-20-2013 |
20130154117 | STACKED DIE IN DIE BGA PACKAGE - Die assemblies may include a first die abutting a substrate comprising a recess adjacent to the substrate. An adhesive element may be contained within the recess to attach the first die to the substrate. A height of the adhesive element may not contribute to an overall height of the die assembly. In some embodiments, a second die comprising a non-rectangular cross-sectional shape may be situated on the first die. Die assemblies ma also comprise a first die on a substrate and comprising a cavity on a side of the first die opposing a side on which the support substrate is located. A second die may be at least partially disposed in the cavity. Die assemblies may also comprise a first die secured to a substrate and partially inserted into a recess of a second die on a side opposing a side on which the substrate is located. | 06-20-2013 |
20130161833 | Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate. | 06-27-2013 |
20130161834 | HETEROGENEOUS INTEGRATION PROCESS INCORPORATING LAYER TRANSFER IN EPITAXY LEVEL PACKAGING - Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes. | 06-27-2013 |
20130161835 | MULTILAYER CONNECTION STRUCTURE - A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers. | 06-27-2013 |
20130175704 | DISCRETE POWER TRANSISTOR PACKAGE HAVING SOLDERLESS DBC TO LEADFRAME ATTACH - A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device. | 07-11-2013 |
20130175705 | Stress Compensation Layer for 3D Packaging - A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate. | 07-11-2013 |
20130175706 | SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip. | 07-11-2013 |
20130181359 | Methods and Apparatus for Thinner Package on Package Structures - Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed. | 07-18-2013 |
20130181360 | INTEGRATED CIRCUIT CONNECTIVITY USING FLEXIBLE CIRCUITRY - An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure. | 07-18-2013 |
20130187292 | Multi-Dimensional Integrated Circuit Structures and Methods of Forming the Same - A structure comprises a first die, a second die, an interposer, a third die, and a fourth die. The first die and the second die each have a first surface and a second surface. First conductive connectors are coupled to the first surfaces of the first and second dies, and second conductive connectors are coupled to the second surfaces of the first and second dies. The interposer is over the first and second dies. A first surface of the interposer is coupled to the first conductive connectors, and a second surface of the interposer is coupled to third conductive connectors. The third and fourth dies are over the interposer and are coupled to the third conductive connectors. The first die is communicatively coupled to the second die through the interposer, and/or the third die is communicatively coupled to the fourth die through the interposer. | 07-25-2013 |
20130193587 | Semiconductor Package Having an Interposer Configured for Magnetic Signaling - There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance. | 08-01-2013 |
20130193588 | SEMICONDUCTOR PACKAGE - A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer. | 08-01-2013 |
20130200529 | Semiconductor Device Packaging Methods and Structures Thereof - Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies. | 08-08-2013 |
20130200530 | Semiconductor Packages Including a Plurality of Stacked Semiconductor Chips - Semiconductor packages including a plurality of semiconductor chips are provided. The semiconductor package includes a semiconductor base frame; a first semiconductor chip stacked on the semiconductor base frame and having an upper surface that has a first area; a second semiconductor chip stacked on the first semiconductor chip and having an upper surface that has a second area larger than the first area; a first adhesive tape attached to a lower surface of the first semiconductor chip and a second adhesive tape attached to a lower surface of the second semiconductor chip; and first and second bonding wires that connect the first semiconductor chip and the second semiconductor chip to the semiconductor base frame, respectively. The first bonding wire bends through the second adhesive tape and is connected to a portion of the semiconductor base frame, which is located below the lower surface of the second semiconductor chip. | 08-08-2013 |
20130207280 | SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING - A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package. | 08-15-2013 |
20130214430 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side. | 08-22-2013 |
20130214431 | Fine-Pitch Package-on-Package Structures and Methods for Forming the Same - A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings. | 08-22-2013 |
20130221542 | Functional Spacer for SIP and Methods for Forming the Same - A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess. | 08-29-2013 |
20130221543 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a base integrated circuit over the base substrate; attaching a lead to the base integrated circuit and the base substrate, the lead having a lead attachment portion over the base integrated circuit; and forming a base encapsulation over the lead, the base encapsulation having a cavity exposing the lead attachment portion. | 08-29-2013 |
20130241081 | COMBINATION FOR COMPOSITE LAYERED CHIP PACKAGE - A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip. | 09-19-2013 |
20130241082 | POWER CONVERTER - A power converter includes a plurality of semiconductor modules that have main body sections, each of the main body sections has a semiconductor element therein, and power terminals projected from the main body sections, and a plurality of bus bars that connect the power terminals of the semiconductor modules. At least one of the plurality of the bus bars are connecting bus bars which have a plurality of terminal connecting sections that connect the power terminals of the plurality of different semiconductor modules, and connecting sections that connect the terminal connecting sections. The entirety of each of the connecting bus bars is formed integrally. The terminal connecting sections and the connecting section of every connecting bus bar are provided alternately in the connecting bus bar, and disposed in substantially the same position in a projecting direction of the power terminals. | 09-19-2013 |
20130249115 | Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 09-26-2013 |
20130249116 | MICROELECTRONIC PACKAGE - A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips. | 09-26-2013 |
20130256911 | SEMICONDUCTOR CHIP STACK PACKAGE AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity | 10-03-2013 |
20130256912 | CHIP ARRANGEMENT AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side. | 10-03-2013 |
20130256913 | DIE STACKING WITH COUPLED ELECTRICAL INTERCONNECTS TO ALIGN PROXIMITY INTERCONNECTS - A method of manufacturing is provided that includes forming a first proximity interconnect on a first side of a first semiconductor chip and a first plurality of interconnect structures projecting from the first side. A second proximity interconnect is formed on a second side of a second semiconductor chip and a second plurality of interconnect structures are formed projecting from the second side. The second semiconductor chip is coupled to the first semiconductor chip so that the second side faces the first side and the first interconnect structures are coupled to the second interconnect structures. The first and second proximity interconnects cooperate to provide a proximity interface. The coupling of the first interconnect structures to the second interconnect structures provides desired vertical and lateral alignment of the first and second proximity interconnects. | 10-03-2013 |
20130256914 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - The described embodiments of forming bonding structures for package on package involves removing a portion of connectors and molding compound of the lower package. The described bonding mechanisms enable easier placement and alignment of connectors of an upper package to with connector of a lower package. As a result, the process window of the bonding process is wider. In addition, the bonding structures have smoother join profile and planar joint plane. As a result, the bonding structures are less likely to crack and also are less likely to crack. Both the yield and the form factor of the package on package structure are improved. | 10-03-2013 |
20130256915 | PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency. | 10-03-2013 |
20130256916 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES - A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package. | 10-03-2013 |
20130256917 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs. | 10-03-2013 |
20130256918 | DEVICE - A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste. | 10-03-2013 |
20130256919 | MULTIFUNCTION SENSOR AS POP MICROWAVE PCB - A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method. | 10-03-2013 |
20130256920 | SEMICONDUCTOR DEVICE - A semiconductor device in one embodiment includes a chip-mount substrate, a first semiconductor chip mounted on the chip-mount substrate, and a second semiconductor chip mounted adjacent to the first semiconductor chip on the chip-mount substrate. | 10-03-2013 |
20130264721 | Electronic Module - The electronic module includes a first carrier and a first semiconductor chip arranged on the first carrier. A second semiconductor chip is arranged above the first semiconductor chip. A material layer adheres the second semiconductor chip to the first carrier and encapsulates the first semiconductor chip. | 10-10-2013 |
20130264722 | MULTILAYERED SEMICONDUCTOR DEVICE, PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTILAYERED SEMICONDUCTOR DEVICE - Provided is a multilayered semiconductor device, including: a first semiconductor package including a first semiconductor element and a first wiring board; a second semiconductor package including: a second semiconductor element, a second wiring board and a first encapsulating resin for encapsulating the second semiconductor element therein; and a plate member disposed between the first semiconductor package and the second semiconductor package, the first semiconductor package, the plate member, and the second semiconductor package being stacked in this order, in which the first wiring board and the second wiring board are electrically connected to each other via a metal wire through one of a notch and an opening formed in the plate member and the first semiconductor element, the second semiconductor package, and the metal wire are encapsulated in a second encapsulating resin. | 10-10-2013 |
20130270717 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam. | 10-17-2013 |
20130270718 | PRINTED CIRCUIT BOARD HAVING EMBEDDED DIES AND METHOD OF FORMING SAME - A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die. | 10-17-2013 |
20130270719 | MICROELECTRONIC PACKAGE AND STACKED MICROELECTRONIC ASSEMBLY AND COMPUTING SYSTEM CONTAINING SAME - A microelectronic package comprises a die ( | 10-17-2013 |
20130277862 | INTERMEDIATE FOR ELECTRONIC COMPONENT MOUNTING STRUCTURE, ELECTRONIC COMPONENT MOUNTING STRUCTURE, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT MOUNTING STRUCTURE - An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal. | 10-24-2013 |
20130285259 | METHOD AND SYSTEM FOR WAFER AND STRIP LEVEL BATCH DIE ATTACH ASSEMBLY - A method and system is provided by which multiple semiconductor die stacks can be assembled in a batch manner, and which also provides for die alignment tolerances required by microelectromechanical systems and other system-in-package applications. The batch process and accuracy is provided, in part, by an intermediate die attach carrier that has multiple die pockets fabricated to hold a set of die with an alignment required for the application. Die are placed in each pocket using a die sorting process. Then a batch process operation is performed in which wafer or strip-level alignment and bonding tools are used to join the die in the intermediate die attach carrier in stacks with a second set of die. | 10-31-2013 |
20130285260 | MULTI-CHIP MODULE INCLUDING STACKED POWER DEVICES WITH METAL CLIP - A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals. | 10-31-2013 |
20130285261 | SEMICONDUCTOR CHIP STACKING ASSEMBLIES - Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second semiconductor device. An assembly comprises a first semiconductor chip that has a first and a second set of electrical interconnect regions disposed on its surface and a second semiconductor chip. The first set of electrical interconnect regions are electrically connected with the electrical interconnect regions of a second semiconductor chip, and the second set of electrical interconnect regions are electrically interconnected with the substrate. Direct electrical connections are for example, silicon photonics device-to-driver or device-to-signal converters, logic-to-memory, memory-to-memory, and logic-to-logic chip interconnections. | 10-31-2013 |
20130292852 | CHIP EMBEDDED PACKAGES AND METHODS FOR FORMING A CHIP EMBEDDED PACKAGE - A chip embedded package is provided, the chip embedded package including: a plurality of dies; wherein a first die of the plurality of dies is a chip implementing a first sensor technology, and wherein a second die of the plurality of dies is a chip implementing a second sensor technology; and wherein the plurality of dies are molded with an encapsulation material; wherein at least one of the first die and the second die includes a film interconnect. | 11-07-2013 |
20130292853 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. | 11-07-2013 |
20130292854 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES - Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die. | 11-07-2013 |
20130300000 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact. | 11-14-2013 |
20130307163 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring substrate, a semiconductor chip whose connection terminal is connected to the wiring substrate, an underfill resin formed from a clearance between the wiring substrate and the semiconductor chip to a periphery area of the semiconductor chip, wherein the underfill resin in the periphery area is formed at a same height as an upper surface of the semiconductor chip, an auxiliary member fixed on the semiconductor chip by an adhesive layer, and including a protruding portion which protrudes to an outside from the semiconductor chip, and the protruding portion arranged at least on the underfill resin via the adhesive layer, and a sealing resin sealing the underfill resin and at least side faces of the auxiliary member, wherein respective coefficients of thermal expansion of the auxiliary member and the adhesive layer are larger than a coefficient of thermal expansion of the semiconductor chip. | 11-21-2013 |
20130307164 | INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS - High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed. | 11-21-2013 |
20130313726 | LOW-TEMPERATURE FLIP CHIP DIE ATTACH - A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection. | 11-28-2013 |
20130313727 | MULTI-STACKED BBUL PACKAGE - A method including forming a first portion of a build-up carrier on at least one first die, the at least one first die; coupling at least one second die to the first portion of the build-up carrier, the at least one second die separated from the first die by the at least one layer of conductive material disposed between layers of dielectric material; and after coupling the at least one second die to the first portion of the build-up carrier, forming a second portion of the build-up carrier on the at least one second die. An apparatus including a build-up carrier including including alternating layers of conductive material and dielectric material and at least two dice therein in different planes of the build-up carrier. | 11-28-2013 |
20130320565 | Interposer Die for Semiconductor Packaging - According to one exemplary implementation, a method includes lithographically forming a plurality of reticle images on a semiconductor wafer. The method further includes singulating the semiconductor wafer into an interposer die such that the interposer die includes at least a portion of a first reticle image and at least a portion of a second reticle image from the plurality of reticle images. The first reticle image and the second reticle image can be produced from a single reticle. The method can further include electrically connecting a first active die to a second active die through the interposer die. The method can also include electrically connecting the first active die to a package substrate through the interposer die. | 12-05-2013 |
20130320566 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch. | 12-05-2013 |
20130320567 | BATCH PROCESS FOR THREE-DIMENSIONAL INTEGRATION - A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical. | 12-05-2013 |
20130320568 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a printed wiring board and a semiconductor chip that has a first signal terminal and a second signal terminal and is mounted on the printed wiring board. The printed wiring board has a first land and a second land for solder joining, which are formed on a surface layer thereof. Further, the printed wiring board has a first wiring for electrically connecting the first signal terminal of the semiconductor chip and the first land, and a second wiring for electrically connecting the second signal terminal of the semiconductor chip and the second land. The second wiring is formed so that the wiring length thereof is larger than that of the first wiring. The second land is formed so that the surface area thereof is larger than that of the first land. This reduces difference in transmission line characteristics due to the difference in wiring length. | 12-05-2013 |
20130320569 | STACKED SEMICONDUCTOR DEVICE - A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability. | 12-05-2013 |
20130328216 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer bottom side and an interposer top side; attaching a base integrated circuit to the interposer bottom side; attaching a lead to the interposer bottom side, the lead adjacent the base integrated circuit and entirely below the interposer; and forming an encapsulation partially covering the lead and exposing the interposer top side. | 12-12-2013 |
20130334706 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive. | 12-19-2013 |
20130334707 | APPARATUS, SYSTEM, AND METHOD FOR WIRELESS CONNECTION IN INTEGRATED CIRCUIT PACKAGES - Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed. | 12-19-2013 |
20130334708 | STACKED SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTIONS OF VARYING HEIGHTS BETWEEN SUBSTRATES, AND SEMICONDUCTOR DEVICE INCLUDING THE STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side. | 12-19-2013 |
20130334709 | STACKED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas. | 12-19-2013 |
20130334710 | Contact and Method of Formation - A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example. | 12-19-2013 |
20130341804 | SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING - Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip. | 12-26-2013 |
20130341805 | MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height. | 12-26-2013 |
20140001651 | PACKAGE SUBSTRATES WITH MULTIPLE DICE | 01-02-2014 |
20140001652 | PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL | 01-02-2014 |
20140001653 | PACKAGE-ON-PACKAGE DEVICE AND METHOD OF FABRICATING THE SAME | 01-02-2014 |
20140008818 | METHOD AND APPARATUS FOR STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip. | 01-09-2014 |
20140015147 | CHIP STACK PACKAGES, SYSTEM IN PACKAGES INCLUDING THE SAME, AND METHODS OF OPERATING THE SAME - A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting data I/O signals, a first flag pad for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip. The second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip. The first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire. Related methods are also provided. | 01-16-2014 |
20140015148 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a circuit board, at least one semiconductor chip mounted on the circuit board, a spacer disposed on the at least one semiconductor chip, the spacer having a thickness of about 5 μm to about 110 μm, and an upper surface of the spacer exposed externally; and an encapsulant covering the at least one semiconductor chip. The semiconductor package may have a small thickness and may prevent incomplete molding that causes exposure of an active surface of a semiconductor chip. | 01-16-2014 |
20140021638 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 01-23-2014 |
20140021639 | Vertical System Integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 01-23-2014 |
20140027930 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR PACKAGE - According to one embodiment, a semiconductor device includes a package substrate, a semiconductor package, a first semiconductor chip and a first bonding wire. The package substrate has a first pad on a first principal surface. The semiconductor package is mounted on the first principal surface of the package substrate. The semiconductor package contains a semiconductor chip and has a second pad. The first semiconductor chip is mounted on the semiconductor package. The first bonding wire is connected between the first pad and the second. | 01-30-2014 |
20140027931 | STACK PACKAGES USING RECONSTITUTED WAFERS - A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads. | 01-30-2014 |
20140035165 | Pierced Substrate on Chip Module Structure - The present invention provides a pierced substrate on chip module structure comprising a first substrate. A chip is configured on the first substrate, with a first contact pad and a sensing area. A second substrate is disposed on the first substrate and the chip, with a concave structure, at least one through hole structure and a second contact pad, wherein the chip is disposed within the concave structure, and the first contact pad and the sensing area are exposed over the through hole structure. The first contact is coupled to the second contact pad via a wire. A transparent material is disposed on the second substrate, substantially aligning to the sensing area. A lens holder is disposed on the second substrate, and a lens is located on the top of the lens holder, substantially aligning to the transparent material and the sensing area. | 02-06-2014 |
20140035166 | SEMICONDUCTOR DEVICE STACK WITH BONDING LAYER AND WIRE RETAINING MEMBER - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 02-06-2014 |
20140042643 | Interposer System and Method - A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region. | 02-13-2014 |
20140042644 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. | 02-13-2014 |
20140048957 | THIN SUBSTRATE PoP STRUCTURE - A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate. | 02-20-2014 |
20140054795 | Electronic Assembly With Three Dimensional Inkjet Printed Traces - One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts. | 02-27-2014 |
20140054796 | STACKED MICROELECTRONIC PACKAGES HAVING PATTERENED SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package. | 02-27-2014 |
20140054797 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors. | 02-27-2014 |
20140054798 | SENSOR PACKAGES AND METHOD OF PACKAGING DIES OF DIFFERING SIZES | 02-27-2014 |
20140054799 | Three-Dimensional Multichip Module - A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips. | 02-27-2014 |
20140061947 | CHIP STACK STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip. | 03-06-2014 |
20140061948 | SENSOR PACKAGING METHOD AND SENSOR PACKAGES | 03-06-2014 |
20140061949 | HETEROGENEOUS ANNEALING METHOD AND DEVICE - A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts. | 03-06-2014 |
20140061950 | STACKABLE FLIP CHIP FOR MEMORY PACKAGES - In one embodiment, an electronic memory module may be provided to couple two or more stacked memory dies. The memory module may include a first substrate that couples the first memory die in a flip chip configuration. The substrate also includes connectors to couple to a second substrate, which has a flip chip connection to a second memory die. A surface of the first substrate opposite the flip chip connection of the first memory die may include connectors to couple to the first memory die (through the first substrate) and may include connectors to couple to the second memory die (through the connectors that couple to the second substrate, and through the first substrate. | 03-06-2014 |
20140061951 | PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a package on package structure includes the step of: providing a package body comprising a first package device and a connection substrate, the first package device comprising a number of first solder pads, the connection substrate comprising a substrate main body and a number of first electrically conductive posts, the first electrically conductive posts spatially corresponding to and being connected to the first solder pads, and a solder paste printed on each first electrically conductive post; attaching a second device on the second surface of the connection substrate, thereby obtaining a stacked structure, the second package device comprising a number of second solder pads; and solidifying the solder paste on each first electrically conductive post, such that each second solder pad is soldered to the corresponding first electrically conductive post using the solder paste, thereby obtaining a package on package structure. | 03-06-2014 |
20140070428 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 μm. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s. | 03-13-2014 |
20140084487 | PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGES - A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages. | 03-27-2014 |
20140084488 | MULTI-CHIP SEMICONDUCTOR DEVICE - A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces. The first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip are vertical to each other. | 03-27-2014 |
20140091479 | SEMICONDUCTOR DEVICE WITH STACKED SEMICONDUCTOR CHIPS - A semiconductor chip | 04-03-2014 |
20140097547 | SEMICONDUCTOR DEVICE - This invention is to improve noise immunity to the power supply and ground of a wiring board and a second semiconductor chip in an interior of a semiconductor device. A first semiconductor chip is mounted over a wiring board, and a second semiconductor chip is mounted in a central part located over the first semiconductor chip. Bottom surface electrodes of power and ground systems in the second semiconductor chip are led to their corresponding external coupling electrodes formed in the central part of the wiring board though chip through vias formed in the central part of the first semiconductor chip. The power and ground system bottom surface electrodes, the through vias and the external coupling electrodes are respectively arranged discretely from each other between the power and ground systems. | 04-10-2014 |
20140103542 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 04-17-2014 |
20140103543 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board. | 04-17-2014 |
20140103544 | SEMICONDUCTOR DEVICE - A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension. | 04-17-2014 |
20140110863 | Power Converter Package Including Vertically Stacked Driver IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 04-24-2014 |
20140110864 | CHIP ARRANGEMENT AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side. | 04-24-2014 |
20140124955 | PACKAGE-ON-PACKAGE STRUCTURE INCLUDING A THERMAL ISOLATION MATERIAL AND METHOD OF FORMING THE SAME - A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component. | 05-08-2014 |
20140124956 | SEMICONDUCTOR PACKAGE HAVING UNIFIED SEMICONDUCTOR CHIPS - A semiconductor package includes one or more semiconductor stack structures mounted on a package board. The semiconductor stack structures include sequentially stacked first to fourth semiconductor devices. Each of the first to fourth semiconductor devices includes a first unit semiconductor chip and a second unit semiconductor chip. The first unit semiconductor chip and the second unit semiconductor chip are unitary. A method for fabricating the semiconductor package includes forming pairs of unit semiconductor chips on a wafer, forming a scribe lane between the pairs of unit semiconductor chips, separating the pairs of unit semiconductor chips into semiconductor devices, each of the semiconductor devices having a corresponding one pair of unit semiconductor chips. | 05-08-2014 |
20140124957 | EXPANDED SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion. | 05-08-2014 |
20140124958 | SENSOR PACKAGING METHOD AND SENSOR PACKAGES | 05-08-2014 |
20140124959 | MEMORY DEVICE, LAMINATED SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller chip. The memory chips have a plurality of first wiring electrodes. The interposed chip has a plurality of second wiring electrodes. The second wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of a plurality of wiring electrodes for controller which are formed in the controller chip. The controller chip is laid on the interposed chip. | 05-08-2014 |
20140124960 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 05-08-2014 |
20140124961 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 05-08-2014 |
20140131894 | POP Structures with Air Gaps and Methods for Forming the Same - A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die. | 05-15-2014 |
20140131895 | MEMORY MODULE AND MEMORY SYSTEM - A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal. | 05-15-2014 |
20140138851 | SEMICONDUCTOR MEMORY CHIPS AND STACK-TYPE SEMICONDUCTOR PACKAGES INCLUDING THE SAME - Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first CA connection pads and second CA connection pads. The memory chip may be mounted on a top surface of the package substrate, the first CA connection pads may be connected to the first command/address pads, and the second CA connection pads may be provide to be opposite to the first CA connection pads and be connected to the second command/address pads. | 05-22-2014 |
20140138852 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element. | 05-22-2014 |
20140138853 | WAFER LEVEL PACKAGING BOND - A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection. | 05-22-2014 |
20140145352 | SEMICONDUCTOR PACKAGES AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad. | 05-29-2014 |
20140151904 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls. | 06-05-2014 |
20140159253 | CHIP STRUCTURE AND MULTI-CHIP STACK PACKAGE - A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern. | 06-12-2014 |
20140167291 | SEMICONDUCTOR PACKAGE HAVING SUPPORTING PLATE AND METHOD OF FORMING THE SAME - A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate. | 06-19-2014 |
20140175671 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element. | 06-26-2014 |
20140175672 | HYBRID SUBSTRATE WITH HIGH DENSITY AND LOW DENSITY SUBSTRATE AREAS, AND METHOD OF MANUFACTURING THE SAME - Provided is a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same. The hybrid substrate with high density and low density substrate areas includes a low density substrate layer having a cavity and a low density area, a high density substrate layer mounted in the cavity of the low density substrate layer and formed of a high density area having a higher pattern density than that of the low density area, an insulating support layer comprising a deposition area formed on upper portions, lower portions and the upper and lower portions of the high density substrate layer and the low density substrate layer, insulating layer vias passing through the deposition area of the insulating support layer and connected to patterns of the high density substrate layer and the low density substrate layer, and an outer pattern layer. | 06-26-2014 |
20140175673 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads. | 06-26-2014 |
20140175674 | Package on Package Device - The present invention provides a package on package device. At least two components are sequentially soldered with each other. A size of a base plate of a component located below is greater than a size of an edge of a component located above. In the case of a package on package device, the size of the base plate of the component located below is greater than the size of the edge of the component located above. | 06-26-2014 |
20140175675 | DEVICES AND METHODS FOR STACKING INDIVIDUALLY TESTED DEVICES TO FORM MULTI-CHIP ELECTRONIC MODULES - A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed. | 06-26-2014 |
20140183758 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, BLOCK STACKED BODY, AND SEQUENTIAL STACKED BODY - A method of manufacturing a semiconductor device is provided which is capable of improving productivity and reliability. The method of manufacturing a semiconductor device ( | 07-03-2014 |
20140191417 | Multi-Chip Package Assembly with Improved Bond Wire Separation - A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances. | 07-10-2014 |
20140191418 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 07-10-2014 |
20140191419 | 3D INTEGRATED CIRCUIT PACKAGE WITH WINDOW INTERPOSER - 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die. | 07-10-2014 |
20140197547 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector. | 07-17-2014 |
20140203456 | Pre-Applying Supporting Materials between Bonded Package Components - A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material. | 07-24-2014 |
20140210106 | ULTRA THIN PoP PACKAGE - A PoP (package-on-package) package includes a bottom package coupled to a top package. The bottom package includes a die coupled to an interposer layer with an adhesive layer. One or more terminals are coupled to the interposer layer on the periphery of the die. The terminals and the die are at least partially encapsulated in an encapsulant. The terminals and the die are coupled to a redistribution layer (RDL). Terminals on the bottom of the RDL are used to couple the PoP package to a motherboard or a printed circuit board (PCB). One or more additional terminals couple the interposer layer to the top package. The additional terminals may be located anywhere along the surface of the interposer layer. | 07-31-2014 |
20140210107 | STACKED WAFER DDR PACKAGE - A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die. | 07-31-2014 |
20140210108 | SEMICONDUCTOR PACKAGE - A semiconductor package offers improved product reliability by supplying a power voltage and a ground voltage to a semiconductor chip in a secured manner using a redistribution layer (RDL) structure. The semiconductor package includes a first semiconductor chip disposed on a substrate, a second semiconductor chip disposed on the first semiconductor chip, a plurality of redistribution lines disposed on the first semiconductor chip and electrically connecting the first semiconductor chip to the second semiconductor chip, and a redistribution wire disposed on the first semiconductor chip and electrically connecting one of the redistribution lines to another. | 07-31-2014 |
20140217613 | INTEGRATED DEVICE AND FABRICATION PROCESS THEREOF - An integrated device includes a die attach pad, a main die, a stacked die, and a mold compound. The main die has a first (e.g., bottom) surface attached to the die attach pad and has a second (e.g., top) surface. The stacked die is attached to the second surface of the main die using, for example, an adhesive film. The main die and the stacked die include silicon crystal. The mold compound encapsulates the die attach pad, the main die, and the stacked die. | 08-07-2014 |
20140217614 | INTEGRATED CIRCUIT FILM AND METHOD OF MANUFACTURING THE SAME - An integrated circuit film and a method of manufacturing the same are disclosed. The integrated circuit film includes a circuit board containing a circuit route; a first set of pads located on a first surface of the circuit board and configured to be applicable to ISO 7816 standard; and a semiconductor device mounted on the circuit board for communicating with at least one of the first set of pads. The first set of pads are arranged in two rows and the semiconductor device is mounted on the circuit board in a space between the two rows of pads. | 08-07-2014 |
20140217615 | METHOD OF MAKING A SYSTEM-IN-PACKAGE DEVICE, AND A SYSTEM-IN-PACKAGE DEVICE - A method of making a system-in-package device, and a system-in-package device is disclosed. In the method, at least one first species die with predetermined dimensions, at least one second species die with predetermined dimensions, and at least one further component of the system-in-device is included in the system-in package device. At least one of the first and second species dies is selected for redimensioning, and material is added to at least one side of the selected die such that the added material and the selected die form a redimensioned die structure. A connecting layer is formed on the redimensioned die structure. The redimensioned die structure is dimensioned to allow mounting of the non-selected die and the at least one further component into contact with the redimensioned die structure via the connecting layer. | 08-07-2014 |
20140217616 | STACK PACKAGE AND METHOD OF MANUFACTURING STACK PACKAGE - A stack package includes a first semiconductor chip having a plurality of first pads, and a second semiconductor chip stacked on the first semiconductor chip and having a plurality of second pads corresponding to the first pads respectively, the second pads connected to the corresponding first pads. The first and second pads are arranged such that the first and second pads overlap with each other even after the first and second semiconductor chips are rotated relative to each other by a predetermined angle. | 08-07-2014 |
20140232015 | Semiconductor Modules and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant. | 08-21-2014 |
20140232016 | SEMICONDUCTOR DEVICE - This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices. | 08-21-2014 |
20140239513 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS - A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, first and second microelectronic elements, and leads extending from contacts exposed at respective front surfaces of the first and second microelectronic elements to central terminals exposed at the central region. The front surface of the first microelectronic element can face the second surface of the dielectric element. The front surface of the second microelectronic element can face a rear surface of the first microelectronic element. The contacts of the second microelectronic element can project beyond an edge of the first microelectronic element. At least first and second ones of the leads can electrically interconnect a first central terminal of the central terminals with each of the first and second microelectronic elements. | 08-28-2014 |
20140246787 | SEMICONDUCTOR APPARATUS - According to one embodiment, a semiconductor apparatus includes a substrate, a first semiconductor chip, a second semiconductor chip and a first converter. The first semiconductor chip includes a first surface and a second surface and is mounted on the substrate, the first surface is opposed to the substrate, the second surface is opposed to the first surface. The second semiconductor chip includes a first area and is stacked on the second surface. The first converter is arranged in the first area, the first converter is configured to perform at least one of analog-to-digital conversion and digital-to-analog conversion and arranged in the first area. A part of the first area does not overlap the first semiconductor chip when viewed from a direction perpendicular to the second surface. | 09-04-2014 |
20140246788 | STACK-TYPE SEMICONDUCTOR PACKAGE - Provided is a stack-type semiconductor package comprising a first semiconductor package with a first package substrate and a logic chip mounted thereon, a second semiconductor package including a second package substrate disposed on the first semiconductor package and first and second memory chips stacked on the second package substrate, and connection pads disposed between the first and second package substrates to connect the first and second semiconductor packages electrically to each other. The first package substrate has first and second edges that are substantially perpendicular to each other. The first package substrate may include first DQ connection pads electrically connected to the first memory chip, and second DQ connection pads electrically connected to the second memory chip. The first DQ connection pads may be arranged adjacent to the first edge and the second DQ connection pads may be arranged adjacent to the second edge. | 09-04-2014 |
20140252655 | FAN-OUT AND HETEROGENEOUS PACKAGING OF ELECTRONIC COMPONENTS - Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate. | 09-11-2014 |
20140252656 | SEMICONDUCTOR PACKAGE - A semiconductor package, comprising: a substrate; a first semiconductor chip; and at least one second semiconductor chip. The first semiconductor chip and the at least one second semiconductor chip are stacked on the substrate; the first semiconductor chip is electrically connected with the substrate; and an electrical connection of each second semiconductor chip is formed through a secondary input/output buffer of the first semiconductor chip. | 09-11-2014 |
20140264944 | Semiconductor Package with Top-Side Insulation Layer - A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector. | 09-18-2014 |
20140264945 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package. | 09-18-2014 |
20140264946 | PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT - To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window. | 09-18-2014 |
20140264947 | Interconnect Apparatus and Method - A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask. | 09-18-2014 |
20140264948 | Air Trench in Packages Incorporating Hybrid Bonding - A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench. | 09-18-2014 |
20140284817 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment a method is provided including positioning and bonding a plurality of first semiconductor chips in a coplanar relation on a first substrate, laminating at least a plurality of second semiconductor chips on the first semiconductor chips, cutting the first substrate for separation into a discrete chip lamination, aligning an electrode pad provided on a surface of the discrete lamination with an electrode pad on a second substrate, and temporarily connecting the electrode pads on the lamination and the second substrate in an opposing relation to the first substrate, providing electrical connection between the electrode pads by a reflow process, flowing a liquid resin from the side of the first substrate towards the second substrate to seal the chip lamination and spaces between the chip lamination and the first and second substrate, and cutting the chip lamination to form a discrete device. | 09-25-2014 |
20140291866 | EMBEDDED DIE-DOWN PACKAGE-ON-PACKAGE DEVICE - An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate. | 10-02-2014 |
20140291867 | APPARATUS AND METHOD TO ATTACH A WIRELESS COMMUNICATION DEVICE INTO A SEMICONDUCTOR PACKAGE - A semiconductor package includes an RFID chip positioned between a first die and a second die attached to a support substrate. The RFID chip is free of electrical connections to the dice and the support substrate. The RFID chip is sized to correspond to an interposer board. Data pertaining to operating characteristics of the dice are stored to and read from the RFID chip during back-end processing to determine abnormalities and improve yield. Said data may be stored to a database corresponding to the RFID chip in the package. A method of making a semiconductor package having an RFID chip positioned between dice is provided. The package is traceable by customers via the data stored to the RFID chip and the database. | 10-02-2014 |
20140291868 | STACK TYPE SEMICONDUCTOR PACKAGE - A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector. | 10-02-2014 |
20140306354 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type. | 10-16-2014 |
20140312510 | Semiconductor Device - The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other. | 10-23-2014 |
20140312511 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature. | 10-23-2014 |
20140319701 | SEMICONDUCTOR CHIP AND A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) STRUCTURE INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate. | 10-30-2014 |
20140319702 | Stackable Package by Using Internal Stacking Modules - A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate. | 10-30-2014 |
20140327155 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip mounted on a surface of the lower substrate, connection terminals between the lower substrate and the lower semiconductor chip, and a protection film covering the lower semiconductor chip. An upper package is spaced apart from the lower package on an upper surface of the lower substrate, the upper package comprising an upper substrate and an upper semiconductor chip. Connections are present between the lower substrate and the upper substrate to horizontally surround the lower semiconductor chip. A molding film is on the upper surface of the lower substrate to fill spaces between the connection terminals and the connections. An uppermost surface of the protection film is positioned at substantially a same vertical level as an uppermost surface of the molding film and is spaced apart from the upper package. | 11-06-2014 |
20140327156 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package may include a substrate, a lower semiconductor chip disposed on an inner surface of the substrate, and an upper semiconductor chip disposed on the lower semiconductor chip. A plurality of connection terminals may be disposed between the substrate and the lower semiconductor chip to electrically connect the lower semiconductor chip to the substrate. The upper semiconductor chip may have a lower surface which faces the substrate and an upper surface which opposes the lower surface. Bonding wires may pass through the windows to connect the lower surface of the upper semiconductor chip to an outer surface of the substrate. | 11-06-2014 |
20140327157 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip. | 11-06-2014 |
20140332982 | Stacked Packages and Microelectronic Assemblies Incorporating the Same - A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position. | 11-13-2014 |
20140332983 | STACKED CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided. | 11-13-2014 |
20140339708 | SEMICONDUCTOR PACKAGE DEVICE - A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package. | 11-20-2014 |
20140346683 | STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING STACKED MICROELECTRONIC DEVICES - Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die. | 11-27-2014 |
20140353847 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a plurality of lead members disposed with a space therebetween over a surface of a substrate, a first semiconductor chip disposed in a face-up manner over the first surface of the substrate between at least two of the plurality of lead members; a second semiconductor chip disposed in a face-up manner over the first semiconductor chip and the at least two lead members, and a connection member for connecting the substrate, the at least two lead members, the first semiconductor chip and the second semiconductor chip with one another. | 12-04-2014 |
20140361441 | STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME - A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors. | 12-11-2014 |
20140361442 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package. | 12-11-2014 |
20140367865 | LEADLESS INTEGRATED CIRCUIT PACKAGE HAVING STANDOFF CONTACTS AND DIE ATTACH PAD - A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material. | 12-18-2014 |
20140367866 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. | 12-18-2014 |
20140367867 | Packaging Methods and Packaged Semiconductor Devices - An embodiment is a method including forming a first package and a second package. The first package includes packaging a first die, forming a plurality of solder balls on the first die, and coating the plurality of solder balls with an epoxy flux. The second package includes forming a first electrical connector, attaching a second die adjacent the first electrical connector, forming a interconnect structure over the first die and the first electrical connector, the interconnect structure being a frontside of the second package, forming a second electrical connector over the interconnect structure, and the second electrical connector being coupled to both the first die and the first electrical connector. The method further includes bonding the first package to the backside of the second package with the plurality of solder balls forming a plurality of solder joints, each of the plurality of solder joints being surrounded by the epoxy flux. | 12-18-2014 |
20140374921 | Ball Height Control in Bonding Process - A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component. | 12-25-2014 |
20140374922 | Alignment in the Packaging of Integrated Circuits - A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package. | 12-25-2014 |
20140374923 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM - Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip ID signal generation unit configured to generate a chip ID signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip ID signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip ID signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal. | 12-25-2014 |
20140374924 | Heterogeneous Integration Process Incorporating Layer Transfer in Epitaxy Level Packaging - Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes. | 12-25-2014 |
20150008592 | Method for Carbon Nanofiber Alignment Using Magnetic Nanoparticles - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The chip stack further includes a thermal interface material pad between the first chip and the second chip. The thermal interface material pad comprises a plurality of nanotubes containing a magnetic material, aligned parallel to mating surfaces of the first chip and the second chip, wherein a hydrophobic tail of oleic acid is wrapped around each one of the plurality of nanotubes and a hydrophilic acid head of the oleic acid is attached to the magnetic material. | 01-08-2015 |
20150008593 | STACKED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor device includes a first substrate and a second substrate. The first electrode is connected to the second electrode so that the first surface faces the second surface. A tip portion of the first wall section that faces the second substrate is connected to a tip portion of the second wall section that faces the first substrate. The first wall section is connected to the second wall section over an entire circumference. An outside space that is formed in an outside of the first wall section and an outside of the second wall section between the first substrate and the second substrate is filled with a sealing member over the entire circumference. | 01-08-2015 |
20150008594 | SEMICONDUCTOR PACKAGES - A semiconductor package may include a first substrate, a second substrate facing the first substrate, a plurality of first electrical connections disposed between the first substrate and the second substrate, and a first material disposed between the first substrate and the second substrate. The plurality of first electrical connections may electrically couple the first substrate and the second substrate to each other. The first material may surround each of the plurality of first electrical connections, and a width of the first material proximal the first substrate may be smaller than a width of the first material proximal the second substrate. | 01-08-2015 |
20150014863 | Dam Structure for Enhancing Joint Yield in Bonding Processes - A package structure includes a bottom package component, a top package component overlying and bonded to the bottom package component, and a dam between the bottom package component and the top package component. The dam has a top surface attached to a bottom surface of the top package component, and a bottom surface spaced apart from a top surface of the bottom package component. | 01-15-2015 |
20150021791 | SEMICONDUCTOR DEVICE - Various aspects of the present disclosure provide a semiconductor device and a method for manufacturing thereof, which can facilitate stacking of semiconductor die while saving manufacturing cost. In an example embodiment, the semiconductor device may comprise a first semiconductor die, a second semiconductor die bonded to a top surface of the first semiconductor die, and a redistribution layer electrically connecting the first semiconductor die to the second semiconductor die, wherein the redistribution layer is formed to extend along surrounding side portions of the second semiconductor die. | 01-22-2015 |
20150028496 | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure - A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die. | 01-29-2015 |
20150035170 | MULTICHIP DEVICE INCLUDING A SUBSTRATE - A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material. | 02-05-2015 |
20150048520 | MAGNETIC CONTACTS - Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed. | 02-19-2015 |
20150048521 | SEMICONDUCTOR PACKAGE - According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package. | 02-19-2015 |
20150048522 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip. | 02-19-2015 |
20150048523 | CHIP-ON-WAFER BONDING METHOD AND BONDING DEVICE, AND STRUCTURE COMPRISING CHIP AND WAFER - [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween. | 02-19-2015 |
20150048524 | STACKED MICROELECTRONIC PACKAGES HAVING AT LEAST TWO STACKED MICROELECTRONIC ELEMENTS ADJACENT ONE ANOTHER - A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element. | 02-19-2015 |
20150061157 | HIGH YIELD SEMICONDUCTOR DEVICE - A semiconductor device including two or more die stacks mounted to a substrate. The first die stack is mounted, at least partially encapsulated, and then tested. If the first die stack functions within predefined parameters, a second die stack is mounted on the first die stack, and then the device may undergo a second encapsulation process. Testing the first die stack before mounting the second improves yield by identifying faulty semiconductor die before all die are mounted within the semiconductor device. | 03-05-2015 |
20150069631 | ALLEVIATION OF THE CORROSION PITTING OF CHIP PADS - Methods for processing a metal pad of a chip and chip structures including a chip with a metal pad. A surface modification agent is applied to the metal pad on the chip. The surface modification agent is effective to increase the hydrophobicity of the metal pad and may involve silylation. | 03-12-2015 |
20150069632 | SEMICONDUCTOR PACKAGE - According to one embodiment, a semiconductor package includes a substrate with first and second pad, first semiconductor chip above the substrate, first wire, first mold member, second semiconductor chip above the first mold member, third semiconductor chip above the second semiconductor chip, second wire, and a second mold member. The first wire electrically connects the first pad and the first semiconductor chip. The first mold member seals the first wire and the first semiconductor chip. The second wire electrically connects the second pad and the second semiconductor chip. The second mold member seals the second wire, the second and the third semiconductor chips, and the first mold member. | 03-12-2015 |
20150069633 | SEMICONDUCTOR DEVICE AND MEMORY DEVICE - A semiconductor device includes a substrate, a controller chip, and memory chips. Wiring is formed on the substrate. The controller chip has a rectangular surface area, and is mounted on the substrate. The memory chips have quadrangular surface areas, and are superposed on the substrate on a first major side of the controller chip. The first major side defines a first direction and a first controller terminal block is formed along a first minor side thereof orthogonal to the first direction, and a second controller terminal block is formed along a second major side opposite to the first major side. | 03-12-2015 |
20150069634 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip. | 03-12-2015 |
20150069635 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern. | 03-12-2015 |
20150069636 | MULTIPLE ACCESS OVER PROXIMITY COMMUNICATION - A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code. | 03-12-2015 |
20150084209 | SEMICONDUCTOR DEVICE - A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided. | 03-26-2015 |
20150097299 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided. | 04-09-2015 |
20150102505 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The method may include mounting a lower stack including a plurality of lower semiconductor chips on a substrate and mounting an upper stack including a plurality of upper semiconductor chips on the lower stack. According to example embodiments of the inventive concept, the semiconductor package can be easily fabricated. | 04-16-2015 |
20150102506 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING - The semiconductor package includes: a package substrate comprising a bonding pad; a plurality of semiconductor chips stacked on the package substrate; and a bonding wire configured to electrically connect the semiconductor chips and the bonding pad. For at least one of the plurality of semiconductor chips: the semiconductor chip comprises: a semiconductor device; a first pad electrically connected to the semiconductor device; a conductive pattern; and a second pad electrically connected to the first pad, spaced apart from the conductive pattern, and extending over the conductive pattern; and the bonding wire is connected to the second pad. | 04-16-2015 |
20150102507 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip. | 04-16-2015 |
20150102508 | STACKED PACKAGING IMPROVEMENTS - A plurality of microelectronic assemblies ( | 04-16-2015 |
20150102509 | SEMICONDUCTOR DEVICE HAVING STACKED MEMORY ELEMENTS AND METHOD OF STACKING MEMORY ELEMENTS ON A SEMICONDUCTOR DEVICE - A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner. | 04-16-2015 |
20150108661 | MICROELECTRONIC PACKAGES CONTAINING STACKED MICROELECTRONIC DEVICES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack. | 04-23-2015 |
20150108662 | PACKAGE MODULE WITH OFFSET STACK DEVICE - A package module with offset stacked device is provided which includes a group of stacked device, a carrier and a substrate. The group of stacked device is offset stacked to dispose in the carrier and the substrate is disposed on the bottom of the carrier. A plurality of electric connections is disposed on the surface substrate that is opposite to the carrier. A plurality of outer connections on another surface of the substrate is electrically connected with the plurality of electric connections. The group of the stacked device is electrically connected with the carrier by the connecting the plurality of metal connections and the pads. The plurality of metal connections is extended to the bottom of the carrier to form another metal connection to electrically connect with the electric connection on the substrate. | 04-23-2015 |
20150108663 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package. | 04-23-2015 |
20150115472 | CO-SUPPORT FOR XFD PACKAGING - A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements. | 04-30-2015 |
20150115473 | HETEROGENEOUS CHANNEL MATERIAL INTEGRATION INTO WAFER - Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device. | 04-30-2015 |
20150115474 | WIREBOND RECESS FOR STACKED DIE - A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack. | 04-30-2015 |
20150115475 | DEVICE INCLUDING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SUCH DEVICE - A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip. | 04-30-2015 |
20150115476 | Module with Stacked Package Components - A module with stack package components includes: at least a package component in a loader. Moreover, each package components includes at least a chip. Package components stacks in the loader. The package components connect with the loader by metal connecters and wire. These package components are placed to make the loader be the module with stack package components. The module connects with some sockets by other metal connecters. | 04-30-2015 |
20150115477 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES - A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture. | 04-30-2015 |
20150123287 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE AND PACKAGING STRUCTURE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween. | 05-07-2015 |
20150123288 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor package includes semiconductor chips, each chip having one or more bonding pads. The semiconductor chips are stacked in a stepped configuration over the surface of the substrate without covering one or more bonding pads. An encapsulation member encapsulates the stacked semiconductor chips on the surface of the substrate. Via wirings in the encapsulation member electrically connect to a bonding pad of at least one of the semiconductor chips. Redistributions are formed over the encapsulation member such that the one or more redistributions are electrically coupled to the via wirings. | 05-07-2015 |
20150123289 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package, the semiconductor package includes a first substrate, a first semiconductor chip which is mounted on the first substrate, a second substrate which is disposed on the first semiconductor chip, at least one second semiconductor chip which is disposed on the second substrate; and a plurality of wires which are in contact with the first substrate and the second substrate to connect the first substrate and the second substrate to each other. | 05-07-2015 |
20150123290 | SEMICONDUCTOR PACKAGES HAVING TRENCH-SHAPED OPENING AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor packages and methods of fabricating the same. In one embodiment, the package may include an upper package stacked on a lower package, and a plurality of connection terminals electrically connecting the lower and upper packages. The lower package may include a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer provided on the lower package substrate to mold the lower semiconductor chip. The lower mold layer may have a trench-shaped first opening through which the lower package substrate is exposed in a substantially line shape. The connection terminals may be electrically connected to the lower package substrate exposed by the first opening and be not in contact with the lower mold layer. | 05-07-2015 |
20150130082 | Configurable Routing for Packaging Applications - Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof. | 05-14-2015 |
20150130083 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip. | 05-14-2015 |
20150137389 | SEMICONDUCTOR PACKAGE - An embodiment includes a semiconductor package comprising: a substrate; a semiconductor chip package unit disposed on the substrate, the semiconductor chip package unit comprising: a first semiconductor chip; a first encapsulating material layer encapsulating the first semiconductor chip; a plurality of connection pads formed on an upper surface of the first encapsulating material layer, at least one of the connection pads being electrically connected to the first semiconductor chip; and a re-wiring layer extending on an upper surface of the semiconductor chip and the upper surface of the first encapsulating material layer, the re-wiring layer being electrically connected to the first semiconductor chip and at least one of the connection pads; and a second semiconductor chip stacked on an upper surface of the semiconductor chip package unit, wherein the second semiconductor chip exposes the connection pads and is electrically connected to one or more of the at least one of the connection pads electrically connected to the first semiconductor chip. | 05-21-2015 |
20150145147 | Apparatus and Method for Increasing Bandwidths of Stacked Dies - A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies. | 05-28-2015 |
20150294940 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING SEMICONDUCTOR DEVICES - Semiconductor devices may include a substrate and a semiconductor die on the substrate. The semiconductor die may include an active surface and a lateral edge at a periphery of the active surface. An electrically insulating material may be located on the active surface proximate the lateral edge. The electrically insulating material may be distinct from any other material located on the active surface. A wire bond may extend from the active surface, over the electrically insulating material, to the substrate. Methods of making semiconductor devices may involve positioning an electrically insulating material on an active surface of a semiconductor die proximate a lateral edge at a periphery of an active surface. After positioning the electrically insulating material on the active surface, a wire bond extending from the active surface, over the electrically insulating material, to the substrate may be formed. | 10-15-2015 |
20150294955 | Stacked Semiconductor Structure and Method - A method for forming a stacked semiconductor structure comprises providing a first chip comprising a plurality of first active circuits and a first aluminum connection pad, depositing a first dielectric layer on a first side of the first chip, forming a first copper bonding pad on the first aluminum connection pad, providing a second chip comprising a plurality of second active circuits, depositing a second dielectric layer on a first side of the second chip, forming a second copper bonding pad in the second dielectric layer, stacking the first chip on the second chip, wherein the first copper bonding pad is in direct contact with the second copper bonding pad and bonding the first chip and the second chip to form a uniform bonded feature. | 10-15-2015 |
20150303122 | COMPOSITE COMPOSITIONS FOR ELECTRONICS APPLICATIONS - An electronics composition includes a curable matrix material and, optionally, a filler material disposed within the matrix material. The cured matrix material includes an oligomer or polymer material derived from a compound selected from a methylene malonate monomer, a multifunctional methylene monomer, a methylene beta ketoester monomer, a methylene beta diketone monomer, or a mixture thereof. | 10-22-2015 |
20150303175 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad. | 10-22-2015 |
20150303176 | MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE - An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. Discrete conductive elements are extended between the active surface of the first semiconductor device and the substrate prior to positioning of the second semiconductor device. Intermediate portions of the discrete conductive elements pass through an aperture formed between the active surface of the first semiconductor device, the back side of the second semiconductor device, and two of the spacers positioned therebetween. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 10-22-2015 |
20150311175 | STACKED CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided. | 10-29-2015 |
20150311183 | WAFER, PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure. | 10-29-2015 |
20150311186 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die. | 10-29-2015 |
20150318265 | SEMICONDUCTOR DEVICE - One semiconductor device has a wiring substrate, a first semiconductor chip, and a second semiconductor chip. Each semiconductor chip includes a first side and a third side which are opposed, a second side which is perpendicular to the first side, and a fourth side opposing the second side. A first electrode (CA electrode pad) parallel to the first side, and a second electrode (I/O electrode pad) arranged parallel to the second side near the second side, are provided on the first semiconductor chip. A third electrode (CA electrode pad) parallel to the first side, and a fourth electrode (I/O electrode pad) arranged parallel to the fourth side near the fourth side, are provided on the second semiconductor chip. | 11-05-2015 |
20150318269 | Method for Carbon Nanotube Alignment Using Magnetic Nanoparticles - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The chip stack further includes a thermal interface material pad between the first chip and the second chip. The thermal interface material pad comprises a plurality of nanotubes containing a magnetic material, aligned parallel to mating surfaces of the first chip and the second chip, wherein a hydrophobic tail of oleic acid is wrapped around each one of the plurality of nanotubes and a hydrophilic acid head of the oleic acid is attached to the magnetic material. | 11-05-2015 |
20150325556 | PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement. | 11-12-2015 |
20150333038 | SEMICONDUCTOR DEVICE INCLUDING FILLING MATERIAL PROVIDED IN SPACE DEFINED BY THREE SEMICONDUCTOR CHIPS - A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each other, a third semiconductor chip mounted on the first and second semiconductor chips, first and second adhesive layers that are provided between the first and second semiconductor chips and the wiring substrate so as to bond the first and second semiconductor chips to the wiring substrate, and a third adhesive layer that is provided between the third semiconductor chip and the first and second semiconductor chips so as to bond the third semiconductor chip to the first and second semiconductor chips, with its thickness being made thicker than that of the first and second adhesive layers, a sealing layer covering the wiring substrate, and a filling layer that is provided between the first and second semiconductor chips and is different from the sealing layer. | 11-19-2015 |
20150333042 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 11-19-2015 |
20150340340 | SEMICONDUCTOR DEVICE - In a semiconductor device ( | 11-26-2015 |
20150340349 | Package on Package Structure - A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit. | 11-26-2015 |
20150357311 | MAGNETIC CONTACTS - Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed. | 12-10-2015 |
20150364363 | VHF ETCH BARRIER FOR SEMICONDUCTOR INTEGRATED MICROSYSTEM - The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die. | 12-17-2015 |
20150364450 | CO-SUPPORT FOR XFD PACKAGING - A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements. | 12-17-2015 |
20150371968 | MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES - A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate. | 12-24-2015 |
20150371969 | METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES - Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping. | 12-24-2015 |
20150380383 | METHOD FOR CARRYING OUT A CONDUCTIVE DIRECT METAL BONDING - A method includes a) Providing a first substrate covered by a metal layer and a second substrate covered by a metal layer, b) Bringing into direct contact the metal layers so as to form a bonding interface having metal material bridges separated by cavities which are fluidly connected to each other, d) Immersing the bonding interface in an oxidizing fluid so as to form a metal oxide which fills at least in part the cavities and metal/metal oxide/metal contact areas. A structure is also provided having a first substrate, a first metal layer, a second metal layer forming a bonding layer with the first metal layer, and a second substrate, the bonding interface having: metal material bridges separated by cavities, a metal oxide partially filling the cavities, and metal/metal oxide/metal contact areas. | 12-31-2015 |
20150380392 | PACKAGE WITH MEMORY DIE AND LOGIC DIE INTERCONNECTED IN A FACE-TO-FACE CONFIGURATION - A semiconductor device package includes a logic die coupled to a memory die in a face-to-face configuration with small interconnect pitch (at most about 50 μm) and small distances between the die (at most about 50 μm). The logic die may be connected to a redistribution layer with terminals that are fanned out, or spaced out, to provide space for the face-to-face connections to the memory die. The memory die may be connected to the logic die before or after the logic die is connected to the redistribution layer. The logic die and the memory die may be at least partially encapsulated in an encapsulant. Routing in the redistribution layer may connect the logic die and/or the memory die to ball grid array terminals coupled to the bottom of the redistribution layer and/or discrete devices coupled to the redistribution layer. | 12-31-2015 |
20160005696 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - One semiconductor device includes a wiring substrate, a semiconductor chip layered on one face of the wiring substrate and having a first face facing the wiring substrate and a second face positioned on a reverse side from the first face, a circuit being formed on at least the second face, a non-circuit-incorporating chip in which a circuit is not formed, the non-circuit-incorporating chip being layered on the second face of the semiconductor chip, and a sealing resin disposed between at least the wiring substrate and the non-circuit-incorporating chip. | 01-07-2016 |
20160005714 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region. | 01-07-2016 |
20160013076 | THREE DIMENSIONAL PACKAGE ASSEMBLIES AND METHODS FOR THE PRODUCTION THEREOF | 01-14-2016 |
20160013154 | SEMICONDUCTOR DEVICES COMPRISING PROTECTED SIDE SURFACES AND RELATED METHODS | 01-14-2016 |
20160013156 | PACKAGE-ON-PACKAGE OPTIONS WITH MULTIPLE LAYER 3-D STACKING | 01-14-2016 |
20160027761 | ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES - Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly. | 01-28-2016 |
20160035394 | Discrete Three-Dimensional Memory - The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. | 02-04-2016 |
20160035395 | Discrete Three-Dimensional Vertical Memory - The present invention discloses a discrete three-dimensional vertical memory (3D-M | 02-04-2016 |
20160035698 | STACK PACKAGE - A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack. | 02-04-2016 |
20160035703 | DIE STACKING TECHNIQUES IN BGA MEMORY PACKAGE FOR SMALL FOOTPRINT CPU AND MEMORY MOTHERBOARD DESIGN - A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate. | 02-04-2016 |
20160035706 | SEMICONDUCTOR DEVICE FOR BATTERY POWER VOLTAGE CONTROL - A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips. | 02-04-2016 |
20160035708 | STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME - A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors. | 02-04-2016 |
20160049349 | SYSTEMS AND METHODS FOR THERMAL DISSIPATION - A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package. | 02-18-2016 |
20160064360 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad. | 03-03-2016 |
20160064365 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate having a lower substrate and an upper substrate disposed on the lower substrate, the package substrate having a first cavity, a first semiconductor chip disposed in the first cavity, and a chip stack disposed to partially cover the first cavity on the upper substrate. | 03-03-2016 |
20160071825 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE - A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability. | 03-10-2016 |
20160079135 | SEMICONDUCTOR PACKAGING HAVING WARPAGE CONTROL AND METHODS OF FORMING SAME - An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound. | 03-17-2016 |
20160093599 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip and a second semiconductor chip, and wherein the first semiconductor chip includes a plurality of first bonding pads, and the second semiconductor chip includes a plurality of second bonding pads for coupling respectively to the first bonding pads by wire-bonding coupling and at least one third bonding pad for enabling relay coupling of a corresponding second bonding pad to at least one predetermined first bonding pad which is arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling. | 03-31-2016 |
20160093601 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy. | 03-31-2016 |
20160099213 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating layer on a first surface of the package substrate, a first interconnection layer on the first insulating layer, a second insulating layer on a second surface of the package substrate opposite the first surface, and a second interconnection layer on the second insulating layer. | 04-07-2016 |
20160126217 | SYSTEMS, METHODS AND DEVICES FOR INTER-SUBSTRATE COUPLING - Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets. | 05-05-2016 |
20160133598 | DIRECT METAL BONDING METHOD - Method including the steps of a) Providing a first stack including a first substrate on which is deposited a first metal layer including a first metal, and a first solubilization layer distinct from the first metal layer, the first solubilization layer including a first getter material configured to solubilize the oxygen, b) Providing a second stack including a second substrate on which is deposited a second metal layer including a second metal, c) Contacting the first metal layer and the second metal layer so as to obtain a direct metal bonding between the first metal layer and the second metal layer, and d) Applying a heat treatment for annealing the bonding. | 05-12-2016 |
20160141272 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device which is provided with: a wiring substrate which has a first region, and a relay pad and a connection pad that are arranged outside the first region; a first semiconductor chip which has an electrode pad that is formed on one surface, and which is mounted on the first region of the wiring substrate; a first wire that connects the electrode pad and the relay pad with each other; and a second wire that connects the relay pad and the connection pad with each other. | 05-19-2016 |
20160148904 | 3D INTEGRATION OF FANOUT WAFER LEVEL PACKAGES - Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer. | 05-26-2016 |
20160148914 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing a semiconductor package are provided. The semiconductor package includes a first substrate having electrodes are disposed on both surfaces thereof, one or more first elements mounted on a first surface of the first substrate, a first insulating member comprising an insulating material disposed on a first surface of the first substrate and affixing one or more first elements to the first surface of the first substrate, and one or more second elements mounted on a second surface of the first substrate. At least a portion of the first elements is externally exposed from the first insulating member. | 05-26-2016 |
20160163662 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding. | 06-09-2016 |
20160172336 | INDEPENDENT CONTROL OF STACKED ELECTRONIC MODULES | 06-16-2016 |
20160172338 | SILICON PACKAGE FOR EMBEDDED ELECTRONIC SYSTEM HAVING STACKED SEMICONDUCTOR CHIPS | 06-16-2016 |
20160172345 | Multi-Chips in System level and Wafer level Package Structure | 06-16-2016 |
20160180013 | METHOD FOR DESIGNING VEHICLE CONTROLLER-ONLY SEMICONDUCTOR BASED ON DIE AND VEHICLE CONTROLLER-ONLY SEMICONDUCTOR BY THE SAME | 06-23-2016 |
20160181214 | STACKED MEMORY CHIP HAVING REDUCED INPUT-OUTPUT LOAD, MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME | 06-23-2016 |
20160190103 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor devise includes a first substrate and a second substrate which are bonded each other. A first substrate includes an insulating first surface film as an uppermost layer, a first electrode and an insulating second surface film respectively formed inside a plurality of openings in the first surface film, and a first seal ring. A second substrate includes an insulating third surface film as an uppermost layer, and a second electrode, an insulating fourth surface film respectively formed inside a plurality of openings in the third surface film, and a second seal ring. The first electrode and the second electrode are directly bonded together. The first surface film and the third surface film are directly bonded together. The second surface film and the fourth surface film are directly bonded together. A seal ring formed of the first seal ring, the second surface film, the fourth surface film, and the second seal ring is continuous between the first substrate and the second substrate. | 06-30-2016 |
20160379952 | DIE PACKAGING WITH FULLY OR PARTIALLY FUSED DIELECTRIC LEADS - A die interconnect system having a first die with a plurality of connection pads, and a ribbon lead extending from the first die, the ribbon lead having a plurality of metal cores with a core diameter, and a dielectric layer surrounding the metal core with a dielectric thickness, with at least a portion of dielectric being fused between adjacent metal cores along the length of the plurality of metal cores, and an outer metal layer attached to ground. | 12-29-2016 |
20170233599 | INKJET ADHESIVE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC COMPONENT | 08-17-2017 |
20170236809 | CHIP PACKAGE ASSEMBLY WITH POWER MANAGEMENT INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT DIE | 08-17-2017 |
20180025967 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES | 01-25-2018 |
20180026067 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR (CIS) PACKAGE WITH AN IMAGE BUFFER | 01-25-2018 |
20190148227 | RLINK-ON-DIE INTERCONNECT FEATURES TO ENABLE SIGNALING | 05-16-2019 |
20190148338 | SEMICONDUCTOR DEVICE ASSEMBLIES WITH MOLDED SUPPORT SUBSTRATES | 05-16-2019 |
20220139873 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a lower semiconductor chip having a lower semiconductor substrate and upper pads on a top surface of the lower semiconductor substrate, an upper semiconductor chip stacked on the lower semiconductor chip, the upper semiconductor chip including an upper semiconductor substrate and solder bumps on a bottom surface of the upper semiconductor substrate, and a curing layer between the lower semiconductor chip and the upper semiconductor chip, the curing layer including a first curing layer adjacent to the upper semiconductor chip, the first curing layer including a first photo-curing agent, and a second curing layer between the first curing layer and the top surface of the lower semiconductor substrate, the second curing layer including a first thermo-curing agent. | 05-05-2022 |
20220139877 | ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE - The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction. | 05-05-2022 |
20220139883 | Network On Layer Enabled Architectures - The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer. | 05-05-2022 |