Class / Patent application number | Description | Number of patent applications / Date published |
257763000 | At least one layer of molybdenum, titanium, or tungsten | 54 |
20080197503 | CHIP PACKAGE - A chip package including a carrier, at least one chip disposed on the carrier, a plurality of wires electrically connecting the carrier and the chip, and an encapsulant wrapping the chip and the wires is provided. The chip has a semiconductor substrate, an interconnection structure, at least one first reference plane, at least one second reference plane, and at least one chip via, in which the first and second reference planes are respectively located on both sides of the semiconductor substrate, and the interconnection structure is located on the first reference plane and the semiconductor substrate. The chip via connects the first reference plane to the second reference plane. The chip package further includes at least one conductive bonding layer, which bonds the second reference plane to the carrier. | 08-21-2008 |
20080217785 | Semiconductor Device with Grounding Structure - Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer structure to the substrate by a grid of grounding structures and isolation and passivation layers which are connected by the grounding structures. This may provide for an enhancement of the lifetime of the semiconductor devices. | 09-11-2008 |
20080290523 | Semiconductor device including barrier metal and coating film and method for manufacturing same - A semiconductor device includes an interconnection layer provided on a substrate, a first insulating film provided on the substrate, and on the interconnection layer so as to coat the interconnection layer, the first insulating film includes a silicon oxide film, a second insulating film provided on the first insulating film, the second insulating film includes either a silicon oxynitride film or a silicon nitride film, and an insulative coating film provided on the second insulating film. | 11-27-2008 |
20090014883 | INTEGRATED CIRCUIT SYSTEM WITH DUMMY REGION - An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region. | 01-15-2009 |
20090032957 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a lower structure, an insulation layer, metal contacts, a bridge and a metal pad. The lower structure has a metal wiring. An insulation layer is formed on the lower structure. The metal contacts penetrate the insulation layer to be connected to the metal wiring. The bridge is provided in the insulation layer, the bridge connecting the metal contacts to one another. The metal pad is provided on the insulation layer, the metal pad making contact with the metal contacts. | 02-05-2009 |
20090160061 | Introducing a Metal Layer Between Sin and Tin to Improve CBD Contact Resistance for P-TSV - The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer. | 06-25-2009 |
20090243113 | Semiconductor structure - A fusible link between metallization layers of a semiconductor device comprises a tungsten plug deposited in a via interconnecting two aluminum metallization layers. | 10-01-2009 |
20090256264 | SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME - A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss. | 10-15-2009 |
20090321942 | Method of forming stacked trench contacts and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. | 12-31-2009 |
20100025853 | BACK-END-OF-LINE WIRING STRUCTURES WITH INTEGRATED PASSIVE ELEMENTS AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT - Back-end-of-line (BEOL) wiring structures that include a passive element, such as a thin film resistor or a metal-insulator-metal capacitor, and multiple-height vias in a metallization level, as well as design structures for a radiofrequency integrated circuit. The wiring structures generally include a first metal-filled via in a dielectric layer having sidewalls that intersect the passive element and a second metal-filled via in the dielectric layer with sidewalls that do not intersect the passive element. The bottom of the first via includes a conductive layer that operates as an etch stop to prevent deepening of the sidewalls of the first via into a portion of the passive element when the second via is fully etched through the dielectric layer. A liner is applied to the layer of conductive material and the sidewalls of the first via, and the remaining space is filled with another conductive layer. | 02-04-2010 |
20100052176 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction which crosses the first direction and being disposed with a space interposed between the first wiring and the second wiring, and including a tantalum layer, a tantalum nitride layer formed over the tantalum layer, and a metal layer formed over the tantalum nitride layer. | 03-04-2010 |
20100072623 | SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided herein. One fabrication method relates to the formation of conductive contact plugs for a semiconductor device. The method begins by providing a semiconductor device structure having a conductive contact region, a layer of insulating material overlying the conductive contact region, and a via formed in the layer of insulating material and terminating at the conductive contact region. The fabrication process then deposits a first electrically conductive material on the semiconductor device structure such that the first electrically conductive material at least partially fills the via. Then, the process anisotropically etches a portion of the first electrically conductive material located in the filled via, resulting in a lined via. Thereafter, the process deposits a second electrically conductive material on the semiconductor device structure such that the second electrically conductive material at least partially fills the lined via. | 03-25-2010 |
20100072624 | METAL INTERCONNECTION - A metal interconnection including a substrate, a first conductive structure, a second conductive structure, a complex plug and a plug is provided. The substrate includes a first region and a second region. The first conductive structure is disposed on the first region. The second conductive structure is disposed on the second region. The complex plug is disposed on the first conductive structure and includes a tungsten layer and a plurality of insulator columns, wherein an extended direction of each of the insulator columns is perpendicular to a surface of the substrate and the tungsten layer is electrically connected with the first conductive structure. The plug is disposed on the second conductive structure and electrically connected with the second conductive structure. | 03-25-2010 |
20100084766 | SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS - Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss. | 04-08-2010 |
20100084767 | DISCONTINUOUS/NON-UNIFORM METAL CAP STRUCTURE AND PROCESS FOR INTERCONNECT INTEGRATION - An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material. | 04-08-2010 |
20100102450 | ZINC OXIDE BASED COMPOSITES AND METHODS FOR THEIR FABRICATION - A transparent, electrically conductive composite includes a layer of molybdenum oxide or nickel oxide deposited on a layer of zinc oxide layer. The molybdenum component exists in a mixed valence state in the molybdenum oxide. The nickel component exists in a mixed valence state in the nickel oxide. The composite may be utilized in various electronic devices, including optoelectronic devices. In particular, the composite may be utilized as a transparent conductive electrode. As compared to conventional transparent conduct oxides such as indium tin oxide, the composite exhibits superior properties, including a higher work function. | 04-29-2010 |
20110031626 | METAL WIRING OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - The present invention relates to a metal wiring of a semiconductor device and a method for the same, and is directed to disclose a technique forming an additional conductive layer within the metal line, which acts as an etching barrier to increase the etching margin and to improve the RC characteristics between the metal lines, which can prevent the Cu migration. | 02-10-2011 |
20110049720 | Refractory metal nitride capped electrical contact and method for frabricating same - According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device. | 03-03-2011 |
20110266681 | ELECTRONIC COMPONENT AS WELL AS METHOD FOR ITS PRODUCTION - An electronic component includes at least one patterned layer of an electrically conductive material on a substrate, a protective layer of a second material being deposited on the patterned layer of the electrically conductive material. The second material is baser than the electrically conductive material of the patterned layer. In a method for producing the electronic component, the patterned layer of the electrically conductive material is deposited on the substrate in a first step, and the protective layer of the second material, which is baser than the electrically conductive material of the patterned layer, is deposited on the patterned layer in a second step. | 11-03-2011 |
20120007244 | Backside Processing of Semiconductor Devices - A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer. | 01-12-2012 |
20120313247 | Through Silicon Via Structure and Method - A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via. | 12-13-2012 |
20120313248 | SEMICONDUCTOR DEVICE STRUCTURES - The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed. | 12-13-2012 |
20120319282 | Reliable Packaging and Interconnect Structures - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 12-20-2012 |
20130127058 | LINER-FREE TUNGSTEN CONTACT - A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity. | 05-23-2013 |
20130207270 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features. | 08-15-2013 |
20130264713 | METHODS OF FORMING CONDUCTIVE STRUCTURES AND METHODS OF FORMING DRAM CELLS - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 10-10-2013 |
20130320546 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD. | 12-05-2013 |
20130328202 | THROUGH-SILICON VIA AND FABRICATION METHOD THEREOF - A through silicon via (TSV) structure including a semiconductor substrate; a first inter-metal dielectric (IMD) layer on the semiconductor substrate; a cap layer overlying the IMD layer; a conductive layer extending through the cap layer, the first IMD layer and into the semiconductor substrate; a tungsten film capping a top surface of the conductive layer; a second IMD layer overlying the cap layer and covering the tungsten film; and an interconnect feature in the second IMD layer. | 12-12-2013 |
20130328203 | METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING AND ASSOCIATED DEVICE - A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substrate having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt or cobalt alloys, tungsten or tungsten alloys and palladium or palladium alloys. | 12-12-2013 |
20140015141 | Backside Processing of Semiconductor Devices - A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer. | 01-16-2014 |
20140048943 | Semiconductor Constructions, Methods of Forming Conductive Structures and Methods of Forming DRAM Cells - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 02-20-2014 |
20140167270 | Method of Fabricating a Layer Stack - In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V. | 06-19-2014 |
20140167271 | INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF - An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming a conductive layer on the semiconductor substrate; forming a mask layer on the conductive layer; forming a groove in the mask layer and the conductive layer, the groove having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the mask layer and fill the groove, wherein an air gap is formed in a portion of the intermetallic dielectric layer in the groove. The mask layer is formed on the conductive layer, so that the depth-to-width ratio of the groove between adjacent interconnects is increased. Besides, the air gap with a relatively large size is formed between two adjacent interconnects. Therefore, a dielectric constant and parasitic capacitance between adjacent interconnects are reduced evidently, and the performance of the semiconductor devices is improved. | 06-19-2014 |
20140183745 | GATE ELECTRODE(S) AND CONTACT STRUCTURE(S), AND METHODS OF FABRICATION THEREOF - A conductive structure(s), such as a gate electrode(s) or a contact structure(s), and methods of fabrication thereof are provided. The conductive structure(s) includes a first conductive layer of a first conductive material, and a second conductive layer of a second conductive material. The second conductive layer is disposed over the first conductive layer, and at least a portion of the first conductive material includes grains having a size larger than a defined value, and at least a second portion of the second conductive material includes grains having a size less than the defined value. In one embodiment, the first and second conductive materials are the same conductive material, with different-sized grains. | 07-03-2014 |
20140203439 | Through Silicon Via Structure and Method - A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via. | 07-24-2014 |
20140210092 | Refractory Metal Nitride Capped Contact - According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device. | 07-31-2014 |
20140217594 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device configured to prevent a penetration of moisture into an internal circuit. The moisture from a bonding pad to the internal circuit is blocked by providing an underlying polysilicon film ( | 08-07-2014 |
20140232004 | SEMICONDUCTOR DEVICE - The present invention includes a semiconductor substrate and a back electrode (a back multilayer electrode in the preferred embodiment) provided on a back surface of the semiconductor substrate. A rough source pattern is formed in a peripheral edge portion of the back surface of the semiconductor substrate which faces the back multilayer electrode. | 08-21-2014 |
20140252630 | Self-Aligned Pitch Split For Unidirectional Metal Wiring - Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided. | 09-11-2014 |
20140374911 | DEVICE HAVING REDUCED PAD PEELING DURING TENSILE STRESS TESTING AND A METHOD OF FORMING THEREOF - The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer. | 12-25-2014 |
20150048511 | Opening Fill Process and Structure Formed Thereby - Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening. | 02-19-2015 |
20150061138 | METHOD OF FORMING A MEMORY DEVICE - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 03-05-2015 |
20150294871 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film. | 10-15-2015 |
20150303147 | Semiconductor Constructions, Methods of Forming Conductive Structures and Methods of Forming DRAM Cells - Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions. | 10-22-2015 |
20150368094 | Robust MEMS Structure with Via Cap and Related Method - Self-supported MEMS structure and method for its formation are disclosed. An exemplary method includes forming a polymer layer over a MEMS plate over a substrate, forming a via collar along sidewalls of a first portion of a trench over the polymer layer, and forming a second portion of the trench within the polymer layer. The method also includes forming an oxide liner in the trench lining sidewalls of the via collar and sidewalls of the second portion of the trench, depositing a metallic filler in the trench to form a via, and forming a metal cap layer over the via collar and the metallic filler. The method further includes removing a portion of the metal cap layer to form a via cap, and removing the polymer layer such that the via is supported only on a bottom thereof by the substrate. An exemplary structure formed by the disclosed method is also disclosed. | 12-24-2015 |
20160018710 | DISPLAY PANEL, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A display panel, an array substrate, and a method for manufacturing the same are provided. The array substrate comprises a plurality of pixel units each having a gate line and a common line. The gate line comprises a first line segment and a second line segment. An electric connection structure is disposed in the interrupted region between the first line segment and the second line segment, so that the first line segment and the second line segment are electrically connected with each other through the electric connection structure, and the common line extends through said interrupted region in a direction perpendicular to the gate line, and is in insulated contact with the first line segment and the second line segment. The present disclosure can improve the uniformity of the optimum common voltage, thereby improving the product quality. | 01-21-2016 |
20160118339 | Structure Having Isolated Deep Substrate Vias with Decreased Pitch and Increased Aspect Ratio and Related Method - A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns. | 04-28-2016 |
20160155703 | Opening Fill Process and Structure Formed Thereby | 06-02-2016 |
20160379869 | LOW RESISTANCE METAL CONTACTS TO INTERCONNECTS - A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact. | 12-29-2016 |
257764000 | Alloy containing molybdenum, titanium, or tungsten | 5 |
20110198757 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region. | 08-18-2011 |
20120007245 | Via and Method of Forming the Via with a Substantially Planar Top Surface that is Suitable for Carbon Nanotube Applications - A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed. | 01-12-2012 |
20130241070 | OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE - A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact. | 09-19-2013 |
20150333030 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured. | 11-19-2015 |
20160163813 | METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS - Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor. | 06-09-2016 |