Class / Patent application number | Description | Number of patent applications / Date published |
257735000 | Beam leads (i.e., leads that extend beyond the ends or sides of a chip component) | 33 |
20080197488 | BOWED WAFER HYBRIDIZATION COMPENSATION - A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane. | 08-21-2008 |
20080284008 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which is small in size and in which the deformation of leads is prevented at the time of wire-bonding. The semiconductor device includes: an island; a semiconductor element mounted on the bottom surface of the island; leads provided close to the island; and a sealing resin for integrally sealing these constituents. Moreover, in the semiconductor device according to the present invention, electrodes on the semiconductor element are bonded to the leads provided adjacent to a side of the island, the side not provided with leads which extends continuously from the island. | 11-20-2008 |
20080315407 | THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USING TWO-DIMENSIONAL FABRICATION - Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g., die-to-substrate); and assemblies including a stack of at least two such devices interconnected die-to-die, or such a stack of devices electrically interconnected to underlying circuitry. Also, apparatus and methods for testing such a die. | 12-25-2008 |
20080315408 | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same - Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups. | 12-25-2008 |
20090014868 | MANUFACTURING IC CHIP IN PORTIONS FOR LATER COMBINING, AND RELATED STRUCTURE - Methods of manufacturing an IC chip in portions for later combining and a related structure are disclosed. In one embodiment, the method includes: fabricating a first portion of the IC chip, the first portion including a structure from a selected level of back-end-of-line (BEOL) processing up to an end of the BEOL processing, the first portion providing a specific functionality when combined with a second portion of the IC chip, fabricating the second portion of the IC chip, the second portion including a structure from a device level of the IC chip up to the selected level of the BEOL processing, the second portion having structure providing generic IC chip functionality. The fabrication of the portions may occur at a single location or different locations, and the combining may occur at the same location or different location as one or more of the fabrication processes. | 01-15-2009 |
20090072390 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A semiconductor apparatus ( | 03-19-2009 |
20090091023 | Semiconductor Device Package - A semiconductor device package incorporating a connector that reduces manufacturing operations and enables efficient manufacturing. The semiconductor device package includes a primary molded product and a secondary molded product. The primary molded product includes a semiconductor device, a lead connected to the semiconductor device, and a plug terminal formed by at least part of the lead. The primary molded product envelops the semiconductor device and part of the lead in a first resin material. The secondary molded product envelops the primary molded product in a second resin material and includes a connector guide surrounding the plug terminal and used to guide insertion of a holder holding a socket terminal connectable to the plug terminal. | 04-09-2009 |
20100140794 | APPARATUS AND METHOD FOR PACKAGING CIRCUITS - An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed. | 06-10-2010 |
20100308456 | Wafer-Level, Polymer-Based Encapsulation for Microstructure Devices - A device includes a first device structure having a semiconductor platform, and a second device structure having a microstructure spaced from the semiconductor platform. The device further includes a cable having a plurality of beams to couple the microstructure to the first device structure. Each beam of the plurality of beams has a polymer coating and a serpentine-shaped region. | 12-09-2010 |
20110042802 | Semiconductor device, external connection terminal, method of manufacturing semiconductor device, and method of manufacturing external connection terminal - A semiconductor device includes an electrode pad and an external connection terminal. The external connection terminal contains Sn equal to or more than 50 wt %, Sn and Pb equal to or more than 90 wt % in total, or Pb equal to or more than 85 wt %, and the surface thereof is coated with an Au layer. The thickness of the Au layer is preferably equal to or more than 10 nm and equal to or less than 1 μm. The weight of the Au layer is preferably equal to or less than 0.6% of the weight of the external connection terminal. | 02-24-2011 |
20110121448 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - The semiconductor device comprises a support plate; a semiconductor element; and conductor posts consisting of a conductor having a first end at one end and a second end at the other end, the second end being connected to the semiconductor element and the conductor posts being connected to the support plate at a position on the side of the second end that is closer to the first end, wherein the conductor posts have a heat conductivity of approximately 200 W/m·K or higher and a Vickers hardness of approximately 70 or lower. | 05-26-2011 |
20110140266 | ELECTROSTATIC CAPACITANCE-TYPE INPUT DEVICE AND METHOD OF MANUFACTURING THEREOF - An electrostatic capacitance-type input device includes: a first translucent conductive film that configures a first electrode that extends in a first direction in an input area on a substrate and second electrodes that extend in a second direction intersecting the first direction in the input area and are disconnected in intersection portions with the first electrode; an interlayer insulating film that is formed at least in areas overlapping the intersection portions; and a second translucent conductive film that configures relay electrodes formed on the interlayer insulating film to have sheet resistance lower than that of the first translucent conductive film and electrically connecting the second electrodes disconnected in the intersection portion by being electrically connected to the second electrodes in an area in which the interlayer insulating film is not formed and a peripheral wiring extending in a peripheral area of the substrate located to the outer side of the input area. | 06-16-2011 |
20110233759 | SEMICONDUCTOR DEVICE - All lead terminals | 09-29-2011 |
20110233760 | SEMICONDUCTOR DEVICE - A power semiconductor chip (first semiconductor chip) | 09-29-2011 |
20110272798 | CHIP UNIT AND STACK PACKAGE HAVING THE SAME - A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other. | 11-10-2011 |
20110298122 | INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS - High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed. | 12-08-2011 |
20120043653 | LEAD PIN FOR PACKAGE SUBSTRATE, AND METHOD FOR MANUFACTURING PACKAGE SUBSTRATE WITH THE SAME - Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate according to the exemplary embodiment of the present invention includes a head part having one surface opposite to the package substrate and the other surface that is an opposite side to the one surface; and a connection pin having a pin shape bonded to the other surface of the head part, wherein the head part has a concave depression part toward the package substrate. | 02-23-2012 |
20120068331 | Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same - At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring. | 03-22-2012 |
20120133040 | SEMICONDUCTOR CHIP AND SOLAR SYSTEM - There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal. | 05-31-2012 |
20130043582 | MULTIPLE DIE IN A FACE DOWN PACKAGE - A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements. | 02-21-2013 |
20130075890 | INTEGRATED CIRCUIT AND METHOD OF MAKING - Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via. | 03-28-2013 |
20130134577 | RIBBON BONDING IN AN ELECTRONIC PACKAGE - A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test. | 05-30-2013 |
20130147029 | ULTRA-SMALL CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Some embodiments of the present disclosure provide the design and manufacture of an ultra-small chip assembly. The ultra-small chip assembly comprises a die, a plate-like back electrode disposed on the back-side of the die, and one or more plate-like positive electrodes disposed on the front-side of the die. The ultra-small chip assembly is configured such that one end of the plate-like back electrode extends beyond a first side of the die, and each of the one or more plate-like positive electrodes includes an end which extends beyond a second side of the die. By attaching both the plate-like back electrode and the plate-like positive electrodes on the surfaces of the die, and directly using the exposed ends of the plate-like electrodes as the lead-out electrodes for the chip assembly, the electrical connections outside of the die only occupy a very small volume. | 06-13-2013 |
20130221516 | POWER SEMICONDUCTOR MODULE - A power semiconductor module ( | 08-29-2013 |
20140048925 | INTEGRATED CIRCUIT - An integrated circuit includes a main body, a number of connection tabs molded on the main body, and a number of pins respectively connected to the connection tabs. The connection tabs and the pins are made of metal. The connection tabs are electrically connected to a logic circuit in the main body. | 02-20-2014 |
20140138814 | Method for Producing an Integrated Circuit Pointed Element, and Corresponding Integrated Circuit - A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element. | 05-22-2014 |
20140167251 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a silicon substrate, an insulation film, and a plurality of chip-side connection terminals. The silicon substrate is internally provided with a first wire layer. The insulation film is stacked on a first surface of surfaces of the silicon substrate, the first surface being approximately parallel to the first wire layer. The chip-side connection terminals are electrically connected to the wire layer. Moreover, the chip-side connection terminals are exposed on a second surface side, the second surface being continuous from the first surface in an approximately perpendicular manner. | 06-19-2014 |
20140239489 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, multiple terminals arranged in a first direction, a resin portion sealing the semiconductor chip and the terminals. The terminals are projected from a side surface of the resin portion in a second direction, and include at least one subject terminal having a first portion and a second portion. In the subject terminal, a first longitudinal end of the first portion is positioned inside of the resin portion and a second longitudinal end of the first portion is positioned outside of the resin portion, and the second portion is arranged adjacent to the first portion. Further, a length of the first portion is greater than a length of the second portion in the third direction, and a length of the first portion is smaller than a length of the second portion in the first direction. | 08-28-2014 |
20150130048 | Semiconductor Package Comprising Two Semiconductor Modules and Laterally Extending Connectors - A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body. | 05-14-2015 |
20160172262 | INTEGRATED CIRCUIT DEVICE WITH SHAPED LEADS AND METHOD OF FORMING THE DEVICE | 06-16-2016 |
257736000 | Layered | 3 |
20100230808 | REDUCING STRESS BETWEEN A SUBSTRATE AND A PROJECTING ELECTRODE ON THE SUBSTRATE - The present invention relates to a semiconductor component that has a substrate and a projecting electrode. The projecting electrode has a substrate face, which faces the substrate and which comprises a first substrate-face section separated from the substrate by a gap. The gap allows a stress-compensating deformation of the projecting electrode relative to the substrate. The substrate face of the projecting electrode further comprises a second substrate-face section, which is in fixed mechanical and electrical connection with the substrate. Due to a smaller footprint of mechanical connection between the projecting electrode and the substrate, the projecting electrode can comply in three dimensions to mechanical stress exerted, without passing the same amount of stress on to the substrate, or to an external substrate in an assembly. This results in an improved lifetime of an assembly, in which the semiconductor component is connected to an external substrate by the projecting electrode. | 09-16-2010 |
20140299984 | CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature. | 10-09-2014 |
20160126205 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor elements and first and second conductive members. A first electrode on the first semiconductor element is bonded to a first stack part of the first conductive member by a first bonding layer. A second electrode on the second semiconductor element is bonded to a second stack part of the second conductive member by a second bonding layer. A first joint part of the first conductive member is bonded to a second joint part of the second conductive member by an intermediate bonding layer. A first surface of the first joint part facing the second joint part, a side surface of the first joint part continuous from the first surface, a second surface of the second joint part facing the first joint part, and a side surface of the second joint part continuous from the second surface are covered by nickel layers. | 05-05-2016 |