Class / Patent application number | Description | Number of patent applications / Date published |
257704000 | Cap or lid | 82 |
20080203558 | Method of semiconductor device protection, package of semiconductor device - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 08-28-2008 |
20080211087 | CHIP MODULE AND METHOD FOR PRODUCING A CHIP MODULE - A chip module comprises a substrate, a chip arranged on one side of the substrate and conductor structures arranged on at least one side of the substrate and conductively connected to the chip. At least one stiffening element is arranged on one side of the substrate and a moulding cap encapsulates at least the chip. For producing the chip module, provision is made for providing a substrate and applying conductor structures to at least one side of the substrate. At least one stiffening element is mounted onto one side of the substrate. Furthermore, a chip is mounted onto one side of the substrate and connected to the conductor structures. A moulding compound is applied on the substrate, such that the chip is covered. | 09-04-2008 |
20080230893 | Integrated Circuit with Package Lid - Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced. | 09-25-2008 |
20080237839 | Semiconductor apparatus and method of manufacturing same - A semiconductor apparatus and a method of manufacturing same can simplify the manufacturing process and prevent a decrease in production yield without decreasing in sensor sensitivity. A semiconductor apparatus includes a package having a first region having a first thickness, a second region having a second thickness greater than the first thickness, the second region being surrounded by the first region, a third region having a third thickness greater than the second thickness, the third region being surrounded by the second region, and at least one connection pad electrically provided in the third region and connected to an external of the package; a sensor chip having a first weight section, a fixed section surrounding the first weight section and being separated from the first weight section, and a beam section having an elasticity and connecting the first weight section to the fixed section, the fixed section being positioned at the second region of the package; and a second weight section separated from the fixed section and the beam section and connected to the first weight section via an adhesive layer. | 10-02-2008 |
20090001552 | SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 01-01-2009 |
20090001553 | Mems Package and Method for the Production Thereof - A micro electro-mechanical systems (MEMS) package is described herein. The package includes a carrier substrate having a top side, a MEMS chip mounted on the top side of the carrier substrate, and at least one chip component on or above the top side of the carrier substrate or embedded in the carrier substrate. The package also includes a thin metallic shielding layer covering the MEMS chip and the chip component and forming a seal with the top side of the carrier substrate. | 01-01-2009 |
20090020866 | SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS THEREFOR - A semiconductor device includes: a package case in which a semiconductor element is mounted, the package case having a bonding portion; a cap having a bonding portion bonded to the bonding portion of the package case so as to hermetically seal the semiconductor element; and one or more bonding/sealing wires disposed between and in contact with the bonding portion of the package case and the bonding portion of the cap such that the one or more bonding/sealing wires form a closed loop and hermetically seal the semiconductor element. | 01-22-2009 |
20090057876 | STACKED PACKAGE STRUCTURE FOR REDUCING PACKAGE VOLUME OF AN ACOUSTIC MICRO-SENSOR - A stacked package structure utilizes flip-chip technology to stack an acoustic micro-sensor on an integrated circuit (IC) device having a recess as a back chamber and cover the acoustic micro-sensor using a glass substrate or a planar substrate with an aperture. With the use of the stacked package structure, the package volume of the acoustic micro-sensor can be reduced effectively. | 03-05-2009 |
20090065928 | Anti-stiction technique for electromechanical systems and electromechanical device employing same - A mechanical structure is disposed in a chamber, at least a portion of which is defined by the encapsulation structure. A first method provides a channel cap having at least one preform portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. A second method provides a channel cap having at least one portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. The at least one portion is fabricated apart from the electromechanical device and thereafter affixed to the electromechanical device. A third method provides a channel cap having at least one portion disposed over or in at least a portion of the anti-stiction channel to seal an anti-stiction channel, at least in part. The at least one portion may comprise a wire ball, a stud, metal foil or a solder preform. A device includes a substrate, an encapsulation structure and a mechanical structure. An anti-stiction layer is disposed on at least a portion of the mechanical structure. An anti-stiction channel is formed in at least one of the substrate and the encapsulation structure. A cap has at least one preform portion disposed over or in at least a portion of the anti-stiction channel to seal the anti-stiction channel, at least in part. | 03-12-2009 |
20090085194 | WAFER LEVEL PACKAGED MEMS DEVICE - An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped. | 04-02-2009 |
20090096084 | Semiconductor chip packages having reduced stress - A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate. | 04-16-2009 |
20090140416 | Cap member and semiconductor device employing same - A cap member capable of alleviating degradation of reliability and improving fabrication yields is provided. The cap member has a cylindrical side wall portion, a top face portion closing one end of the side wall portion and having a light exit hole formed therein to allow extraction of laser light from a semiconductor laser chip; a light transmission window fitted to the top face portion to stop the light exit hole, and a flange portion arranged at the other end of the side wall portion and welded on the upper face of a stem on which the semiconductor laser chip is mounted. A groove portion is formed in an inner surface of the top face portion, and this groove portion makes part of the top face portion in a predetermined region less thick than the other part thereof. | 06-04-2009 |
20090146290 | Interconnect Structure and Method for Semiconductor Device - An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device. | 06-11-2009 |
20090160047 | DOWNHOLE TOOL - A downhole tool having at least one semiconductor device, including: a die; a bonding pad which is attached to the surface of the die; a bonding wire which is attached to the bonding pad; a bonding point which is formed on the bonding pad for connecting the bonding wire to the bonding pad; an encapsulating resin encapsulating the die and being provided with a cavity such that a connecting portion of the bonding point and the bonding pad is exposed out of the resin in the cavity; and a lid on the encapsulating resin to cover the cavity. | 06-25-2009 |
20090200659 | Chip Package with Channel Stiffener Frame - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate. | 08-13-2009 |
20090200660 | HEATPLATES FOR HEATSINK ATTACHMENT FOR SEMICONDUCTOR CHIPS - An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction. | 08-13-2009 |
20090236731 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM - A stackable integrated circuit package system including mounting an integrated circuit device over a package carrier, mounting a stiffener over the package carrier and mounting a mountable package carrier over the stiffener with a vertical gap between the integrated circuit device and the mountable package carrier. | 09-24-2009 |
20090243084 | SUSPENSION MICROSTRUCTURE AND A FABRICATION METHOD FOR THE SAME - A suspension microstructure and its fabrication method, in which the method comprises the steps of: forming at least one insulation layer with inner micro-electro-mechanical structures on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one microstructure and a plurality of metal circuits that are independent from each other, the micro-electro-mechanical structures have an exposed portion on the surface of the insulation layer, and the exposed portion is provided with through holes or stacked metal-via layers correspondingly to the predetermined etching spaces of the micro-electro-mechanical structures, the above predetermined etching spaces and the stacked metal-via layers only penetrate the insulation layer; forming a photoresist with an opening on the upper surface of the exposed portion, and the opening of the photoresist is located outside all the through holes or the stacked metal-via layers; subsequently, conducting etching to realize the suspension of the microstructures. | 10-01-2009 |
20100052154 | SURFACE SMOOTHENED ULTRAHIGH CONDUCTIVITY COMPOSITE LID FOR IMPROVED MARKING PERMANENCY OF SEMICONDUCTOR PACKAGED DEVICES - A semiconductor-lid structure and method of forming a semiconductor-lid structure includes a semiconductor die, an ultrahigh thermal conductivity lid disposed on the semiconductor die, and a thermal interface layer between said semiconductor die and said ultrahigh thermal conductivity lid. The ultrahigh thermal conductivity lid includes a coupon having at least one uneven surface, a first layer on said at least one uneven surface formed from a process comprising one of sputter coating a highly adhesive metal over said uneven surface and sputtering a metallic seed layer, and a second layer on said first layer formed from a process comprising one of sputtering a metallic diffusion barrier layer over said first layer and electroplating the metallic seed layer with a highly conductive metal. The ultrahigh thermal conductivity lid has a smooth outer surface formed by chemical and/or mechanical processing of the ultrahigh thermal conductivity lid after formation of the second layer. | 03-04-2010 |
20100052155 | METHODS OF PROMOTING ADHESION BETWEEN TRANSFER MOLDED IC PACKAGES AND INJECTION MOLDED PLASTICS FOR CREATING OVER-MOLDED MEMORY CARDS - A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package. | 03-04-2010 |
20100059877 | Method for packaging electronic devices and integrated circuits - The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits. | 03-11-2010 |
20100102440 | HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE - A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die. | 04-29-2010 |
20100109152 | Electronic device and lid - The present invention can prevent a lid from tilting when the lid is attached to a substrate. An electronic device | 05-06-2010 |
20100117221 | Capped Wafer Method and Apparatus - A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die. Removing excess cap wafer material involves making a first cut in the cap wafer near a first row of bond pads and a second cut near the adjacent row of bond pads, such that a strip of wafer cap material is suspended from portions of an underlying supporting member near the edge of the capped wafer, and then removing the wafer cap material suspended from the portions of the supporting glass frit using an adhesive tape. | 05-13-2010 |
20100117222 | Void Reduction in Indium Thermal Interface Material - Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling. | 05-13-2010 |
20100117223 | SEMICONDUCTOR MODULE - A semiconductor module includes a base plate, at least one semiconductor chip mounted on the base plate, a case fixed to the base plate and surrounding the at least one semiconductor chip, an electrically insulating gel layer covering the at least one semiconductor chip, a thermosetting resin layer formed on top of the gel layer, and a lid formed on top of the thermosetting resin layer. The lid comprises a lid-extension, which defines a lid-opening. The lid-opening extends through the thermosetting resin layer to the gel layer and allows gel of the gel layer to expand into the lid-opening. | 05-13-2010 |
20100155934 | MOLDING COMPOUND INCLUDING A CARBON NANO-TUBE DISPERSION - A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns. | 06-24-2010 |
20100276799 | Semiconductor Chip Package with Stiffener Frame and Configured Lid - Various semiconductor chip packages and methods of assembling and making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a stiffener frame to a first side of a substrate. The stiffener frame has a central opening to accommodate a semiconductor chip and an outer edge surface. A semiconductor chip is coupled to the first side in the opening. A lid is coupled to the stiffener frame with an adhesive. The lid has a first edge surface set back from the outer edge surface of the stiffener frame. The adhesive is set back from the outer edge surface of the stiffener frame. | 11-04-2010 |
20110042801 | MEMS PACKAGING SCHEME USING DIELECTRIC FENCE - A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device. | 02-24-2011 |
20110049699 | METHOD OF SEMICONDUCTOR DEVICE PROTECTION, PACKAGE OF SEMICONDUCTOR DEVICE - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 03-03-2011 |
20110068462 | SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS - A structure. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate. | 03-24-2011 |
20110079893 | DEVICE PACKAGE AND METHODS FOR THE FABRICATION AND TESTING THEREOF - Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component. | 04-07-2011 |
20110180923 | RELIABILITY ENHANCEMENT OF METAL THERMAL INTERFACE - A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated. | 07-28-2011 |
20110180924 | MEMS MODULE PACKAGE - A MEMS module package includes a carrier, a lid capped on the carrier, a spacer disposed between the carrier and the lid, and a chip mounted on the spacer and electrically connected with the carrier. The spacer has a channel in communication between a chamber and a receiving hole of the lid, and the chip is received in the chamber of the lid and corresponding to the channel of the spacer. Therefore, an external signal can be transmitted from the receiving hole of the lid into the chamber of the lid through the channel of the spacer so as be received by the chip. | 07-28-2011 |
20120018872 | LID FOR AN ELECTRICAL HARDWARE COMPONENT - To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate. | 01-26-2012 |
20120074560 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier. | 03-29-2012 |
20120080784 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. | 04-05-2012 |
20120119349 | INSULATION SHEET MADE FROM SILICON NITRIDE, AND SEMICONDUCTOR MODULE STRUCTURE USING THE SAME - An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains β-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride. | 05-17-2012 |
20120161309 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base portion including a first member and a second member which are joined to each other; a semiconductor element mounted on the first member; a terminal mounted on the second member; and a wire electrically connecting the semiconductor element to the terminal. Heat resistance of the first member is lower than heat resistance of the second member, and linear thermal expansion coefficient of the second member is smaller than linear thermal expansion coefficient of the first member. | 06-28-2012 |
20120181683 | THREE-DIMENSIONALLY INTEGRATED SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCORPORATION BY REFERENCE - A three-dimensionally integrated semiconductor device includes a flexible circuit substrate which has a lower portion, an upper portion, and at least one side portion, a support body which supports the upper portion of the flexible circuit substrate, and at least two devices mounted on the flexible circuit substrate and wherein at least one of the devices is mounted on an upper surface of the lower portion of the flexible circuit substrate, at least one of the other devices is mounted on a lower surface of the upper portion of the flexible circuit substrate, and a gap is provided between the device mounted on the upper surface of the lower portion of the flexible circuit substrate and the device mounted on the lower surface of the upper portion of the flexible circuit substrate. | 07-19-2012 |
20120241938 | ORGANIC PACKAGING CARRIER - An organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and a sealing metal layer. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and includes at least a conductive layer and a sealing ring. The sealing ring is a closed ring. The sealing metal layer is located on the sealing ring, wherein a meterial of the sealing metal layer includes AgSn and is lead-free. | 09-27-2012 |
20120256308 | Method for Sealing a Micro-Cavity - A method for sealing a cavity is disclosed. The method includes depositing a membrane layer on top of a sacrificial layer, etching release holes into the membrane layer, and removing at least a portion of the sacrificial layer through the release holes to form a cavity. Prior to removing the sacrificial layer portion, the method includes producing a narrowing layer on the side walls of the release holes. The narrowing layer can be a sealing layer that seals off the release holes after a reflow step. Alternatively, the narrowing layer can be a layer that does not have a sealing function and is used to narrow the holes, allowing the holes to be sealed without a sealing or other material entering the cavity. The narrowing layer may be deposited by conformal deposition followed by an anisotropic etch or by direct deposition on the side walls of the release holes. | 10-11-2012 |
20120326294 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The method comprises adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting comprises placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further comprise lowering the lid until the pistons contact the chip shim. The method further comprises separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further comprises dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further comprises sealing the lid to the chip carrier with sealant. | 12-27-2012 |
20130001765 | INTEGRATED HEATER ON MEMS CAP FOR WAFER SCALE PACKAGED MEMS SENSORS - A system and method for controlling temperature of a MEMS sensor are disclosed. In a first aspect, the system comprises a MEMS cap encapsulating the MEMS sensor and a CMOS die vertically arranged to the MEMS cap. The system includes a heater integrated into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. In a second aspect, the method comprises encapsulating the MEMS sensor with a MEMS cap and coupling a CMOS die to the MEMS cap. The method includes integrating a heater into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. | 01-03-2013 |
20130032935 | IMPLEMENTING ENHANCED THERMAL CONDUCTIVITY IN STACKED MODULES - A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove. | 02-07-2013 |
20130032936 | PACKAGE FOR A MEMS SENSOR AND MANUFACTURING PROCESS THEREOF - A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure. | 02-07-2013 |
20130056863 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a stiffener, having a stiffener opening completely through the stiffener, on the substrate; molding an encapsulation on the substrate and directly on an outer upper periphery surface of the stiffener and exposing an inner upper periphery surface of the stiffener, the encapsulation exposing a portion of the substrate; mounting an integrated circuit over the substrate and within the perimeter of the stiffener; and attaching a lid plate on the inner upper periphery surface of the stiffener and over the integrated circuit, the lid plate extending above an encapsulation top side. | 03-07-2013 |
20130075888 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed. | 03-28-2013 |
20130119529 | SEMICONDUCTOR DEVICE HAVING LID STRUCTURE AND METHOD OF MAKING SAME - A semiconductor device includes a substrate, a first die attached to the substrate, and a lid coupled to the substrate. The lid defines a cavity for engaging the first die, and the lid has a die enclosure barrier having ends extending downwardly into the cavity. The ends of the die enclosure barrier are attached to the substrate and a thermal interface material is disposed between the first die and the lid, thermally connecting the first die to the lid. | 05-16-2013 |
20130127036 | NOVEL MECHANISM FOR MEMS BUMP SIDE WALL ANGLE IMPROVEMENT - The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided. | 05-23-2013 |
20130241045 | PACKAGES AND METHODS FOR PACKAGING - Integrated devices and methods for packaging the same can include an external housing, an internal housing positioned within the external housing, and an external cavity formed between the external housing and the internal housing. An integrated device die can be positioned within the external cavity in fluid communication with an internal cavity formed by the internal lid. An air way can extend through the external cavity to the internal cavity, and can further extend from the internal cavity to the external cavity. The air way can provide fluid communication between the package exterior and the integrated device die, while reducing contamination of the integrated device die. | 09-19-2013 |
20130313700 | CAVITY-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SAME | 11-28-2013 |
20130320517 | LIDDED INTEGRATED CIRCUIT PACKAGE - A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material. | 12-05-2013 |
20140027898 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The method includes adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting includes placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further includes lowering the lid until the pistons contact the chip shim. The method further includes separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further includes dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further includes sealing the lid to the chip carrier with sealant. | 01-30-2014 |
20140061891 | SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package. | 03-06-2014 |
20140061892 | PACKAGED DEVICE EXPOSED TO ENVIRONMENTAL AIR AND LIQUIDS AND MANUFACTURING METHOD THEREOF - A packaged device, wherein at least one sensitive portion of a chip is enclosed in a chamber formed by a package. The package has an air-permeable area having a plurality of holes and a liquid-repellent structure so as to enable passage of air between an external environment and the chamber and block the passage of liquids. | 03-06-2014 |
20140077352 | Matrix Lid Heatspreader for Flip Chip Package - A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array ( | 03-20-2014 |
20140103518 | STRUCTURE AND METHOD FOR AIR CAVITY PACKAGING - A structure and method for air cavity packaging, the structure comprises a carrier having plural die pads and leads, plural dies, plural wires, plural walls, and a lid. The dies are mounted on the die pads. The wires electrically connect the dies to the leads. The plural walls are disposed on the carrier and form plural cavities in a way that each cavity contains at least one die pad and plural leads, and each wall is provided with at least one air vent for exhausting air to the outside. The lid is attached on the plural walls via an adhesive agent to seal the plural air cavities, so that the plural connected air cavity packages are formed. | 04-17-2014 |
20140117527 | REDUCED INTEGRATED CIRCUIT PACKAGE LID HEIGHT - One embodiment of the present invention sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, and a lid having a top portion and an end portion and configured to encapsulate the one or more devices. The top portion is thinner than the end portion. One advantage of the disclosed design is that the overall height of an IC package may be reduced without significantly impacting the structural integrity or co-planarity of the IC package. | 05-01-2014 |
20140151869 | INTEGRATED HEATER ON MEMS CAP FOR WAFER SCALE PACKAGED MEMS SENSORS - A system and method for controlling temperature of a MEMS sensor are disclosed. In a first aspect, the system comprises a MEMS cap encapsulating the MEMS sensor and a CMOS die vertically arranged to the MEMS cap. The system includes a heater integrated into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. In a second aspect, the method comprises encapsulating the MEMS sensor with a MEMS cap and coupling a CMOS die to the MEMS cap. The method includes integrating a heater into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. | 06-05-2014 |
20140203424 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the substrate; a cover member configured to be disposed on the sidewall member, and to partition a space around the element along with the sidewall member on the substrate; and a seal member configured to be disposed outside of the sidewall member, to bond the sidewall member and the cover member to a surface of the substrate, and to seal the space. | 07-24-2014 |
20140264815 | Semiconductor Device Package and Method - Various packages and methods are disclosed. A package according to an embodiment includes a substrate, a chip attached to a surface of the substrate with electrical connectors, a molding compound on the surface of the substrate and around the chip, an adhesive on a surface of the chip that is distal from the surface of the substrate, and a lid on the adhesive. In an embodiment, a region between the molding compound and the lid at a corner of the lid is free from the adhesive. In another embodiment, the lid has a recess in a surface of the lid facing the surface of the molding compound. | 09-18-2014 |
20140346658 | FABRICATING A MICROELECTRONICS LID USING SOL-GEL PROCESSING - A method for fabrication of a lid for a microelectronic device is described, wherein the microelectronic device comprises of a die and a laminate. A gel is formed having a coefficient of thermal expansion (CTE) within a threshold percentage value of either a CTE of the die or a CTE of the laminate of the microelectronics device. A metal piece is inserted into the gel to form a lid. | 11-27-2014 |
20140346659 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: semiconductor modules in which a circuit board having at least one or more semiconductor chips mounted thereon is sealed with a mold resin material and an attachment hole is formed; main terminal plates that individually connect individual connection terminals of the plurality of semiconductor modules which are arranged in parallel; and a module storage case into which the plurality of the semiconductor modules connected by the main terminal plates are inserted integrally with the main terminal plates from an opening portion and which holds the plurality of semiconductor modules such that the position of the semiconductor modules can be adjusted during attachment and includes attachment insertion holes facing the attachment holes of the semiconductor modules. | 11-27-2014 |
20140361424 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor modules, each of which includes a semiconductor circuit having a circuit board on which at least one or more semiconductor chips are mounted; and a module storage case that accommodates the plurality of semiconductor modules which are arranged in parallel. In the module storage case, a plurality of pairs of positioning guide members, which position and guide the semiconductor modules, are formed on opposite surfaces forming a module storage region for accommodating the semiconductor modules so as to protrude inward and to face each other, so that a distance between the plurality of semiconductor modules in a longitudinal direction can be selected. A pair of fitting concave portions, which are fitted to the pair of positioning guide members, are formed at both ends of each semiconductor module in the longitudinal direction. | 12-11-2014 |
20150035133 | ELECTRONIC MODULES AND METHODS OF MAKING ELECTRONIC MODULES - A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity. | 02-05-2015 |
20150061104 | SEMICONDUCTOR DEVICE - An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other. | 03-05-2015 |
20150061105 | SEMICONDUCTOR MODULE - Aspects of the invention provide a semiconductor module that can be manufactured without using a bending jig for bearing the stress in bending process of the terminal and scarcely generates cracks in the resin parts of the semiconductor module. In some aspects of the invention, a semiconductor module can include a casing made of a resin material accommodating a semiconductor chip, a terminal one end of which is electrically connected to the semiconductor chip and the other end of which is projecting out of the casing and bent and a lid made of a resin material fitted on an opening of the casing, a part of end region of the lid being in contact with the terminal and being a thick part with a thickness thicker than a thickness of other parts of the lid. | 03-05-2015 |
20150061106 | CAVITY-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SAME | 03-05-2015 |
20150061107 | INSULATION SHEET MADE FROM SILICON NITRIDE, AND SEMICONDUCTOR MODULE STRUCTURE USING THE SAME - An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains β-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride. | 03-05-2015 |
20150076683 | Integrated Circuit Device Packages And Methods for Manufacturing Integrated Circuit Device Packages - An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device. | 03-19-2015 |
20150076684 | Semiconductor Device - A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and | 03-19-2015 |
20150091153 | WAFER LEVEL SEALING METHODS WITH DIFFERENT VACUUM LEVELS FOR MEMS SENSORS - The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure. | 04-02-2015 |
20150357254 | SUBSTRATE FOR ELECTRONIC DEVICE PACKAGE, ELECTRONIC DEVICE PACKAGE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - A base substrate includes a first layer which is a ceramic layer; a second layer which is disposed on one surface side of the first layer, and contains at least one of a glass layer, a silicon layer, and a quartz layer; and a concave portion that is opened on a side of the second layer opposite to the first layer. In addition, the concave portion is formed through etching. | 12-10-2015 |
20150364392 | SEMICONDUCTOR DEVICE WITH COVERING MEMBER THAT PARTIALLY COVERS WIRING SUBSTRATE - An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other. | 12-17-2015 |
20150364393 | POWER MODULE SEMICONDUCTOR DEVICE - There is provided a power module semiconductor device allowing reduction in size and weight of a thin type SiC power module. The power module semiconductor device includes: a ceramic substrate; a first pattern of a first copper plate layer disposed on a surface of the ceramic substrate; a first semiconductor chip disposed on the first pattern; a first pillar connection electrode disposed on the first pattern; and an output terminal connected to the first pillar connection electrode. | 12-17-2015 |
20160027724 | WIRING BOARD - The wiring board of the present invention includes at least one insulating layer and at least one conductor layer being alternately laminated, a semiconductor element connection pad formed on an upper surface of the insulating layer at an uppermost layer of the insulating layers, a cap connection pattern arranged so as to surround a region where the semiconductor element connection pad is formed, and at least one strip-shaped pattern extending from the semiconductor element connection pad to a region outside an end portion on the region side of the cap connection pattern. The cap connection pattern is formed by a plurality of island-shaped patterns spaced apart from one another, and the strip-shaped pattern is formed between the adjacent island-shaped patterns on the upper surface of the insulating layer at the uppermost layer. | 01-28-2016 |
20160039665 | HERMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER - A sealed package having a device disposed on a wafer structure and slid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material. | 02-11-2016 |
20160064307 | LIQUID COOLING OF SEMICONDUCTOR CHIPS UTILIZING SMALL SCALE STRUCTURES - A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds. | 03-03-2016 |
20160064355 | CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF - A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at least partially surrounding the at least one second die, the lid having inclined sidewalls spaced apart from and facing the at least one second die. | 03-03-2016 |
20170236804 | APPARATUSES AND METHODS FOR INTERNAL HEAT SPREADING FOR PACKAGED SEMICONDUCTOR DIE | 08-17-2017 |
20190144269 | WAFER LEVEL ENCAPSULATION FOR MEMS DEVICE | 05-16-2019 |