Entries |
Document | Title | Date |
20080203539 | Semiconductor Components With Conductive Interconnects - A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a substrate contact. A stacked semiconductor component includes multiple semiconductor components in a stacked array having bonded connections between conductive interconnects on adjacent components. An image sensor semiconductor component includes a semiconductor substrate having light detecting elements on the circuit side, and conductive interconnects on the backside. | 08-28-2008 |
20080224271 | Semiconductor Device and Method of Manufacturing Same, Wiring Board and Method of Manufacturing Same, Semiconductor Package, and Electronic Device - Passivation films | 09-18-2008 |
20080237806 | THROUGH-ELECTRODE AND SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device is produced by laminating a plurality of semiconductor chips having through-electrodes running through semiconductor substrates, wherein each through-electrode includes an internal electrode, a ring-shaped semiconductor, and an external electrode. The internal electrode is formed using an internal conductive film and includes a plurality of pillar semiconductors, each of which is formed in a rectangular shape or a polygonal shape. The pillar semiconductors are each arranged with a prescribed distance therebetween in connection with the ring-shaped semiconductor. The internal conductive film is embedded in regions between the ring-shaped semiconductor and the pillar semiconductors and between the pillar semiconductors adjoining together. This makes it possible to form trenches having uniform depth, thus realizing a high-speed film growth with respect to the conductive film. | 10-02-2008 |
20080237807 | SEMICONDUCTOR DEVICE - A second electrode is selectively brought into contact with a semiconductor substrate. Specifically, an insulating film having opening portions is provided on the second principal surface of the semiconductor substrate, and the second electrode is provided on the insulating film. The second electrode comes into contact with the second principal surface of the semiconductor substrate through the opening portions. The total area of the opening portions is approximately the half of the total area of the second principal surface of the semiconductor substrate. Consequently, minority carriers (holes) are prevented by the insulating film from being drawn out, and thus, the loss of the minority carriers around the second electrode is decreased. Accordingly, the conductivity modulation effect is improved. Therefore, the forward voltage can be decreased even with a structure in which the impurity concentration of a p type impurity region is decreased in order to shorten a reverse recover time. | 10-02-2008 |
20080237808 | Semiconductor Device and Method of Manufacturing the Same - Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction. | 10-02-2008 |
20080251890 | Method of Forming Buffer Layer for Nitride Compound Semiconductor Light Emitting Device and Nitride Compound Semiconductor Light Emitting Device Having the Buffer Layer - A method of forming a buffer layer for a nitride compound semiconductor light emitting device includes placing a sapphire (Al | 10-16-2008 |
20080258267 | Method of Producing Semiconductor Device and Semiconductor Device - A method of producing a semiconductor device which can reliably perform conductor filling to form a through hole electrode by a simple method is provided. A method of producing a semiconductor device of the present invention includes the steps of thinning a substrate from its back side in a state in which a first supporting body is attached to the front side of the substrate, removing the first supporting body from the substrate and attaching a second supporting body having an opening to the back side of the substrate, forming a through hole communicating with the opening of the second supporting body in the substrate before or after attaching the second supporting body, forming an insulating film within the through hole, and filling a conductor into the through hole of the substrate. | 10-23-2008 |
20080272466 | SEMICONDUCTOR SUBSTRATES INCLUDING VIAS OF NONUNIFORM CROSS SECTION AND ASSOCIATED STRUCTURES - Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the form of a hollow ball, extending laterally further within the wafer than the first portion. Backgrinding the wafer to the second portion of the via may create a vent. A conductive path may be formed by filling the via with a conductive material, such as solder. Flux gases may escape through the vent. The wafer surrounding the second portion of the via may be removed, exposing a conductive element in the shape of a ball, the shape of the second portion of the via. Semiconductor devices including the conductive paths of the present invention are also disclosed. | 11-06-2008 |
20080296735 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the present invention, a first circuit pattern | 12-04-2008 |
20080308910 | SEMINCONDUCTOR DEVICE INCLUDING THROUGH-WAFER INTERCONNECT STRUCTURE - Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the first surface of the substrate. The through-wafer interconnect may include an electrically conductive material extending from the first surface of the substrate to the second, opposing surface of the substrate. The through-wafer interconnect may also include a first dielectric material disposed between the electrically conductive material and the substrate and extending from the second, opposing surface of the substrate to the first portion of the conductive material. Additionally, the through-wafer interconnect may include a second dielectric material disposed over a portion of the electrically conductive material and exhibiting a surface that defines a blind aperture extending from the first surface toward the second, opposing surface. | 12-18-2008 |
20080315367 | WIRING SUBSTRATE - There is provided a wiring substrate. The wiring substrate includes: a semiconductor substrate having a through hole; an insulating film provided to cover an upper surface, a lower surface and a first surface of the semiconductor substrate, the first surface corresponding to a side surface of the through hole; a through electrode provided in the through hole; a first wiring pattern disposed on an upper surface side of the semiconductor substrate and coupled to the through electrode; and a second wiring pattern disposed on a lower surface side of the semiconductor substrate and coupled to the through electrode. A first air gap is provided between the first wiring pattern and the insulating film formed on the upper surface, and a second air gap is provided between the second wiring pattern and the insulating film formed on the lower surface. | 12-25-2008 |
20080315368 | Silicon Wafer Having Through-Wafer Vias - A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is lined with the dielectric material. The trench is filled with a conductive material. An electrical component is electrically connected to the conductive material exposed at the first main surface. A cap is mounted to the first main surface. The cap encloses the electrical component and the electrical connection. | 12-25-2008 |
20090008747 | Semiconductor device and method for manufacturing thereof - A semiconductor device | 01-08-2009 |
20090014843 | MANUFACTURING PROCESS AND STRUCTURE OF THROUGH SILICON VIA - A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions. | 01-15-2009 |
20090020855 | METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME - A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked. | 01-22-2009 |
20090039472 | STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER - A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced. | 02-12-2009 |
20090045487 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME AND STACKED PACKAGE HAVING THE SAME - A semiconductor chip, a method of fabricating the same and a stacked package having the same are disclosed. The semiconductor chip includes a wafer, a semiconductor device disposed on the wafer, an insulating layer covering the semiconductor device and disposed on the wafer, a deep via formed to penetrate the wafer and the insulating layer, and a heat dissipation member spaced at a predetermined interval from the deep via and penetrating at least a portion of the insulating layer for dissipating heat generated by the deep via. | 02-19-2009 |
20090051012 | Through-hole interconnection structure for semiconductor wafer - A through-hole interconnection structure for a semiconductor wafer, in which: the each wafer includes at least a first wafer and a second wafer electrically connected to the first wafer; an electrical signal connecting section of the second wafer is provided to protrude from a bonding surface of the second wafer, the bonding surface being bonded with the first wafer; and the electrical signal connecting section has a cross section with a curved line or two or more straight lines extending in different directions when the second wafer is seen along a cross section parallel to the bonding surface. | 02-26-2009 |
20090057844 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device | 03-05-2009 |
20090057845 | APPARATUS TO SAW WAFER AND HAVING NOZZLE TO REMOVE BURRS IN SCRIBE LANES, METHOD OF SAWING WAFER, AND SEMICONDUCTOR PACKAGE FABRICATED BY THE SAME - An apparatus to saw a wafer and having a nozzle to remove burrs in scribe lanes, a method of sawing a wafer, and a semiconductor package fabricated by the same. The apparatus includes a blade to cut scribe lanes of the wafer and a burr removing nozzle disposed spaced apart from the blade. The burr removing nozzle removes metal burrs generated adjacent to the blade during cutting the wafer. | 03-05-2009 |
20090065904 | SUBSTRATE HAVING THROUGH-WAFER VIAS AND METHOD OF FORMING - An annular trench region is formed at a semiconductor substrate of an electronic device that defines a conductive plug of the through-wafer via, wherein the conductive plug includes an undisturbed portion of the semiconductor substrate. | 03-12-2009 |
20090065905 | Conductive metal structure applied to a module IC and method of manufacturing the same - A conductive metal structure applied to a module IC includes a wafer, a first insulating unit, and a first conductive unit. The wafer has a main body and a through hole passing through the main body. The first insulating unit has a first inner insulating layer formed on an inner surface of the through hole and a first outer insulating layer that is extended from the first inner insulating layer and is formed on a first bottom surface of the main body. The first conductive unit has a first inner conductive layer formed on the first inner insulating layer and at least one first conductive pad formed on the first outer insulating layer. The present invention integrates semiconductor technologies of etching and deposition and combines them with the development of the module IC in order to provide a conductive metal structure that has lower cost and is manufactured easily. | 03-12-2009 |
20090065906 | SEMICONDUCTOR DEVICE AND PRODUCING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening. | 03-12-2009 |
20090065907 | Semiconductor packaging process using through silicon vias - A microelectronic unit | 03-12-2009 |
20090096065 | ELECTRICAL ISOLATION OF MONOLITHIC CIRCUITS USING A CONDUCTIVE THROUGH-HOLE IN THE SUBSTRATE - A monolithic electronic chip including: a substrate; a first circuit formed on a first circuit portion of the substrate; a second circuit formed on a second circuit portion of the substrate; and at least one conductive impedance tap formed a through-hole in the substrate. The substrate includes first and second opposing surfaces and at least one through-hole extending from the first surface to the second surface. Each of the circuit portions is disposed on one or both of the opposing surfaces. Each conductive impedance tap is coupled to the surface of the through-hole it is formed in to electrically couple the substrate to a reference voltage. The impedance between each circuit and the reference voltage via the conductive impedance tap(s) is less than the crosstalk impedance between the first circuit and the second circuit via the substrate. | 04-16-2009 |
20090102021 | Through-Silicon Vias and Methods for Forming the Same - An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad. | 04-23-2009 |
20090102022 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which minimizes the line width of a pattern and allows a low temperature oxide film and a thinly formed photoresist film to serve as ion blockers when performing an ion implantation process on the semiconductor substrate. | 04-23-2009 |
20090108411 | SILICON SUBSTRATE FOR PACKAGE - In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity. | 04-30-2009 |
20090115026 | SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIAS FOR HIGH CURRENT,HIGH FREQUENCY, AND HEAT DISSIPATION - An integrated circuit device ( | 05-07-2009 |
20090121323 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including an active surface and an inactive surface which faces the active surface, a device isolation layer and a pad stacked on the active surface; and a through electrode disposed in a first via hole and a second via hole and including a protruding part that protrudes from the pad, the first via hole penetrating the semiconductor substrate, the second via hole penetrating the device insulation layer and the pad continuously, wherein at least a surface of the protruding part of the through electrode is formed of an oxidation resistance-conductive material. | 05-14-2009 |
20090127667 | Semiconductor chip device having through-silicon-via (TSV) and its fabrication method - A semiconductor device with TSV and its fabrication method are revealed. The semiconductor device primarily comprises a chip and a flexible metal wire inside. A redistributed trace layer and a passivation layer are formed on the active surface of the chip. A through hole penetrates the chip from the active surface to the back surface, in which an insulation layer is disposed. The flexible metal wire has a first terminal and a second terminal where the first terminal is bonded to a redistributed pad of the redistributed trace layer and the second terminal passes through the through hole and protrudes from the back surface of the chip. Therefore, the flexible metal wire passing through the chip has two protruded integral terminals to achieve high stress resistance TSV with lower costs for good electrical connections of vertical stacking chips. | 05-21-2009 |
20090127668 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF - A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed. | 05-21-2009 |
20090134497 | Through Substrate Via Semiconductor Components - A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench. | 05-28-2009 |
20090134498 | SEMICONDUCTOR APPARATUS - The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material. | 05-28-2009 |
20090140394 | Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die. | 06-04-2009 |
20090140395 | EDGE SEAL FOR THRU-SILICON-VIA TECHNOLOGY - One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel. | 06-04-2009 |
20090146261 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device having a VIA hole without disconnection caused by step is achieved. | 06-11-2009 |
20090160030 | METHODS FOR FORMING THROUGH WAFER INTERCONNECTS AND STRUCTURES RESULTING THEREFROM - The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed. | 06-25-2009 |
20090166811 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a semiconductor chip and through electrodes formed passing through the semiconductor chip. A ground layer connected to the through electrode and a patch antenna connected to the through electrode are provided through an inorganic insulating layer formed of SiO | 07-02-2009 |
20090179305 | SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - According to the present invention, on a double-sided substrate | 07-16-2009 |
20090184400 | VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE - Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via. | 07-23-2009 |
20090189256 | MANUFACTURING PROCESS OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate. | 07-30-2009 |
20090212400 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND MOUNTING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate having an active region on a surface thereof; at least one electrode pad provided in a peripheral portion of the surface of the semiconductor substrate; and a through electrode extending through the semiconductor substrate and connected to the electrode pad. A taper is provided on at least one side of the semiconductor substrate, whereby a portion of the through electrode which is exposed to a side of the semiconductor substrate serves as an external electrode. | 08-27-2009 |
20090243045 | Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection - A semiconductor package includes a semiconductor die having a contact pad formed over a top surface of the semiconductor die. The semiconductor die may include an optical device. In one embodiment, a second semiconductor die is deposited over the semiconductor die. The package includes an insulating material deposited around a portion of the semiconductor die. In one embodiment, the insulating material includes an organic material. A first through hole via (THV) is formed in the insulating material using a conductive material. The first THV may form a protrusion extending beyond a bottom surface of the semiconductor die opposite the top surface and be connected to a first semiconductor device. A redistribution layer (RDL) may be deposited over the semiconductor die. The RDL forms an electrical connection between the contact pad of the semiconductor die and the first THV. | 10-01-2009 |
20090243046 | Pulse-Laser Bonding Method for Through-Silicon-Via Based Stacking of Electronic Components - There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component such that the holes are in alignment, and a pulse of laser energy is applied to form a bond between the metal plugs. | 10-01-2009 |
20090243047 | Semiconductor Device With an Interconnect Element and Method for Manufacture - A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material. | 10-01-2009 |
20090261457 | DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET - A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die. | 10-22-2009 |
20090261458 | THROUGH-ELECTRODE, CIRCUIT BOARD HAVING A THROUGH-ELECTRODE, SEMICONDUCTOR PACKAGE HAVING A THROUGH-ELECTRODE, AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SEMICONDUCTOR CHIP OR PACKAGE HAVING A THROUGH-ELECTRODE - A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad disposed at a portion corresponding to the first pad and blocking the through-hole; and a through-electrode disposed within the through-hole, and having a pillar shaped core supported by the second pad, a through-electrode unit disposed over a surface of the core and electrically connected with the second pad, a first metal layer interposed between the core and the through electrode unit, and a second metal layer interposed between an inner surface of the first semiconductor chip formed by the through-hole and the through-electrode unit. | 10-22-2009 |
20090267194 | SEMICONDUCTOR CHIP HAVING TSV (THROUGH SILICON VIA) AND STACKED ASSEMBLY INCLUDING THE CHIPS - A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring. Accordingly, a plurality of semiconductor chip can be stacked each other with accurate alignment without shifting to effectively reduce the stacked assembly height, moreover, chip stacking processes are accomplished by vertically stacking a plurality of chips first then filling conductive material into the through holes without electrical short between the adjacent bonding pads due to overflow of conductive material to meet the fine-pitch requirements of TSV. The process flow for the stacked assembly is simplified with higher production yields. | 10-29-2009 |
20090278237 | THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE - A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture. | 11-12-2009 |
20090278238 | TSVS HAVING CHEMICALLY EXPOSED TSV TIPS FOR INTEGRATED CIRCUIT DEVICES - A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch. | 11-12-2009 |
20090283871 | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack - A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside. | 11-19-2009 |
20090283872 | PACKAGE STRUCTURE OF THREE-DIMENSIONAL STACKING DICE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a package structure of three-dimensional stacking dice and its manufacturing method. This invention employs the Through-Silicon-Vias (TSVs) technology to establish vertical electrical connection of the three-dimensional stacking dice and a redistribution layer between a blind hole-on-pad and a vertical through hole formed by the TSVs technology to direct the electrical connection from a first surface to an opposite second surface of this structure. In addition, this invention employs a conductive bump completely covering the pads jointed together between the stacking dice to avoid breakage of the pads. The reliability of the three-dimensional stacking dice of the present invention is increased. | 11-19-2009 |
20090294914 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 12-03-2009 |
20090294915 | TSV-Enabled Twisted Pair - A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace. | 12-03-2009 |
20090294916 | BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING - There is described a hybrid bonding method for through-silicon-via based wafer stacking. Patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bondng is used to electrically connect the vias. The adhesive layers are patterned to enable outgassing and to provide stress relief. | 12-03-2009 |
20090302429 | Electrically Conducting Connection with Insulating Connection Medium - A device comprising a first component ( | 12-10-2009 |
20090302430 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r | 12-10-2009 |
20090315154 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 12-24-2009 |
20090321892 | SEMICONDUCTOR PACKAGE USING THROUGH-ELECTRODES HAVING VOIDS - A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package. | 12-31-2009 |
20090321893 | Multi-die integrated circuit device and method - In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die. | 12-31-2009 |
20100001378 | Through-substrate vias and method of fabricating same - An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, and depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole. The isolation material may be prepared by activating it with a seed layer deposited by ALD. The via hole is preferably formed by dry etching first and second cavities having respective diameters into the substrate's top and bottom surfaces, respectively, to form a single continuous aperture through the substrate. The present method may be practiced at temperatures of less than 200° C. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias. | 01-07-2010 |
20100001379 | Multi-chip package (MCP) having three dimensional mesh-based power distribution network, and power distribution method of the MCP - A MCP includes a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being stacked to define a three-dimensional (3D) structure, and a mesh structure, the mesh structure interconnecting the plurality of semiconductor memory devices to define a 3D mesh-based power distribution network. | 01-07-2010 |
20100013060 | METHOD OF FORMING A CONDUCTIVE TRENCH IN A SILICON WAFER AND SILICON WAFER COMPRISING SUCH TRENCH - A method of forming a conductive trench such as a through-silicon-via in a silicon wafer is disclosed. The method includes depositing a mask over a wafer surface; patterning the mask to expose a portion of the wafer; exposing the wafer to a first etching step in which a first portion of the trench is formed; exposing the wafer to an second etching step in which a tapered second portion of the trench is formed, where the first portion has a continuously non-increasing width from the wafer surface to the second portion; and filling the trench with a conductive material. A silicon wafer including such a conductive trench is also disclosed. | 01-21-2010 |
20100025825 | METAL ADHESION BY INDUCED SURFACE ROUGHNESS - Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer. | 02-04-2010 |
20100032808 | THROUGH WAFER VIA AND METHOD OF MAKING SAME - A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure. | 02-11-2010 |
20100032809 | METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS - An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams. | 02-11-2010 |
20100032810 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate. | 02-11-2010 |
20100032811 | THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate. | 02-11-2010 |
20100052107 | VIAS AND METHOD OF MAKING - The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias. | 03-04-2010 |
20100052108 | VERTICAL THROUGH-SILICON VIA FOR A SEMICONDUCTOR STRUCTURE - A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via. | 03-04-2010 |
20100052109 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and 10 a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit. | 03-04-2010 |
20100052110 | SEMICONDUCTOR DEVICE COMPRISING A CARBON-BASED MATERIAL FOR THROUGH HOLE VIAS - In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized. | 03-04-2010 |
20100052111 | STACKED-CHIP DEVICE - A stacked chip device includes a first chip having a first function, and a second chip having a second function which is different from the first function, which is stacked on the first chip. The first chip is a through-silicon-via chip which is comprised of a first semiconductor substrate having first and second surfaces, a first semiconductor integrated circuit which is provided on the first surface of the first semiconductor substrate, a first conductive layer connecting to the first semiconductor integrated circuit, which goes through the first surface of the first semiconductor substrate to the second surface of the first semiconductor substrate, and a second conductive layer not connecting to the first semiconductor integrated circuit, which goes through the first surface of the first semiconductor substrate to the second surface of the first semiconductor substrate. The first and second conductive layers have the same shape and the same structure. | 03-04-2010 |
20100059865 | Package with Power and Ground Through Via - A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry. | 03-11-2010 |
20100059866 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device has a vertically offset bond on trace (BOT) interconnect structure. The vertical offset is achieved by forming a first conductive layer extending above a surface of a carrier. The first conductive layer is pressed into a surface of a substrate so that the first conductive layer is recessed below the surface of the substrate. The carrier is removed. A second conductive layer is formed above the surface of the substrate to create the vertical offset between the first and second conductive layers. The vertical offset is about 20 micrometers. A conductive via is formed through the substrate. Bond wire bumps are formed on the first and second conductive layers. The bond wire bumps are about 10 micrometers in height. A seed layer is formed over the carrier prior to forming the first conductive layer and removed after forming the second conducive layer. | 03-11-2010 |
20100065948 | Semiconductor Device and Method of Forming a Fan-In Package-on-Package Structure Using Through-Silicon Vias - A semiconductor device is made by providing a first semiconductor die having a plurality of contact pads formed over a first surface of the first semiconductor die and having a plurality of through-silicon vias (TSVs) formed within the first semiconductor die. A second semiconductor die is mounted to the first surface of the first semiconductor die using a plurality of solder bumps. At least one of the solder bumps is in electrical communication with the TSVs in the first semiconductor die. The second semiconductor die is mounted to a printed circuit board (PCB) using an adhesive material. A plurality of solder bumps is formed to connect the contact pads of the first semiconductor die to the PCB. An encapsulant is deposited over the first semiconductor die and the second semiconductor die. An interconnect structure is formed over a back surface of the PCB. | 03-18-2010 |
20100065949 | Stacked Semiconductor Chips with Through Substrate Vias - Structures and methods of forming stacked chips are disclosed. In one embodiment, a first chip is disposed over a second chip, a top surface of the first and the second chip includes active circuitry. A first through substrate via is disposed within the first chip, the first through substrate via includes a protruding tip projecting below a bottom surface of the first chip, the bottom surface being opposite the top surface. A second through substrate via is disposed on the second chip, the second through substrate via including an opening, wherein the first protruding tip of the first chip is disposed within the opening of the second chip. | 03-18-2010 |
20100072579 | Through Substrate Conductors - Structures and methods of forming through substrate vias are disclosed. In one embodiment, the method includes forming a through substrate opening from a top surface of a substrate, the top surface including active devices, and filling the first through substrate opening with an ancillary material. A conductive capping layer is formed over the ancillary material to cap the first through substrate opening. The substrate is thinned from a back surface to expose a portion of the ancillary material, the back surface being opposite to the top surface. The ancillary material is removed from the first through substrate opening, and a conductor is formed by filling a conductive material into the through substrate opening. | 03-25-2010 |
20100078770 | Lock and Key Through-Via Method for Wafer Level 3 D Integration and Structures Produced - A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art. | 04-01-2010 |
20100078771 | On-Chip RF Shields with Through Substrate Conductors - Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit. | 04-01-2010 |
20100078772 | PACKAGING TECHNOLOGY - Metallised through silicon vias located in the scribe lanes between die are used to create an electrical connection between the front-side and the rear-side of a silicon die. One of the metallisation layers on the front-side of the die comprises portions which extend into the scribe lanes to form capture pads for the through silicon vias. The rear-side of the wafer is metallised and this metallisation may, in some embodiments, be patterned to form tracks or components. The silicon die may be used to create improved package on package devices. In other examples, other substrate materials may be used. | 04-01-2010 |
20100084747 | Zigzag Pattern for TSV Copper Adhesion - A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad. | 04-08-2010 |
20100090317 | Interconnect Structures and Methods - Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece. | 04-15-2010 |
20100090318 | Backside Connection to TSVs Having Redistribution Lines - An integrated circuit structure includes a semiconductor substrate including a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, and has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. The integrated circuit structure further includes a passivation layer over the RDL; an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and a nickel layer in the opening and contacting the RDL. | 04-15-2010 |
20100090319 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 04-15-2010 |
20100109129 | WAFER LEVEL BUCK CONVERTER - A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die. | 05-06-2010 |
20100117201 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 05-13-2010 |
20100133660 | METHOD FOR PRODUCING INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate ( | 06-03-2010 |
20100133661 | METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS - A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole. | 06-03-2010 |
20100133662 | SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies. | 06-03-2010 |
20100140749 | SEMICONDUCTOR DEVICE - A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin. | 06-10-2010 |
20100140750 | Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System - An IC device is constructed in a manner that allows for the memory and processor elements to be positioned one above the other on parallel planes of a 3-D structure. Interconnections between the memory(s) and the processor(s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor. | 06-10-2010 |
20100140751 | Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure - A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area. | 06-10-2010 |
20100140752 | Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief - A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion. | 06-10-2010 |
20100140753 | Stacked Semiconductor Component Having Through Wire Interconnect And Method Of Fabrication - A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on the semiconductor substrates of the stacked array in electrical contact with contacts on the semiconductor substrates. A method for fabricating the semiconductor component includes the steps of stacking the semiconductor substrates in a stacked array with aligned vias; threading a wire through the aligned vias; and forming a plurality of electrical connections between the wire and the contacts on the semiconductor substrates. | 06-10-2010 |
20100148316 | Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV - A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV. | 06-17-2010 |
20100171196 | ELECTRICALLY SHIELDED THROUGH-WAFER INTERCONNECT - Through-Wafer Interconnections allow for the usage of cost-effective substrates for detector chips. According to an exemplary embodiment of the present invention, detecting element for application in an examination apparatus may be provided, comprising a wafer with a sensitive region and a coaxial through-wafer interconnect structure. This may reduce the susceptibility of the interconnection by providing an effective shielding. | 07-08-2010 |
20100171197 | Isolation Structure for Stacked Dies - An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed. | 07-08-2010 |
20100176494 | Through-Silicon Via With Low-K Dielectric Liner - A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place. | 07-15-2010 |
20100200961 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 08-12-2010 |
20100219511 | CARBON NANOTUBE-SOLDER COMPOSITE STRUCTURES FOR INTERCONNECTS, PROCESS OF MAKING SAME, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME - A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used. | 09-02-2010 |
20100224965 | THROUGH-SILICON VIA STRUCTURE AND METHOD FOR MAKING THE SAME - A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material. | 09-09-2010 |
20100224966 | Stress Barrier Structures for Semiconductor Chips - Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump. | 09-09-2010 |
20100237471 | Semiconductor Die and Method of Forming Through Organic Vias Having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 09-23-2010 |
20100237472 | Chip Guard Ring Including a Through-Substrate Via - At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip. | 09-23-2010 |
20100244201 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor substrate including a first integrated circuit, a second semiconductor substrate mounted over the first semiconductor substrate, the second semiconductor substrate including a second integrated circuit, a post made of an inorganic substance and formed over the first semiconductor substrate, an adhesive layer made of an organic substance arranged between the first and the second semiconductor substrates, and a substrate-through-via made of an electrical conductor extending through the second semiconductor substrate and the post, the substrate-through-via extending to the first semiconductor substrate. | 09-30-2010 |
20100244202 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and its manufacturing method, the semiconductor device comprising: a semi-insulating substrate | 09-30-2010 |
20100258917 | CONDUCTIVE THROUGH CONNECTION AND FORMING METHOD THEREOF - A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular. | 10-14-2010 |
20100258918 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE EMPLOYING THEREOF - A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode. | 10-14-2010 |
20100264521 | Semiconductor Component Having Through Wire Interconnect (TWI) With Compressed Wire - A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact. | 10-21-2010 |
20100270657 | Chip-on-board package - Provided is a chip-on-board package. The chip-on-board package may include a board, a grounding pad on a first surface of the board, the grounding pad including a body portion and at least one line portion, and at least two conductive pads on the first surface, the at least two conductive pads being arranged adjacent to the body portion. The at least one line portion may extend between the at least two conductive pads and the at least one line portion may have a narrower width than the at least two conductive pads. | 10-28-2010 |
20100276786 | Through Substrate Vias - Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal. | 11-04-2010 |
20100276787 | Wafer Backside Structures Having Copper Pillars - An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL. | 11-04-2010 |
20100283130 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate having a first surface as a surface on which an element is formed, and a second surface opposite to the first surface; a through hole formed so as to extend through the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through hole; and a conductive portion formed in a space surrounded by the insulating film in the through hole. The insulating film continuously extends on the inner wall of the through hole and on the second surface. | 11-11-2010 |
20100308443 | Semiconductor Device and Method of Forming an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure. | 12-09-2010 |
20100320575 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 12-23-2010 |
20110018107 | TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices - A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch. | 01-27-2011 |
20110068437 | Semiconductor Element Having a Conductive Via and Method for Making the Same and Package Having a Semiconductor Element with a Conductive Via - The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased. | 03-24-2011 |
20110068438 | SEMICONDUCTOR DEVICE - In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna. | 03-24-2011 |
20110073997 | Semiconductor Structure and Method for Making Same - One or more embodiments relate to a method for making a semiconductor structure, the method including: forming a first conductive interconnect at least partially through the substrate; and forming a second conductive interconnect over the substrate, wherein the first conductive interconnect and the second conductive interconnect are formed at least partially simultaneously. | 03-31-2011 |
20110084365 | Through Silicon Via (TSV) Wire Bond Architecture - A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads. | 04-14-2011 |
20110108958 | Metal Oxide Semiconductor (MOS)-Compatible High-Aspect Ratio Through-Wafer Vias and Low-Stress Configuration Thereof - A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed. | 05-12-2011 |
20110108959 | Semiconductor Component Having Through Wire Interconnect With Compressed Bump - A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components. | 05-12-2011 |
20110121433 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip and a stacked semiconductor package are presented. The semiconductor chip includes a semiconductor substrate, circuit patterns, first input/output pads and second input/output pads. The semiconductor substrate is divided into cell and peripheral regions and has first and second surfaces which oppose each other. The circuit patterns are formed on the first surface of the semiconductor substrate and are connected with the cell region and the peripheral region. The first input/output pads are formed in the cell region and are connected to the circuit patterns. The second input/output pads are formed in the peripheral region and connected with the circuit patterns. | 05-26-2011 |
20110127649 | 3D INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove. | 06-02-2011 |
20110163422 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF PRINTING ON SEMICONDUCTOR WAFER - A method of printing on a semiconductor wafer, a manufacturing method of a semiconductor device, and a semiconductor device which enable to easily perform positioning in the direction perpendicular to the top of the wafer and to easily identify the type of the wafer. The manufacturing method includes preparing a semiconductor wafer having a structure in which an element forming film is stacked on the top of an insulative transparent substrate, forming a light reflection film to reflect light for positioning on the bottom of the transparent substrate, irradiating a laser from the side at which the element forming film is disposed so as to form printed letters at the light reflection film, forming a semiconductor element at the element forming film, forming an interlayer dielectric film to cover the element forming film and the semiconductor element, forming a contact wire, and forming a metal wire on the interlayer dielectric film. | 07-07-2011 |
20110163423 | METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME - A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked. | 07-07-2011 |
20110169139 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole. | 07-14-2011 |
20110169140 | RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS - Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV. | 07-14-2011 |
20110175206 | SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies. | 07-21-2011 |
20110180908 | WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other. | 07-28-2011 |
20110186968 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions. | 08-04-2011 |
20110193199 | ELECTROMIGRATION IMMUNE THROUGH-SUBSTRATE VIAS - A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions. | 08-11-2011 |
20110198732 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate. | 08-18-2011 |
20110204485 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion. | 08-25-2011 |
20110204486 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other. | 08-25-2011 |
20110204487 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate; a through electrode passing through the semiconductor substrate in a thickness direction of the semiconductor substrate; an internal electrode provided in a part of the top surface of the semiconductor substrate and electrically connected to the through electrode which reaches the part; a first protective film covering the top surface except a part of the internal electrode; a second protective film formed apart from the first protective film, on the part of the internal electrode, the part being not covered by the first protective film; and metal wiring formed on the back surface of the semiconductor substrate and electrically connected to the through electrode, the second main surface being on a side of the semiconductor substrate opposite the first main surface. | 08-25-2011 |
20110210426 | SEMICONDUCTOR DEVICE PROVIDING A FIRST ELECTRICAL CONDUCTOR AND A SECOND ELECTRICAL CONDUCTOR IN ONE THROUGH HOLE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device | 09-01-2011 |
20110215442 | ALIGNMENT OF WAFERS FOR 3D INTEGRATION - A method of aligning substrates, e.g., semiconductor wafers, is provided in which a first substrate can be at least coarsely aligned atop a second substrate. Each substrate can have a pattern thereon, wherein the pattern of the first substrate can be aligned with a window of the first substrate. A return signal can be returned from simultaneously illuminating the patterns of the first and second substrates through the window in the first substrate. The return signal can be compared to at least one stored signal to determine relative misalignment between the first and second substrates. A position of at least one of the first and second substrates can be altered relative to a position of the other of the first and second substrates to address the misalignment. | 09-08-2011 |
20110215443 | Multichip semiconductor device, chip therefor and method of formation thereof - A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug. | 09-08-2011 |
20110221044 | TUNGSTEN BARRIER AND SEED FOR COPPER FILLED TSV - Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described. | 09-15-2011 |
20110241180 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, METHOD FOR DETECTING A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CHIP PACKAGE - A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness. | 10-06-2011 |
20110260297 | THROUGH-SUBSTRATE VIA AND FABRICATION METHOD THEREOF - A method for fabricating a through-substrate via structure. A semiconductor substrate is provided. A first via hole is etched into the semiconductor substrate. A spacer is formed on sidewall of the first via hole. The semiconductor substrate is etched through the first via hole to form a second via hole. The second via hole is wet etched to form a bottle-shaped via hole. An insulating layer is formed lining a lower portion of the bottle-shaped via hole. A first conductive layer is deposited within the bottle-shaped via hole, wherein the first conductive layer define a cavity. A bond pad is formed on a front side of the semiconductor substrate, wherein the bond pad is electrically connected with the first conductive layer. A back side of the semiconductor substrate is polished to reveal the cavity. The cavity is filled with a second conductive layer. | 10-27-2011 |
20110266658 | ISOLATED WIRE BOND IN INTEGRATED ELECTRICAL COMPONENTS - An electrical component includes a semiconductor layer having a first conductivity type and a interconnect layer disposed adjacent to a frontside of the semiconductor layer. At least one bond pad is disposed in the interconnect layer and formed adjacent to the frontside of the semiconductor layer. An opening formed from the backside of the semiconductor layer and through the semiconductor layer exposes at least a portion of the bond pad. A first region having a second conductivity type extends from the backside of the semiconductor layer to the frontside of the semiconductor layer and surrounds the opening. The first region can abut a perimeter of the opening or alternatively, a second region having the first conductivity type can be disposed between the first region and a perimeter of the opening. | 11-03-2011 |
20110291245 | Semiconductor Device with Substrate-Side Exposed Device-Side Electrode and Method of Fabrication - A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE. | 12-01-2011 |
20110291246 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE WITH STACK CHIP STRUCTURE - A semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material. The filling material fills a gap between the semiconductor chips. | 12-01-2011 |
20110298097 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is provided wherein stacked semiconductor substrates are electrically coupled together in a satisfactory state by a conductor buried in the interior of a through hole. A first semiconductor substrate includes a substrate having main surfaces, further includes a semiconductor element formed within and over the substrate, a wiring coupled to the semiconductor element electrically, and a conductive layer formed in the interior of a through hole, the through hole extending through mutually confronting first and second main surfaces as the main surfaces of the substrate and reaching the wiring. The first semiconductor substrate and a second semiconductor substrate are stacked and the conductive layer is coupled to a wiring of the second semiconductor substrate electrically. In a second main surface of the conductive layer, a recess is formed around an end portion of the through hole so that a bottom wall surface of the recess is present in the interior of the substrate. A conductive material which constitutes the conductive layer is filled in the interior of the recess. | 12-08-2011 |
20110304026 | VIA AND METHOD OF VIA FORMING AND METHOD OF VIA FILLING - An electronic or micromechanical device having first ( | 12-15-2011 |
20110304027 | SEMICONDUCTOR CHIP WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor chip includes: a device layer having a first surface and a second surface facing away from the first surface, and possessing conductive patterns, which are formed in the first surface such that at least portions of the conductive patterns are exposed on the first surface, and bonding pads, which are formed on the second surface, are electrically connected. An insulation layer pattern, formed on the first surface of the device layer, has via holes which expose the conductive patterns, and through electrodes are formed in the via holes to be electrically connected with the exposed conductive patterns. | 12-15-2011 |
20110316124 | SEMICONDUCTOR DEVICE - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 12-29-2011 |
20120007218 | SEMICONDUCTOR DEVICE WITH ONE-SIDE CONTACT AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers. | 01-12-2012 |
20120007219 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug. | 01-12-2012 |
20120018851 | METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE - A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination. | 01-26-2012 |
20120038029 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, a first insulating layer, an electrode pad, a through hole, a second insulating layer, and a conductive material. A through groove passes through the semiconductor substrate from a surface to an opposite surface. The first insulating layer fills the through groove. The electrode pad is connected with an interconnection layer. The second insulating layer is provided between the electrode pad and the first insulating layer. The through hole communicates with the electrode pad and passes through the first insulating layer and the second insulating layer. The conductive material is provided in the through hole so as to be connected with the electrode pad. | 02-16-2012 |
20120038030 | METHOD FOR FILLING CAVITIES IN WAFERS, CORRESPONDINGLY FILLED BLIND HOLE AND WAFER HAVING CORRESPONDINGLY FILLED INSULATION TRENCHES - A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to the predetermined surface of the wafer; heating the wafer at a first temperature; driving out gas bubbles enclosed in the filling material by heating the wafer under vacuum at a second temperature which is equal to or higher than the first temperature; and curing the filling material by heating the wafer at a third temperature which is higher than the second temperature. Furthermore, also described is a blind hole filled using such a method and general 3D cavities as well as a wafer having insulation trenches of a silicon via filled using such a method. | 02-16-2012 |
20120061804 | Systems and Methods for Enabling Esd Protection on 3-D Stacked Devices - An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry. | 03-15-2012 |
20120068313 | Semiconductor device and method of forming conductive TSV with insulating annular ring - A semiconductor wafer has an insulating layer formed over an active surface of the wafer. A conductive layer is formed over the insulating layer. A first via is formed from a back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. A conductive material is deposited in the first via to form a conductive TSV. An insulating material can be deposited in the first via to form an insulating core within the conductive via. After forming the conductive TSV, a second via is formed around the conductive TSV from the back surface of the semiconductor wafer through the semiconductor wafer and insulating layer to the conductive layer. An insulating material is deposited in the second via to form an insulating annular ring. The conductive via can be recessed within or extend above a surface of the semiconductor die. | 03-22-2012 |
20120074529 | SEMICONDUCTOR PACKAGE WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips. | 03-29-2012 |
20120074530 | INTERPOSER INCLUDING AIR GAP STRUCTURE, METHODS OF FORMING THE SAME, SEMICONDUCTOR DEVICE INCLUDING THE INTERPOSER, AND MULTI-CHIP PACKAGE INCLUDING THE INTERPOSER - Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element. | 03-29-2012 |
20120098106 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When a silicon through electrode is to be formed from a back surface (the surface on which a semiconductor device is not formed) of a silicon substrate, a wide range of an interlayer insulating film made of a Low-k material absorbs moisture, and there is a problem that the electrical characteristics of wiring are degraded. The above-described problem can be solved by forming at least a single ring-shaped frame laid out to enclose the silicon through electrode by using metal wirings in plural layers and a connection via connecting the upper and lower metal wirings in a Low-k material layer penetrated by the silicon through electrode and by forming a moisture barrier film made up of at least a metal wiring and a connection via between the silicon through electrode and a circuit wiring formed in the vicinity of the silicon through electrode. | 04-26-2012 |
20120104560 | SEMICONDUCTOR DEVICE HAVING A THROUGH ELECTRODE - A semiconductor device | 05-03-2012 |
20120104561 | Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits - A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring. | 05-03-2012 |
20120104562 | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die - A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer. | 05-03-2012 |
20120104563 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a second oxide film and a pad electrode on a first oxide film that is formed on a front surface of a semiconductor substrate, a contact electrode and a first barrier layer formed in the second oxide film and connected to the pad electrode, a silicide portion formed between the contact electrode and a through-hole electrode layer and connected to the contact electrode and the first barrier layer, a via hole extending from a back surface of the semiconductor substrate to reach the silicide portion and the second oxide film, a third oxide film formed on a sidewall of the via hole and on the back surface of the semiconductor substrate, and a second barrier layer and a rewiring layer formed inside the via hole and on the back surface of the semiconductor substrate and connected to the silicide portion. | 05-03-2012 |
20120112324 | THROUGH-WAFER INTERCONNECTION - A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array. | 05-10-2012 |
20120119335 | Semiconductor Device With A Plurality Of Mark Through Substrate Vias - The present invention relates to a semiconductor device with a plurality of mark through substrate vias, comprising a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying to the position and direction on the backside surface. Thus, the redistribution layer (RDL) or the special equipment for achieving the backside alignment (BSA) is not necessary. | 05-17-2012 |
20120126373 | SEMICONDUCTOR DEVICE INCLUDING INNER INTERCONNECTION STRUCTURE - A semiconductor device includes a semiconductor chip and an inner interconnection structure. The semiconductor chip includes a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals. The inner interconnection structure includes horizontal buried conductive lines and vertical connection lines disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals. | 05-24-2012 |
20120133030 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 05-31-2012 |
20120175744 | COPPER ELECTROPLATING COMPOSITION - The present invention relates to a copper electroplating composition comprising a copper alkanesulfonate salt, a free alkanesulfonic acid, and one or more organic compounds selected from the group consisting of suppressors, accelerators, levelers, and mixtures thereof, in which the concentration of free acid is from 0 M to about 0.25 M and the composition is free of halide ions. The present invention also relates to a process of metalizing micro-sized trenches or vias in a substrate using the composition. | 07-12-2012 |
20120181672 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening. | 07-19-2012 |
20120187545 | DIRECT THROUGH VIA WAFER LEVEL FANOUT PACKAGE - Methods, systems, and apparatuses are described for improved integrated circuit packages. An integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing one or both surfaces of the semiconductor substrate. The die is mounted to the first surface of the semiconductor substrate. An encapsulating material encapsulates the die on the first surface of the semiconductor substrate. | 07-26-2012 |
20120211872 | SEMICONDUCTOR DEVICE - A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device | 08-23-2012 |
20120217620 | SEMICONDUCTOR APPARATUS - The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR | 08-30-2012 |
20120228745 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate. | 09-13-2012 |
20120228746 | SEMICONDUCTOR DEVICE, FABRICATION PROCESS, AND ELECTRONIC DEVICE - A semiconductor device includes: a semiconductor substrate that includes a semiconductor; an electrode layer formed on a first surface side inside the semiconductor substrate; a frame layer laminated on the first surface of the semiconductor substrate; a conductor layer formed in an aperture portion formed by processing the semiconductor substrate and the frame layer in such a manner as to expose the electrode layer on the first surface of the semiconductor substrate; a vertical hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate. | 09-13-2012 |
20120241915 | Semiconductor Device and Method of Forming Leadframe With Notched Fingers for Stacking Semiconductor Die - A semiconductor device has a leadframe with first and second opposing surfaces and a plurality of notched fingers. The leadframe is mounted to a carrier. A first semiconductor die is mounted over the carrier between the notched fingers. Conductive TSVs are formed through the first semiconductor die. A bond wire is formed between a first contact pad on the first semiconductor die and notched finger. The conductive TSV are electrically connected to the bond wires. An encapsulant is deposited over the first semiconductor die and notched fingers. Bumps are formed over the first surface of the leadframe. The carrier is removed and the leadframe is singulated. The leadframe and first semiconductor die is mounted to a substrate. A second semiconductor die is mounted to a second contact pad on the first semiconductor die. A third semiconductor die is mounted to the second surface of the leadframe. | 09-27-2012 |
20120248579 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer. | 10-04-2012 |
20120248580 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate. | 10-04-2012 |
20120256300 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor. | 10-11-2012 |
20120261801 | Wiring Board, Semiconductor Device, and Method for Manufacturing Wiring Board - A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole. | 10-18-2012 |
20120280366 | RADIO- AND ELECTROMAGNETIC INTERFERENCE THROUGH-SILICON VIAS FOR STACKED- DIE PACKAGES, AND METHODS OF MAKING SAME - An apparatus includes a radio-frequency die with shielding through-silicon vias and a die backside lattice lid that shield a sector in the RF die from radio - and electromagnetic interference. | 11-08-2012 |
20120286400 | Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device - A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias. | 11-15-2012 |
20120286401 | 3D INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove. | 11-15-2012 |
20120292745 | Semiconductor Device and Method of Forming 3D Semiconductor Package with Semiconductor Die Stacked Over Semiconductor Wafer - A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die. | 11-22-2012 |
20120292746 | SEMICONDUCTOR DEVICES INCLUDING STRESS RELIEF STRUCTURES - A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed. | 11-22-2012 |
20120306057 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured. | 12-06-2012 |
20120319248 | STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS - A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC. | 12-20-2012 |
20120326281 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity. | 12-27-2012 |
20120326282 | METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES - Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die. | 12-27-2012 |
20120326283 | Interconnect Regions - Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous. | 12-27-2012 |
20130020683 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit. | 01-24-2013 |
20130026606 | TSV PILLAR AS AN INTERCONNECTING STRUCTURE - The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch. | 01-31-2013 |
20130032929 | METHOD OF PROTECTING DEEP TRENCH SIDEWALL FROM PROCESS DAMAGE - Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region. | 02-07-2013 |
20130032930 | SEMICONDUCTOR DEVICE COMPRISING THROUGH-ELECTRODE INTERCONNECT - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 02-07-2013 |
20130037917 | WAFER LEVEL CHIP SCALE PACKAGE WITH THICK BOTTOM METAL EXPOSED AND PREPARATION METHOD THEREOF - A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices. | 02-14-2013 |
20130062736 | POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS - A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core. | 03-14-2013 |
20130082359 | REMOVING CONDUCTIVE MATERIAL TO FORM CONDUCTIVE FEATURES IN A SUBSTRATE - Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate. | 04-04-2013 |
20130087892 | Electrical Connection for Chip Scale Packaging - A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion. | 04-11-2013 |
20130087893 | Through Silicon Via Structure, Method of Formation, and Integration in Semiconductor Substrate - Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate. | 04-11-2013 |
20130093061 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film. | 04-18-2013 |
20130099359 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape. | 04-25-2013 |
20130099360 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer. | 04-25-2013 |
20130113084 | SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER - Various semiconductor substrates and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor chip on a side of a first substrate. The first substrate has at least one thru-silicon-via. An insulating layer is molded on the side of the first substrate. The insulating layer provides a support structure to enable handling of the first substrate. | 05-09-2013 |
20130119521 | Through-Silicon Via With Low-K Dielectric Liner - A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place. | 05-16-2013 |
20130127019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH SILICON VIA ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed. | 05-23-2013 |
20130140680 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an active region located in an upper portion of a semiconductor substrate; a through-hole electrode penetrating the substrate, and made of a conductor having a thermal expansion coefficient larger than that of a material for the substrate; and a stress buffer region located in the upper portion of the substrate and sandwiched between the through-hole electrode and the active region. The stress buffer region does not penetrate the substrate and includes a stress buffer part made of a material having a thermal expansion coefficient larger than that of the material for the substrate and an untreated region where the stress buffer part is not present. The stress buffer part is located in at least two locations sandwiching the untreated region in a cross section perpendicular to a surface of the substrate and passing through the through-hole electrode and the active region. | 06-06-2013 |
20130140681 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 06-06-2013 |
20130147020 | Component Having a Via and Method for Manufacturing It - An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer. | 06-13-2013 |
20130161796 | THROUGH SILICON VIA AND METHOD OF FORMING THE SAME - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV. | 06-27-2013 |
20130168832 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device is provided such that a penetrating via with a conductive material embedded through a medium of an insulating film is formed in a through hole of a p-type semiconductor substrate. The semiconductor device includes an n-type well on an upper section of the p-type semiconductor substrate in the vicinity of the penetrating via, an electrode connected to the n-type well, and the electrode connected to the p-type semiconductor substrate in the vicinity of the electrode. | 07-04-2013 |
20130175673 | INTEGRATED CIRCUIT DEVICES INCLUDING THROUGH-SILICON-VIAS HAVING INTEGRAL CONTACT PADS - An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole. | 07-11-2013 |
20130181330 | INTEGRATING THROUGH SUBSTRATE VIAS INTO MIDDLE-OF-LINE LAYERS OF INTEGRATED CIRCUITS - A semiconductor wafer has an integrated, through substrate, via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion. | 07-18-2013 |
20130187258 | Sawing Underfill in Packaging Processes - A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components. | 07-25-2013 |
20130207241 | Semiconductor Devices Having Through-Vias and Methods for Fabricating the Same - The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole. | 08-15-2013 |
20130207242 | Semiconductor Devices Having Through-Vias and Methods for Fabricating the Same - Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer. | 08-15-2013 |
20130214389 | INTEGRATED CIRCUIT - An integrated circuit includes a first chip having a plurality of through-chip vias, and a second chip stacked on the first chip and having a plurality of through-chip vias which are disposed at positions corresponding to the plurality of through-chip vias of the first chip and each of which is connected with at least one through-chip via of the first chip arranged in an oblique direction, which is not on a straight line extending in a chip stacking direction, among the plurality of through-chip vias of the first chip, wherein the first chip inputs/outputs a signal through a through-chip via which is selected by first repair information among the plurality of through-chip vias of the first chip, and the second chip inputs/outputs a signal through a through-chip via which is selected by second repair information among the plurality of through-chip vias of the second chip. | 08-22-2013 |
20130214390 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 08-22-2013 |
20130221494 | STRUCTURE AND METHOD FOR STRAIN-RELIEVED TSV - A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face, The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion. | 08-29-2013 |
20130228897 | Electrical Connections for Chip Scale Packaging - Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch. | 09-05-2013 |
20130228898 | SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SUBSTRATE - Disclosed herein is a device that includes: a first semiconductor chip having a first internal circuit formed in a first substrate; and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate. The plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line. The first and second penetrating electrodes are in a floating state without electrically connected to the first internal circuit. The third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit. The fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit. The third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode. | 09-05-2013 |
20130234295 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, WIRING BOARD AND METHOD OF MANUFACTURING SAME, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE - Passivation films | 09-12-2013 |
20130234296 | INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate. | 09-12-2013 |
20130256841 | VIA PLUGS - The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes. | 10-03-2013 |
20130256842 | SEMICONDUCTOR DEVICE PACKAGING STRUCTURE AND PACKAGING METHOD - Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained. | 10-03-2013 |
20130277807 | ELECTRONIC DEVICE INCLUDING A FEATURE IN AN OPENING - A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows. | 10-24-2013 |
20130292804 | Semiconductor Device and Method of Forming a Shielding Layer over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV - A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die. | 11-07-2013 |
20130299949 | Through Silicon Via and Method of Forming the Same - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface. | 11-14-2013 |
20130313687 | Through via/the buried via elrctrolde material and the said via structure and the said via manufacturing method - [Aim of Invention] | 11-28-2013 |
20130313688 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device includes the step of forming a through hole in a semiconductor substrate. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface, and includes a first conductive layer formed on the second main surface. The through hole penetrates through the semiconductor substrate from the first main surface to the second main surface, so that the first conductive layer formed on the second main surface is exposed at a bottom portion of the through hole. The method further includes the steps of forming a seed layer on a side surface of the through hole from the bottom portion of the through hole to the first main surface; forming a second conductive layer on the seed layer through a first plating process; and forming a third conductive layer selectively on the second conductive layer. | 11-28-2013 |
20130313689 | SEMICONDUCTOR DEVICE - In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material. | 11-28-2013 |
20130313690 | SEMICONDUCTOR DEVICE - Disclosed herein is a device that includes a semiconductor substrate, a plurality of first electrodes formed over the semiconductor substrate and arranged in line in a first direction, a plurality of second electrodes formed over the semiconductor substrate and arranged in line in the first direction on a left side of an associated one of the first electrodes, and a plurality of third electrodes formed over the semiconductor substrate and arranged in line in the first direction on a right side of an associated one of the first electrodes. Each of the first electrodes is configured to be supplied with a corresponding electrical potential, whereas each of the second and third electrodes is in an electrical floating state serving as a dummy electrode. | 11-28-2013 |
20130320504 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THROUGH SILICON VIAS - A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate, and an impedance path blocking unit located between the plurality of TSVs. | 12-05-2013 |
20130320505 | SEMICONDUCTOR REFLOW PROCESSING FOR HIGH ASPECT RATIO FILL - A method for at least partially filling a feature on a workpiece includes obtaining a workpiece including a feature having a high aspect ratio in the range of about 10 to about 80, depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature. | 12-05-2013 |
20130320506 | BACK-SIDE CONTACT FORMATION - In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer. | 12-05-2013 |
20130334669 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination. | 12-19-2013 |
20130341765 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a plurality of metal terminals that are formed on a surface of the semiconductor substrate on the opposite side to a circuit-forming surface; and a resin that is formed on the surface of the semiconductor substrate on the opposite side to the circuit-forming surface, and covers at least part of side surfaces of the metal terminals, wherein upper surfaces of the metal terminals are exposed from the resin. | 12-26-2013 |
20130341766 | COMPONENT HAVING THROUGH-HOLE PLATING, AND METHOD FOR ITS PRODUCTION - A method for producing a component having a semiconductor substrate with through-hole plating is provided, the through-plating being surrounded by a recess, and the semiconductor substrate having a first layer on one side, which covers the recess on the first side. The semiconductor substrate has a second layer on a second side, which covers the recess on the second side, and the through-hole plating is surrounded by a ring structure which is produced from the semiconductor substrate. The recess surrounding the ring structure is produced in the same process step or at the same time as the recess for the through-hole plating. | 12-26-2013 |
20140001604 | SEMICONDUCTOR STRUCTURES INCLUDING FLUIDIC MICROCHANNELS FOR COOLING AND RELATED METHODS | 01-02-2014 |
20140035109 | METHOD AND STRUCTURE OF FORMING BACKSIDE THROUGH SILICON VIA CONNECTIONS - A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction. | 02-06-2014 |
20140048910 | SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING SAME - Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate. | 02-20-2014 |
20140054751 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a semiconductor package having a top surface, a bottom surface, and a through hole provided from the top surface to the bottom surface; and an electrode inserted into the through hole of the semiconductor package. The semiconductor package includes: an insulating substrate; a semiconductor chip on the insulating substrate; an electrode pattern on the insulating substrate and connected to the semiconductor chip; a resin sealing the insulating substrate, the semiconductor chip, and the electrode pattern; and an electrode section on an inner wall of the through hole and connected to the electrode pattern. The through hole penetrates the insulating substrate and the resin. The electrode inserted into the through hole is connected to the electrode section inside the semiconductor package. | 02-27-2014 |
20140061866 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate having one surface, the other surface which faces away from the one surface, and an integrated circuit which is formed on the one surface; and a shielding layershielding layer formed in the semiconductor substrate to correspond to the other surface. | 03-06-2014 |
20140061867 | METHOD FOR DEPOSITING ONE OR MORE POLYCRYSTALLINE SILICON LAYERS ON SUBSTRATE - A method for depositing one or more polycrystalline silicon layers ( | 03-06-2014 |
20140070375 | ELECTRONIC DEVICE INCLUDING A VIA AND A CONDUCTIVE STRUCTURE, A PROCESS OF FORMING THE SAME, AND AN INTERPOSER - An electronic device can include a substrate including a first region having a first thickness, and a second region having a second thickness different from the first thickness. The electronic device can include a via within the first region. The electronic device can include a conductive structure adjacent to the first region and connected to the via, wherein a combined thickness of the first thickness and a thickness of the conductive structure is thicker than the second thickness. In another embodiment, an interposer may have a similar structure, with laterally offset conductive structures that allow for lateral routing of electronic signals. A process of forming an electronic device can include forming a via and removing a portion of the substrate. The process can include forming a conductive structure connected to the via, wherein the conductive structure is adjacent to a region where the portion of the substrate has been removed. | 03-13-2014 |
20140084428 | INTEGRATED CIRCUIT WITH ELECTRICAL THROUGH-CONTACT AND METHOD FOR PRODUCING ELECTRICAL THROUGH-CONTACT - A substrate of an integrated circuit has a first surface and an opposing second surface. A functionalized region is formed at least on the first surface. At least one electrical through-plating is provided as a through-hole which is continuously filled with an electrically conductive material and which runs from the first surface to the second surface through the substrate. To ensure that the through-plating can be reliably produced and is provided in a space-saving manner, the through-hole has at least one gradation on which a transition occurs from a smaller hole cross-section on the side of the first surface to a larger hole cross-section on the side of the second surface. | 03-27-2014 |
20140091438 | MULTIPLE METAL LAYER SEMICONDUCTOR DEVICE AND LOW TEMPERATURE STACKING METHOD OF FABRICATING THE SAME - A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process. | 04-03-2014 |
20140117506 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package. | 05-01-2014 |
20140124900 | THROUGH-SILICON VIA (TSV) DIE AND METHOD TO CONTROL WARPAGE - A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer. | 05-08-2014 |
20140124901 | INTEGRATED CIRCUIT CHIPS HAVING VERTICALLY EXTENDED THROUGH-SUBSTRATE VIAS THEREIN - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 05-08-2014 |
20140131841 | METAL PAD STRUCTURE OVER TSV TO REDUCE SHORTING OF UPPER METAL LAYER - Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced. | 05-15-2014 |
20140138798 | POWER VOLTAGE SUPPLY APPARATUS FOR THREE DIMENSIONAL SEMICONDUCTOR - Provided is a power voltage supply apparatus of a 3-dimensional (3D) semiconductor. The power voltage supply apparatus includes a plurality of integrated circuits (ICs) which each include a first through silicon via (TSV) and a second TSV, are stacked such that the first TSVs are connected and second TSVs are connected, and are mounted on a printed circuit board (PCB), wherein a first PCB line formed on the PCB and supplying a first voltage is connected to a bottom of a first TSV of a bottom IC from among the plurality of ICs, and a second PCB line formed on the PCB and supplying a second voltage is connected to a top of a second TSV of a top IC. | 05-22-2014 |
20140138799 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Semiconductor packages capable of reducing a total height thereof and methods of manufacturing the semiconductor package are provided. The semiconductor package includes a semiconductor substrate having first and second surfaces opposite to each other, a semiconductor device formed on the first surface of the semiconductor substrate, pads formed on the first surface of the semiconductor substrate and electrically connected to the semiconductor device, and at least one printed circuit layer including a resin layer, via electrodes penetrating through the resin layer, and line layers formed on the first resin layer and connected to the via electrodes and attached onto the first surface of the semiconductor substrate. The via electrodes and the line layers are formed of the same type of material, and the via electrodes are electrically connected to the pads. | 05-22-2014 |
20140175614 | WAFER STACKING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A wafer stacking structure includes a first wafer and a second wafer. The first wafer includes a first through silicon via (TSV) opening and a first TSV filling portion formed in the first TSV opening and including a concave structure. The second wafer includes a second TSV opening and a second TSV filling portion formed in the second TSV opening and including a convex structure. A front surface of the first wafer faces a front surface of the second wafer, and the convex structure of the second TSV filling portion is inserted into the concave structure of the first TSV filling portion. | 06-26-2014 |
20140175615 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film. | 06-26-2014 |
20140183705 | SEMICONDUCTOR DEVICE WITH THROUGH SILICON VIA AND ALIGNMENT MARK - A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor. | 07-03-2014 |
20140197522 | HYBRID CONDUCTOR THROUGH-SILICON-VIA FOR POWER DISTRIBUTION AND SIGNAL TRANSMISSION - A method of providing signal, power and ground through a through-silicon-via (TSV), and an integrated circuit chip having a TSV that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a TSV through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via. The multitude of conductive bars include at least one signal bar, at least one power bar, and at least one ground bar. The method further comprises connecting the at least one power bar to a power voltage source to apply power through the TSV; connecting the at least one ground bar to a ground voltage; and connecting the at least one signal bar to a source of an electronic signal to conduct the signal through the TSV and to form a hybrid power-ground-signal TSV in the substrate. | 07-17-2014 |
20140203412 | THROUGH SILICON VIAS FOR SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad. | 07-24-2014 |
20140217559 | Semiconductor Devices Having Through Silicon Vias and Methods of Fabricating the Same - A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body. | 08-07-2014 |
20140217560 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion. | 08-07-2014 |
20140231966 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening. | 08-21-2014 |
20140239457 | THERMAL VIA FOR 3D INTEGRATED CIRCUITS STRUCTURES - A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion. | 08-28-2014 |
20140239458 | BONDED STRUCTURE WITH ENHANCED ADHESION STRENGTH - A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates. | 08-28-2014 |
20140246757 | THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS - Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure. | 09-04-2014 |
20140252561 | VIA-ENABLED PACKAGE-ON-PACKAGE - A via-enabled package-on-package circuit includes a first package including a first package die having a plurality of through substrate vias (TSVs). The TSVs are configured to carry the input/output signaling for at least one second package die. | 09-11-2014 |
20140252562 | SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate. | 09-11-2014 |
20140264772 | Shielding for Through-Silicon-Via - 3D integrated circuit devices include first and second semiconductor bodies. The first semiconductor body has an active area, a through-silicon-via outside the active area, and two or more disjoint guard rings. The first guard ring encircles the via. The second guard ring encircles the active area, but not the via. The guard rings can reduce the noise coupling coefficient between the via and the active area to −60 dB or less at 3 GHz and 20 μm spacing. | 09-18-2014 |
20140264773 | SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE - In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter. | 09-18-2014 |
20140284772 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE THEREOF - According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole. A first metal layer including copper is grown bottom-up from one end of the through-hole toward the other end thereof, to partially fill the through-hole, leaving a space having a depth less than the radius of the through-hole as measured from the second side surface of the substrate. A second metal layer including nickel is conformally grown in the space from the inner peripheral surface of the through-hole to a height having a summit surface protruding from the second side surface of the substrate. A third metal layer is formed on the summit surface of the second metal layer. | 09-25-2014 |
20140306322 | RELIABLE BACK-SIDE-METAL STRUCTURE - A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface. | 10-16-2014 |
20140312467 | THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES - Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining. | 10-23-2014 |
20140312468 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer. | 10-23-2014 |
20140332930 | INTEGRATED CIRCUIT DEVICE AND CONFIGURATION METHOD THEREOF - An integrated circuit device comprises N stacked first integrated circuit chips each of which includes a first circuit and N stacked second integrated circuit chips each of which includes a second circuit. The N stacked second integrated circuit chips are stacked on the N stacked first integrated circuit chips. A first and second integrated circuit chips at symmetric positions with respect to a reference surface are paired. Each of the first and second integrated circuit chips include connection terminals for connecting the first circuit of the first integrated circuit chip and the second circuit of the second integrated circuit chip in the pair, and through electrodes each penetrating an inside of the chip. The connection terminals and through electrodes are arranged to be symmetric with respect to the reference surface. | 11-13-2014 |
20140346645 | THROUGH SILICON VIA AND PROCESS THEREOF - A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole. | 11-27-2014 |
20140346646 | STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERS - A through via contains a conductor ( | 11-27-2014 |
20140361410 | SEMICONDUCTOR DEVICE - This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction. | 12-11-2014 |
20140361411 | SEMICONDUCTOR DEVICE - This invention can reduce heat that is generated in a first semiconductor chip and transfers, to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area. | 12-11-2014 |
20150041960 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment. | 02-12-2015 |
20150041961 | Through silicon via structure - A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via. | 02-12-2015 |
20150054136 | METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE - A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is <300 μm. | 02-26-2015 |
20150054137 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate. | 02-26-2015 |
20150054138 | SEMICONDUCTOR DEVICE HAVING STACKED SUBSTRATES WITH PROTRUDING AND RECESSED ELECTRODE CONNECTION - A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion. | 02-26-2015 |
20150054139 | THROUGH-SILICON VIA WITH SIDEWALL AIR GAP - Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor. | 02-26-2015 |
20150054140 | STACK OF SEMICONDUCTOR STRUCTURES AND CORRESPONDING MANUFACTURING METHOD - A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar. | 02-26-2015 |
20150061082 | CONTACT PLUG AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening. | 03-05-2015 |
20150061083 | METAL TRENCH DE-NOISE STRUCTURE AND METHOD FOR FORMING THE SAME - A metal trench de-noise structure includes a trench disposed in a substrate, an insulating layer deposited on the sidewall of the trench, an Inter-Layer Dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the Inter-Layer Dielectric layer to fill up the trench. The metal layer may be grounded or floating. | 03-05-2015 |
20150061084 | SUBSTRATE, METHOD OF FABRICATING THE SAME, AND APPLICATION THE SAME - Provided is a substrate, including a substrate material, two conductive structures, and at least one diode. The two conductive structures extend from a first surface of the substrate material to a second surface of the substrate material via two through holes penetrating through the substrate material. The at least one diode is embedded in the substrate material at a sidewall of one of the through holes. | 03-05-2015 |
20150061085 | PACKAGE INTERCONNECTS - A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate. | 03-05-2015 |
20150069579 | METHOD FOR FORMING AN AIR GAP AROUND A THROUGH-SILICON VIA - Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first cavity with a sacrificial material, forming a second cavity in the substrate, through the sacrificial material, by removing a portion of the sacrificial material and a portion of the substrate below the sacrificial material, filling the second cavity with a conductive material, removing a remaining portion of the sacrificial material to form an air gap between the conductive material and the substrate, and forming a cap over the air gap. | 03-12-2015 |
20150069580 | Alignment Mark and Method of Formation - In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess. | 03-12-2015 |
20150076666 | SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA - A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface. | 03-19-2015 |
20150084165 | STACKED MICROELECTRONIC DICE EMBEDDED IN A MICROELECTRONIC SUBSTRATE - Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material. | 03-26-2015 |
20150084166 | Semiconductor Device Having Plural Memory Chip - A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions. | 03-26-2015 |
20150091139 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure. | 04-02-2015 |
20150097273 | METHOD AND STRUCTURE OF FORMING BACKSIDE THROUGH SILICON VIA CONNECTIONS - A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction. | 04-09-2015 |
20150097274 | THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE - An improved through-silicon via (TSV) is disclosed. A semiconductor substrate has a a back-end-of-line (BEOL) stack formed thereon. The BEOL stack and semiconductor substrate has a TSV cavity formed thereon. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield. | 04-09-2015 |
20150102468 | CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other. | 04-16-2015 |
20150108614 | SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE - A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side. | 04-23-2015 |
20150115412 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a first conductive layer disposed on the second main surface so that the through hole passes through the semiconductor substrate from the first main surface to the second main surface; forming an insulation film to extend from a bottom portion of the through hole to the first main surface through a side surface of the through hole; coating an organic member on the insulation film on the side surface of the through hole and the first main surface; removing an air bubble in the organic member and between the organic member and the insulation film; and forming a first opening portion in the organic member. | 04-30-2015 |
20150130029 | Semiconductor Constructions Having Through-Substrate Interconnects - Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect. | 05-14-2015 |
20150130030 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip. | 05-14-2015 |
20150137323 | METHOD FOR FABRICATING THROUGH SILICON VIA STRUCTURE - A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure. | 05-21-2015 |
20150137324 | STARTUP CIRCUIT AND METHOD FOR AC-DC CONVERTERS - A pattern generator includes and upper chip and one or more lower chips. The upper chip includes an upper substrate and a plurality of conductive plates on the upper substrate. The plurality of conductive plates is arranged as an array. The one or more lower chips include one or more lower substrates and a plurality of driving circuits each on one of the one or more lower substrates and electrically coupled with a corresponding one of the plurality of conductive plates. The upper chip and the one or more lower chips are stacked one over another. | 05-21-2015 |
20150137325 | SEMICONDUCTOR DEVICE HAVING METAL PATTERNS AND PIEZOELECTRIC PATTERNS - Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process. | 05-21-2015 |
20150137326 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer. | 05-21-2015 |
20150137327 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer. | 05-21-2015 |
20150137328 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 05-21-2015 |
20150137329 | COMPONENT HAVING A VIA AND METHOD FOR MANUFACTURING IT - An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer. | 05-21-2015 |
20150303141 | SEMICONDUCTOR DEVICE WITH INTEGRATED HOT PLATE AND RECESSED SUBSTRATE AND METHOD OF PRODUCTION - The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step. | 10-22-2015 |
20150357263 | Through Via Structure - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. | 12-10-2015 |
20150357273 | SEMICONDUCTOR SUBSTRATE, ELETRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate includes a vertical conductor and an insulating layer. The vertical conductor includes a metal/alloy component of a nanocomposite crystal structure and is filled in a vertical hole formed in the semiconductor substrate along its thickness direction. The insulating layer is formed around the vertical conductor in a ring shape and includes nm-sized silica particles and a nanocrystal or nanoamorphous silica filling up a space between the silica particles to provide a nanocomposite structure along with the silica particles. | 12-10-2015 |
20150357313 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers. | 12-10-2015 |
20150364401 | DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION - Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip. | 12-17-2015 |
20150364432 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter. | 12-17-2015 |
20150371893 | BURIED SIGNAL TRANSMISSION LINE - A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit. | 12-24-2015 |
20150371927 | COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip. | 12-24-2015 |
20150380343 | FLIP CHIP MMIC HAVING MOUNTING STIFFENER - A flip-chip mounted semiconductor structure having a flip chip mounting pad and a circuit structure flip-chip mounted to the flip chip mounting pad. The circuit structure includes: a semiconductor die; and a stiffener structure attached to the die, the stiffener structure having a conduit passing through the stiffener structure between a front side of the stiffener structure and a hack side of the stiffener structure, the stiffener and attached die having a degree of rigidity greater than the die alone. | 12-31-2015 |
20160035705 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other. | 02-04-2016 |
20160035850 | Semiconductor Device and Manufacturing Method - A semiconductor device includes a trench extending into a semiconductor body from a first surface. At least one of a ternary carbide and a ternary nitride is in the trench. | 02-04-2016 |
20160049355 | Thinned Processed Wafer Having Devices and Vias and Related Method - A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs. | 02-18-2016 |
20160049371 | INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS - A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow. | 02-18-2016 |
20160049377 | SEMICONDUCTOR DEVICES AND PACKAGE SUBSTRATES HAVING PILLARS AND SEMICONDUCTOR PACKAGES AND PACKAGE STACK STRUCTURES HAVING THE SAME - A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar. | 02-18-2016 |
20160056048 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first layer comprising an organic film above a work layer; forming a second layer comprising an inorganic film above the organic film; forming a third layer above the second layer; and forming an opening pattern into the third layer. The method further includes etching the second layer, the first layer, and the work layer using the third layer as a mask, the etching progressing obliquely through the first layer to form a slope in the first layer. The method still further includes removing the first layer to cause the second layer to be disposed in direct contact with the work layer to thereby form a step portion. | 02-25-2016 |
20160056110 | METHOD OF FORMING A PATTERN - A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern. | 02-25-2016 |
20160071806 | SHIELDING FOR THROUGH-SILICON-VIA NOISE COUPLING - In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring. | 03-10-2016 |
20160079197 | SEMICONDUCTOR DEVICE HAVING A DIE AND THROUGH-SUBSTRATE VIA - Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die. | 03-17-2016 |
20160099196 | Formation of Through Via Before Contact Processing - The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads. | 04-07-2016 |
20160099201 | INTEGRATED CIRCUIT DEVICES HAVING THROUGH-SILICON VIAS AND METHODS OF MANUFACTURING SUCH DEVICES - An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied. | 04-07-2016 |
20160099234 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 04-07-2016 |
20160118326 | METHOD FOR FABRICATING FAN-OUT WAFER LEVEL PACKAGE AND FAN-OUT WAFER LEVEL PACKAGE FABRICATED THEREBY - A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first semiconductor chip and the dummy substrate, removing the dummy substrate to expose the first semiconductor chip, disposing a second semiconductor chip on the exposed first semiconductor chip, forming an insulating layer on the second semiconductor chip, the first semiconductor chip, and the mold substrate, and forming a plurality of redistribution lines that electrically connects the first semiconductor chip and the second semiconductor chip through the insulating layer. | 04-28-2016 |
20160118354 | MICROELECTRONIC PACKAGE UTILIZING MULTIPLE BUMPLESS BUILD-UP STRUCTURES AND THROUGH-SILICON VIAS - A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes. | 04-28-2016 |
20160118356 | Interconnect Structure and Method of Forming Same - An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer. | 04-28-2016 |
20160133517 | Self-Limited, Anisotropic Wet Etching of Transverse Vias in Microfluidic Chips - The present invention is notably directed to a method of fabrication of a microfluidic chip ( | 05-12-2016 |
20160133570 | SEMICONDUCTOR DEVICE, CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE - A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si substrate, wherein a rectangular electrode pad is provided on the other surface with an insulation film laid between the electrode pad and the other surface, an opening of the through hole on the one surface side is circular, an opening of the through hole on the other surface side is rectangular, and the area of the opening on the other surface side is made smaller than the area of the opening on the one surface side. | 05-12-2016 |
20160141226 | DEVICE CONNECTION THROUGH A BURIED OXIDE LAYER IN A SILICON ON INSULATOR WAFER - An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer. Additionally, a dielectric layer is deposited on the buried oxide layer and the at least one semiconductor device. At least one via is created from the at least one semiconductor device through the buried oxide layer. Furthermore at least one through silicon via is formed through the semiconductor substrate electrically connected to the at least one via from the dielectric layer through the buried oxide layer. | 05-19-2016 |
20160141228 | DEVICE CONNECTION THROUGH A BURIED OXIDE LAYER IN A SILICON ON INSULATOR WAFER - An approach to forming a semiconductor structure for a semiconductor device with connections through a buried oxide layer in a silicon on insulator wafer. A buried oxide layer is formed on a semiconductor substrate and at least one semiconductor device is formed on the buried oxide layer. Additionally, a dielectric layer is deposited on the buried oxide layer and the at least one semiconductor device. At least one via is created from the at least one semiconductor device through the buried oxide layer. Furthermore at least one through silicon via is formed through the semiconductor substrate electrically connected to the at least one via from the dielectric layer through the buried oxide layer. | 05-19-2016 |
20160148858 | METHOD OF FORMING THROUGH-HOLE IN SILICON SUBSTRATE, METHOD OF FORMING ELECTRICAL CONNECTION ELEMENT PENETRATING SILICON SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY - The present invention herein relates to a method of forming a through-hole in a silicon substrate. The present invention herein also relates to a method of forming an electrical connection element which penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. More particularly, the present invention herein relates to a method of forming in a silicon substrate a through-hole capable of reducing roughness in a side wall of the through-hole and exhibiting low permittivity, by alternatingly laminating cationic and anionic polymer on the through-hole that has a dent on the side wall to form a porous elastic layer, and also relates to a method of forming an electrical connection that penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. | 05-26-2016 |
20160148888 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor substrate and exposing the conductive pad, and a bump structure. The bump structure may include a first bump structure on the conductive pad and a second bump structure on the passivation layer. The first bump structure may include a base bump layer, a first pillar bump layer, and a first solder bump layer that are sequentially stacked on the conductive pad. The second bump structure may include a second pillar bump layer and a second solder bump layer that are sequentially stacked on the passivation layer. | 05-26-2016 |
20160148913 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal. | 05-26-2016 |
20160181211 | DIE PACKAGE WITH SUPERPOSER SUBSTRATE FOR PASSIVE COMPONENTS | 06-23-2016 |
20160181212 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME | 06-23-2016 |
20160204082 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 07-14-2016 |
20160204083 | Integrated Semiconductor Device And Wafer Level Method Of Fabricating The Same | 07-14-2016 |
20160204085 | SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE | 07-14-2016 |
20160379883 | INTEGRATED CIRCUIT (IC) CHIPS WITH THROUGH SILICON VIAS (TSV) AND METHOD OF FORMING THE IC - A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip. | 12-29-2016 |
20160379934 | WAFER RIGIDITY WITH REINFORCEMENT STRUCTURE - Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias. | 12-29-2016 |
20170236789 | SEMICONDUCTOR DEVICE | 08-17-2017 |
20190148309 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 05-16-2019 |
20220139840 | THROUGH-SILICON VIA (TSV) KEY FOR OVERLAY MEASUREMENT, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING TSV KEY - A through-silicon via (TSV) key for overlay measurement includes: a first TSV extending through at least a portion of a substrate in a first direction that is perpendicular to a top surface of the substrate; and at least one ring pattern, which is apart from and surrounds the first TSV in a second direction that is parallel to the top surface of the substrate, the at least one ring pattern being arranged in a layer that is lower than a top surface of the first TSV in the first direction, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV. | 05-05-2022 |
20220139880 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power. | 05-05-2022 |