Class / Patent application number | Description | Number of patent applications / Date published |
257357000 | In complementary field effect transistor integrated circuit | 26 |
20080197416 | Semiconductor protection circuit, method for fabricating the same and method for operating semiconductor protection circuit - A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS. | 08-21-2008 |
20080224220 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor ( | 09-18-2008 |
20080277728 | Semiconductor structure for protecting an internal integrated circuit and method for manufacturing the same - A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate and enclosing the N-well and the P-well; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; and a first ground and a second ground respectively disposed to positions corresponding to outside and inside of the N+ section. Also, the second doping regions are isolated from the first doping regions. The first and second doping regions located within the N+ section are isolated from the substrate by the N+ section. Furthermore, the second ground is electrically connected to at least one of the second doping regions. | 11-13-2008 |
20080303093 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line. Resistance of a current path extending from the output terminal through the one MOS transistor to the one power supply line has a value such that, when a voltage at which the protection transistor causes snapback is applied between the output terminal and the one power supply line, a current flowing through the current path is lower than a breakdown current of the one MOS transistor. | 12-11-2008 |
20090014801 | DECOUPLING CAPACITOR CIRCUIT AND LAYOUT FOR LEAKAGE CURRENT REDUCTION AND ESD PROTECTION IMPROVEMENT - In order to reduce the leakage current and increase the ESD protection performance, several MOS capacitors are serially connected. The E field between the gate and the source/drain of the MOS transistor is lowered and so is the gate leakage current. Besides, because the ESD voltage is distributed on the gates of the MOS capacitors, the MOS capacitors have good ESD protection performance. | 01-15-2009 |
20090020818 | SEMICONDUCTOR DIODE STRUCTURES - A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential. | 01-22-2009 |
20090057767 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a protected device formed on a semiconductor substrate, a first protection transistor formed in a second well of a second conductivity type, and a second protection transistor formed in a first well of a first conductivity type. A fourth source/drain diffusion layer of the second protection transistor is in contact with a second diffusion layer, and a third source/drain diffusion layer is in contact with a second source/drain diffusion layer of the first protection transistor in the second well. A first source/drain diffusion layer of the first protection transistor is in contact with a first diffusion layer, which is in contact with a protected device electrode. | 03-05-2009 |
20090079003 | Method for protecting circuits from damage due to currents and voltages during manufacture - A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the at-risk devices. During operation of the IC, the protection circuit network is powered down, such that excessive current leakage is avoided. | 03-26-2009 |
20090140340 | ESD protection device structure - An electrostatic discharge (ESD) protective device structure is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, wherein the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage. | 06-04-2009 |
20090152632 | LATCHUP ROBUST ARRAY I/O USING THROUGH WAFER VIA - A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits. | 06-18-2009 |
20090218626 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used. | 09-03-2009 |
20090294856 | I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS - A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps. | 12-03-2009 |
20100038718 | ELECTRO-STATIC DISCHARGE AND LATCHUP RESISTANT SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region, which includes a voltage input terminal. The isolation layer is located between the backgate region and the substrate layer and has a doping type opposite that of the backgate region. The diode includes a first terminal connected to the isolation layer and a second terminal coupled to an isolation voltage source. | 02-18-2010 |
20110073949 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line. Resistance of a current path extending from the output terminal through the one MOS transistor to the one power supply line has a value such that, when a voltage at which the protection transistor causes snapback is applied between the output terminal and the one power supply line, a current flowing through the current path is lower than a breakdown current of the one MOS transistor. | 03-31-2011 |
20110233678 | JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS - An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions. | 09-29-2011 |
20130161750 | N-Channel Laterally Diffused Metal-Oxide-Semiconductor Device - The disclosure relates to an n-channel laterally diffused metal-oxide-semiconductor device comprising an n+ source ( | 06-27-2013 |
20130256801 | INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME - During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW. | 10-03-2013 |
20150340358 | SURROUNDED EMITTER BIPOLAR DEVICE - A surrounded emitter bipolar device includes a substrate having a p-epitaxial (p-epi) layer thereon, and a p-base in the p-epi layer. A two dimensional (2D) grid of p-base contacts (base units) include the p-base, wherein each base unit includes an outer dielectric structure surrounding an inner dielectric isolation ring. The inner dielectric isolation ring surrounds an n region (n+ moat). A first portion of the n+ moats are collector (C) units, and a second portion of the n+ moats are emitter (E) units. The E units are all fully surrounded by C units. | 11-26-2015 |
20160043067 | SEMICONDUCTOR DEVICE - In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p | 02-11-2016 |
257358000 | Including resistor element | 7 |
20100200921 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a field effect transistor that is provided with a gate region, a drain region and a source region and that is formed on a substrate; a circuit region that is formed on the substrate so as to be electrically isolated from the field effect transistor; a first guard ring that is formed in a ring shape encircling the field effect transistor and that includes an internal resistance; and a second guard ring that is formed in a ring shape encircling the circuit region, that forms a capacitance between the second guard ring and the gate region by capacitive coupling with the gate region, and that includes an internal resistance. | 08-12-2010 |
20110073950 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a first MIS transistor including a gate insulating film | 03-31-2011 |
20110133282 | Semiconductor device - A semiconductor device includes a power supply line supplied with a power supply voltage; a power supply node connected with the power supply line; a ground line; a ground pad connected with the ground line; a signal input pad; a main protection circuit section configured to discharge an ESD surge applied to a first pad as one of the power supply node, the signal input pad and the ground pad to a second pad as another thereof; a protection object circuit; a connection node connected with the protection object circuit; a first resistance element connected between the signal input pad and the connection node; and a sub protection circuit section. The sub protection circuit section includes a least one of a first PMOS transistor having a source connected with the connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with the connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line. | 06-09-2011 |
20120181611 | SEMICONDUCTOR DEVICE - The invention provides a semiconductor device including an ESD protection circuit with a high ESD protection characteristic. An RC timer included discharge portion including an RC timer formed by a resistor element and a capacitor element and a PLDMOS transistor is formed so as to turn on only when a surge voltage due to static electricity is applied. Furthermore, a noise prevention portion including first and second NMOS off transistors of which the source electrode and the drain electrode are connected is formed. The source electrode of the PLDMOS transistor of the RC timer included discharge portion is connected to a power supply line. The drain electrode of the PLDMOS transistor and the drain electrode of the first NMOS off transistor are connected. The source electrode of the second NMOS off transistor is connected to a ground line. | 07-19-2012 |
20130001697 | SEMICONDUCTOR DEVICE - A semiconductor device includes a signal input pad, a protection object circuit, a first connection node connected with the protection object circuit, a first resistance element connected between the signal input pad and the first connection node, a first protection circuit section arranged between a power supply line or a ground line and a second connection node between the signal input pad and the first resistance element, and a second protection circuit section. The second protection circuit section includes at least one of a first PMOS transistor having a source connected with the first connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with said first connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line. | 01-03-2013 |
20130200460 | ESD Protection Circuit - An electrostatic discharge (ESD) protection circuit is provided. A first NMOS transistor is coupled to a power line. A second NMOS transistor is coupled between the first transistor and a ground. A detection unit provides a detection signal when an ESD event occurs at the power line. A trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors. | 08-08-2013 |
20140361372 | SEMICONDUCTOR INTEGRATED CIRCUIT - An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET designed so as to withstand ESD. A second protection element includes a second transistor configured as a P-channel MOSFET designed so as to withstand ESD. A capacitance element is connected to a second line, and forms an RC filter together with a filter resistor. The capacitance element includes at least one from among a third transistor having the same device structure as that of the first transistor and a fourth transistor having the same device structure as that of the second transistor. | 12-11-2014 |