Class / Patent application number | Description | Number of patent applications / Date published |
257348000 | Depletion mode field effect transistor | 79 |
20080224216 | STRAINED HOT (HYBRID OREINTATION TECHNOLOGY) MOSFETs - A strained HOT MOSFET. The MOSFET includes (a) a first semiconductor layer having a first crystallographic orientation; (b) a buried oxide layer on top of the first semiconductor layer; (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic orientation, and wherein the second crystallographic orientation is different from the first crystallographic orientation; (d) a third semiconductor layer on top of the first semiconductor layer, wherein the third semiconductor layer has the first crystallographic orientation; and (e) a fourth semiconductor layer on top of the third semiconductor layer, wherein the fourth semiconductor layer includes a different material than that of the third semiconductor layer, and wherein the fourth semiconductor layer has the first crystallographic orientation. | 09-18-2008 |
20080237717 | Fully Depleted SOI Multiple Threshold Voltage Application - An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric. | 10-02-2008 |
20080265325 | BUILDING FULLY-DEPLETED AND PARTIALLY-DEPLETED TRANSISTORS ON SAME CHIP - An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and partially-depleted silicon-on-insulator (PD-SOI) transistors on a semiconductor substrate is disclosed. | 10-30-2008 |
20080290414 | INTEGRATING STRAIN ENGINEERING TO MAXIMIZE SYSTEM-ON-A-CHIP PERFORMANCE - A semiconductor device comprising a first transistor device and second transistor device both on a semiconductor substrate. The first transistor device has a first n-channel and a first p-channel and the second transistor device has a second n-channel and a second p-channel. Each of the p-channels and the n-channels have a long lateral axis that is aligned with a orientation plane of a silicon layer of the semiconductor substrate. The second p-channel and the first and second n-channels include the silicon layer configured as strained silicon. The first p-channel includes the silicon layer configured as relaxed silicon. Each of the n-channels contact gate structures that impart a tensile stress in the n-channels. | 11-27-2008 |
20080308867 | PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION - Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET. | 12-18-2008 |
20090039429 | SOI MOSFET DEVICE WITH REDUCED POLYSILICON LOADING ON ACTIVE AREA - Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors or partial depletion type transistors. | 02-12-2009 |
20090078999 | SEMICONDUCTOR DEVICE STRUCTURES WITH FLOATING BODY CHARGE STORAGE AND METHODS FOR FORMING SUCH SEMICONDUCTOR DEVICE STRUCTURES. - Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths. When electrically biased, the floating charge-neutral region at least partially resides in the wider section of the semiconductor body. | 03-26-2009 |
20090096026 | METHOD OF FABRICATING HIGH VOLTAGE FULLY DEPLETED SOI TRANSISTOR AND STRUCTURE THEREOF - A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI. | 04-16-2009 |
20090250757 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There is provided a semiconductor device having excellent device characteristics and reliability in which V | 10-08-2009 |
20090261415 | FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S) - Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs. | 10-22-2009 |
20090321830 | INTEGRATED CIRCUIT DEVICE, SYSTEM, AND METHOD OF FABRICATION - A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portions that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion. | 12-31-2009 |
20090321831 | PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION - Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET. | 12-31-2009 |
20100090281 | Field Effect Transistor with Metal-Semiconductor Junction - A MOSFET transistor comprising a substrate of semiconductor material having a source junction connected to a source electrode, a drain junction connected to a drain electrode, and a gate layer connected to a gate electrode, the source junction or the drain junction being a metal-semiconductor junction. | 04-15-2010 |
20100133617 | FIN FIELD EFFECT TRANSISTOR - Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si | 06-03-2010 |
20100140708 | Multi-Thickness Semiconductor with Fully Depleted Devices and Photonic Integration - Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region. | 06-10-2010 |
20100155844 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a semiconductor device having excellent device characteristics in which V | 06-24-2010 |
20100213548 | Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof - Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric. | 08-26-2010 |
20100244134 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an insulating layer; a semiconductor layer formed on the insulating layer; a first partially depleted transistor formed in the semiconductor layer; and a first diode formed in the semiconductor layer, wherein the first transistor has a first gate electrode formed above the semiconductor layer via an insulating film and a first source or a first drain of a first conductivity type formed in the semiconductor layer below both sides of the gate electrode, the first diode has a first impurity layer of a second conductivity type formed in a shallow portion of the semiconductor layer and a second impurity layer of the first conductivity type formed in a deep portion of the semiconductor layer, the first impurity layer and the second impurity layer are stacked in a depth direction of the semiconductor layer, and a side surface of the first impurity layer and a side surface of the second impurity layer are in contact with the semiconductor layer in a region just below the first gate electrode. | 09-30-2010 |
20100252884 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an insulating layer; a semiconductor layer formed on the insulating layer; a first partially depleted transistor formed in the semiconductor layer; and a second transistor formed in the semiconductor layer, wherein the first transistor has a first gate electrode formed above the semiconductor layer via an insulating film and a first source or a first drain of a first conductivity type formed in the semiconductor layer below both sides of the first gate electrode, the second transistor has a second gate electrode formed above the semiconductor layer via an insulating film and a second source or a second drain of a second conductivity type formed in the semiconductor layer below both sides of the second gate electrode, and one of the second source and the second drain is electrically connected to the semiconductor layer in a region just below the first gate electrode. | 10-07-2010 |
20100252885 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device ( | 10-07-2010 |
20100264492 | Semiconductor on Insulator Semiconductor Device and Method of Manufacture - A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions ( | 10-21-2010 |
20100327356 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. | 12-30-2010 |
20110037124 | THIN FILM TRANSISTOR - The present disclosure provides a thin film transistor which includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconducting layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by the insulating layer. At least one of the gate electrode, the drain electrode, the source electrode includes a carbon nanotube composite layer. | 02-17-2011 |
20110042745 | SEMICONDUCTOR DEVICE - A disclosed semiconductor device includes an MOS transistor having an N-type low-concentration drain region, a source region, an ohmic drain region, a P-type channel region, an ohmic channel region, a gate isolation film, and a gate electrode. The N-type low-concentration drain region includes two low-concentration drain layers in which the N-type impurity concentration of the upper layer is higher than that of the lower layer; the P-type channel region includes two channel layers in which the P-type impurity concentration of the upper layer is lower than that of the lower layer; and the gate electrode is formed on the P-type channel region and the N-type low-concentration drain region and disposed to be separated from the ohmic drain region when viewed from the top. | 02-24-2011 |
20110042746 | SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME - A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode. | 02-24-2011 |
20110062520 | METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL - A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process. | 03-17-2011 |
20110127609 | SEMICONDUCTOR MEMORY DEVICE - The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line. | 06-02-2011 |
20110147841 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of the channel region, wherein the transistor is a memory element constituting the channel region as a floating body cell. | 06-23-2011 |
20110169087 | MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER - The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells. | 07-14-2011 |
20110180873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention also provides a semiconductor device comprising: a plurality of first gate patterns disposed in a cell area of a substrate region; a plurality of first junction regions disposed in the cell area respectively adjacent to the first gate patterns; buried insulation film buried in the middle area of the substrate region at a bottom region of the cell area; at least one second gate pattern disposed in a peripheral area of the substrate region; and a plurality of second junction regions disposed in the substrate region respectively adjacent to the second gate pattern. | 07-28-2011 |
20110193166 | STRUCTURE AND METHOD FOR REDUCING FLOATING BODY EFFECT OF SOI MOSFETS - The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET. | 08-11-2011 |
20110215407 | SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures. | 09-08-2011 |
20110215408 | FLOATING BODY CELL STRUCTURES, DEVICES INCLUDING SAME, AND METHODS FOR FORMING SAME - Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed. | 09-08-2011 |
20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 01-26-2012 |
20120104497 | HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI - An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel). | 05-03-2012 |
20120139048 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device. | 06-07-2012 |
20120146146 | PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion. | 06-14-2012 |
20120168865 | Transistor and Method for Manufacturing the Same - The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved. | 07-05-2012 |
20120193717 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first device isolation insulating film formed in a semiconductor substrate, a first well having a first conductivity type, defined by the first device isolation insulating film, and shallower than the first device isolation insulating film, a second device isolation insulating film formed in the first well, shallower than the first well, and defining a first part of the first well and a second part of the first well, a gate insulating film formed above the first part, a gate electrode formed above the gate insulating film, and an interconnection electrically connected to the second part of the first well and the gate electrode, wherein an electric resistance of the first well in a first region below the second device isolation insulating film is lower than an electric resistance of the first well in a second region other than the first region on the same depth level. | 08-02-2012 |
20120199908 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 08-09-2012 |
20120205743 | PD SOI DEVICE WITH A BODY CONTACT STRUCTURE - The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology. | 08-16-2012 |
20120228709 | INTEGRATED CIRCUIT STRUCTURE INCORPORATING ONE OR MORE ASYMMETRIC FIELD EFFECT TRANSISTORS AS POWER GATES FOR AN ELECTRONIC CIRCUIT WITH STACKED SYMMETRIC FIELD EFFECT TRANSISTORS - Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin). | 09-13-2012 |
20120228710 | Castellated gate MOSFET tetrode capable of fully-depleted operation - A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions. | 09-13-2012 |
20120235238 | FULLY-DEPLETED SON - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension. | 09-20-2012 |
20120267719 | Method and Apparatus for use in Improving Linearity of MOSFETS using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 10-25-2012 |
20120292703 | SEMICONDUCTOR DEVICE - In view of achieving a cost reduction of an antenna switch, a technique is provided which can reduce harmonic distortion generated in the antenna switch as much as possible in particular even when the antenna switch is comprised of a field effect transistor formed over a silicon substrate. | 11-22-2012 |
20120299105 | ETSOI CMOS with Back Gates - A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage. | 11-29-2012 |
20130009245 | Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof - Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric. | 01-10-2013 |
20130026575 | THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP - Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff. | 01-31-2013 |
20130099317 | Fin-Based Adjustable Resistor - According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel. | 04-25-2013 |
20130200459 | STRAINED CHANNEL FOR DEPLETED CHANNEL SEMICONDUCTOR DEVICES - A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device. | 08-08-2013 |
20130240993 | FULLY-DEPLETED SON - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension. | 09-19-2013 |
20140015052 | ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges - An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well. | 01-16-2014 |
20140021549 | Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle - An exemplary semiconductor memory cell is provided to include: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a buried layer region in electrical contact with the floating body region, below the first and second regions, spaced apart from the first and second regions; and a substrate region configured to inject charge into the floating body region to maintain the state of the memory cell; wherein an amount of charge injected into the floating body region is a function of a charge stored in the floating body region. | 01-23-2014 |
20140021550 | Transistor Structures And Integrated Circuitry Comprising An Array of Transistor Structures - This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed. | 01-23-2014 |
20140027853 | Fluctuation Resistant Low Access Resistance Fully Depleted SOI Transistor with Improved Channel Thickness Control and Reduced Access Resistance - The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional δ-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor. | 01-30-2014 |
20140027854 | Fluctuation Resistant FDSOI Transistor with Implanted Subchannel - The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. | 01-30-2014 |
20140084372 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 03-27-2014 |
20140117450 | PARTIALLY DEPLETED (PD) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion. | 05-01-2014 |
20140151807 | COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE - A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer. | 06-05-2014 |
20140159156 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 06-12-2014 |
20140264605 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 09-18-2014 |
20140291763 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 10-02-2014 |
20140299936 | INTEGRATED CIRCUIT DEVICES AND FABRICATION TECHNIQUES - Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device. | 10-09-2014 |
20140312422 | Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 10-23-2014 |
20150061023 | On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges - The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater. | 03-05-2015 |
20150069513 | SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths. | 03-12-2015 |
20150084130 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing an SOI substrate, onto which a heavily doped buried layer and a surface active layer are formed; forming a gate stack and sidewall spacers on the substrate; forming an opening at one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the SOI substrate; filling the opening to form a plug; forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug. Accordingly, the present invention further provides a semiconductor structure. In the present invention, the heavily doped buried layer is favorable for reducing width of depletion layers at source/drain regions and suppressing short-channel effects. The heavily doped buried layer overlaps with the source region, which thence forms a heavily doped pn junction favorable for suppressing floating body effects of SOI MOS devices, thereby improving performance of semiconductor devices. Besides, no body contact is needed in the present invention, thus device area and manufacturing cost are saved. | 03-26-2015 |
20150145045 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer. | 05-28-2015 |
20150325597 | FINFETS SUITABLE FOR USE IN A HIGH DENSITY SRAM CELL - Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays. | 11-12-2015 |
20150364498 | BACK BIASED TRANSISTOR AND CURRENT SOURCE BIASING - A semiconductor chip device may include a silicon on insulator (SOI) base, a first transistor, and a voltage device. The SOI base may include a semiconductor substrate having a first doped layer and a second doped layer directly on the first doped layer, a buried oxide layer directly on the second doped layer, and a first moat electrically isolating a first bias region of the second doped layer. The first bias region may be electrically coupled to a current source. The first transistor may be formed above the buried oxide layer and the first bias region. The first transistor may include a first drain a first source a first body a first gate and a first back gate. The voltage device may be electrically coupled to the first back gate and the first gate and configured to maintain a voltage difference between the first gate and the first back gate. | 12-17-2015 |
20160064561 | Method and Apparatus for use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 03-03-2016 |
20160079277 | FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS - A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage. | 03-17-2016 |
20160111534 | DUAL GATE FD-SOI TRANSISTOR - Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module. | 04-21-2016 |
20160190203 | SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE - There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed. | 06-30-2016 |
20160380100 | FDSOI VOLTAGE REFERENCE - An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET. | 12-29-2016 |
20160380101 | SUPPRESSION OF BACK-GATE TRANSISTORS IN RF CMOS SWITCHES BUILT ON AN SOI SUBSTRATE - The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer. | 12-29-2016 |
20170236826 | INTEGRATED CIRCUIT DEVICES AND FABRICATION TECHNIQUES | 08-17-2017 |
20190148519 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME | 05-16-2019 |