Entries |
Document | Title | Date |
20080203473 | Lateral Field-Effect Transistor Having an Insulated Trench Gate Electrode - A field-effect transistor having cells ( | 08-28-2008 |
20080211017 | Semiconductor Device - A semiconductor substrate is formed with trenches, and each of the trenches includes: a gate electrode portion in which a gate electrode is arranged; and a gate lead portion which is brought into contact with an interconnect for electrically connecting the gate electrode to the outside. In the gate lead portion for electrically connecting the gate electrode to the outside, an end of each of the trenches has a greater width than a portion of the trench other than the end. | 09-04-2008 |
20080224207 | INSULATED GATE TRANSISTOR - A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate. | 09-18-2008 |
20080246081 | Self-Aligned Trench MOSFET and Method of Manufacture - A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions. | 10-09-2008 |
20080251839 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si | 10-16-2008 |
20080251840 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 10-16-2008 |
20080296673 | Double gate manufactured with locos techniques - This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of the bottom insulation attached to sidewalls of the trench extending above a top surface of the bottom trench-filling segment. | 12-04-2008 |
20080315301 | Trench Gate Power Semiconductor Device - A trench gate power MOSFET ( | 12-25-2008 |
20090008709 | Power Semiconductor Devices with Trenched Shielded Split Gate Transistor and Methods of Manufacture - A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches. Electrical contact to the conductive shield electrode can be made inside the active area. The device can also include a perimeter trench extending at least partially around the active trenches such that at least some of the active trenches are perpendicular to the perimeter trench, gate fingers extending from a perimeter gate poly runner located in said perimeter trench, and shield poly fingers extending from a perimeter shield poly runner located in the perimeter trench. The gate fingers are staggered with respect to the shield poly fingers. | 01-08-2009 |
20090014787 | Multi-Layer Semiconductor Structure and Manufacturing Method Thereof - A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively. | 01-15-2009 |
20090020810 | Method of Forming Power Device Utilizing Chemical Mechanical Planarization - A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench. | 01-22-2009 |
20090065861 | MOS device with low injection diode - A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and into the body, an active region contact electrode disposed within the active region contact trench, wherein a thin layer of body region separating the active region contact electrode from the drain. | 03-12-2009 |
20090085107 | Trench MOSFET with thick bottom oxide tub - A semiconductor power device includes a plurality of trenched gates. The trenched gates include a thin dielectric layer padded sidewalls of the trenched gate and a tub-shaped thick dielectric layer below a bottom of the trenched gates having a width narrower than the trenched gate. In an exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further includes a local deposition of silicon oxide (LOCOS) filling in a tub-shaped trench having a narrower width than the trenched gate. In another exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further comprising a high density plasma (HDP) chemical vapor deposition (CVD) silicon oxide filled in a tub-shaped trench having a narrower width than the trenched gate. | 04-02-2009 |
20090096019 | MOSGATED POWER SEMICONDUCTOR DEVICE WITH SOURCE FIELD ELECTRODE - A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench. | 04-16-2009 |
20090159965 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers. | 06-25-2009 |
20090166734 | TRENCH GATE MOSFET AND METHOD FOR FABRICATING THE SAME - A trench gate MOSFET and a fabrication method thereof includes forming a first epitaxial layer over a semiconductor substrate, and then forming a second epitaxial layer formed over the first epitaxial layer, and then forming a body region over the second conductive type second epitaxial layer, and then forming a circular cross-section in a portion of the body region by performing an ion implantation process on the body region such that a bottom area thereof has a circular cross-section. | 07-02-2009 |
20090179262 | Floating Body Memory Cell with a Non-Overlapping Gate Electrode - An integrated circuit includes a memory cell with a transistor. The transistor includes first and second doped portions, and a third portion disposed between the first and second doped portions. The first and the second doped portions and the third portion are disposed in a semiconductor substrate. The transistor further includes a gate electrode adjacent to the third portion, the gate electrode being insulated from the third portion. The gate electrode does not overlap at least one of the first and second doped portions, and a line connecting the first and the second portions extends substantially perpendicular to a surface of the substrate. | 07-16-2009 |
20090194814 | Semiconductor device and method for manufacturing the same - A semiconductor device includes: a channel region extending substantially perpendicular to a main surface of a semiconductor substrate; a first diffusion layer provided on a bottom of the channel region; a second diffusion layer provided on a top of the channel region; a first gate electrode that extends substantially perpendicular to the main surface of the semiconductor substrate and that is provided on a side of the channel region through a gate insulation film; and a second gate electrode that extends substantially parallel to the main surface of the semiconductor substrate and that is connected to the top of the first gate electrode, wherein a planar position of the second gate electrode is offset relative to a planar position of the first gate electrode. | 08-06-2009 |
20090206400 | SYSTEMS AND DEVICES INCLUDING FIN TRANSISTORS AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin field-effect transistors disposed in rows, a plurality of insulating fins each disposed between the rows, and a plurality of memory elements each coupled to a terminal of a fin field-effect transistor among the plurality of fin field-effect transistors. | 08-20-2009 |
20090212359 | TRENCHED MOSFET WITH TRENCHED SOURCE CONTACT - A trenched MOSFET with trenched source contact, comprising: a semiconductor region, further comprising a silicon substrate, a epitaxial layer corresponding to the drain region of the trenched MOSFET, a base layer corresponding to the body region of the trenched MOSFET, and a source layer corresponding to the source region of the trenched MOSFET; an interlayer oxide film formed on the source layer; a front metal layer formed on a upper surface of the semiconductor region; a back metal layer formed on a lower surface of the semiconductor region; a plurality of trenched gates formed to reach the epitaxial layer through the source layer and the base layer, and is covered by the interlayer oxide film; and a plurality of source contact trenches formed to reach the base layer through the interlayer oxide film and the source layer, and is covered by the front metal layer; wherein the silicon substrate, the epitaxial layer, the base layer, and the source layer are stacked in sequence; and each of the source contact trenches has a lateral contact layer at a sidewall thereof. | 08-27-2009 |
20090218618 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME - A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench. | 09-03-2009 |
20090230466 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a bulb-type trench separated from a surrounding gate and forming a buried bit line in the bulb-type trench, thereby preventing electric short of a word line and the buried bit line. A semiconductor device includes a vertical pillar formed over a semiconductor substrate, a surrounding gate formed outside the vertical pillar, and a buried bit line separated from the surrounding gate. | 09-17-2009 |
20090236658 | ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION - An array of vertical trigate transistors and method of production are disclosed. One embodiment provides an array of selection transistors for selecting one of a plurality of memory cells. A selection transistor is a vertical trigate transistor. | 09-24-2009 |
20090267143 | TRENCHED MOSFET WITH GUARD RING AND CHANNEL STOP - A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate structure filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a guard ring wrapping around the metal layer corresponding to the gate region at the termination; and a channel stop which is a heavier N-type doping region aside the guard ring at the termination; Wherein the contact plugs connecting to the top metal layer are corresponding to the source and the body regions. | 10-29-2009 |
20090315105 | High-voltage vertical transistor structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 12-24-2009 |
20100032752 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the first conductivity type; and control electrodes each provided within a trench through an insulating film, a sidewall of the trench being formed so as to contact each of the third semiconductor region and the fourth semiconductor region. | 02-11-2010 |
20100038711 | TRENCHED MOSFET WITH GUARD RING AND CHANNEL STOP - A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate structure filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a guard ring wrapping around the metal layer corresponding to the gate region at the termination; and a channel stop which is a heavier N-type doping region aside the guard ring at the termination; Wherein the contact plugs connecting to the top metal layer are corresponding to the source and the body regions. | 02-18-2010 |
20100044787 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes the following processes. A first gate trench is formed if a semiconductor substrate region. Then a first insulating film is formed to cover bottom and side surfaces of the first gate trench. Then, the first insulating film is removed to cover the bottom surface. Then, the semiconductor substrate region exposed to the first gate trench is etched by the first insulating film covering the side surfaces as a mask, to form, in the semiconductor substrate region, a second gate trench directly below the first gate trench. The second gate trench is defined by an unetched film portion of the semiconductor substrate region. The unetched film portion extends toward one of the side surfaces of the first gate trench. | 02-25-2010 |
20100072543 | TRENCH MOSFET WITH ETCHING BUFFER LAYER IN TRENCH GATE - The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the source region; and the second gate trench comprises a gate contact hole which is filled with metal to form a gate metal contact plug, and a gate buffer layer which is formed in the gate conductive layer at the bottom of the gate contact hole in the second gate trench to prevent from over etching, causing gate-drain shortage. | 03-25-2010 |
20100072544 | METHOD OF FORMING AN MOS TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar. | 03-25-2010 |
20100078718 | SEMICONDUCTOR DEVICE AND METHODS FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a trench, a buried insulated source electrode arranged in a bottom portion of the trench, a first gate electrode and a second gate electrode arranged in an upper portion of the trench and spaced apart from one another. A surface gate contact extends into the upper portion of the trench and is in physical and electrical contact with the first gate electrode and second gate electrode. | 04-01-2010 |
20100090274 | TRENCH MOSFET WITH SHALLOW TRENCH CONTACT - A trench MOSFET element with shallow trench contact is disclosed. This shallow trench contact structure has some advantages: blocking the P+ underneath trench contact from lateral diffusion to not touch to channel region when a larger trench contact CD is applied; avoiding the trench gate contact etching through poly and gate oxide when trench gate becomes shallow; making lower cost to refill the trench contact using Al alloys with good metal step coverage as the trench contact is shallower. The disclosed trench MOSFET element further includes an n* region around the bottom of gate trenches to reduce Rds. In some embodiment, the disclosed trench MOSFET provides a terrace gate to further reduce Rg and make self-aligned source contact; In some embodiment, the disclosed trench MOSFET comprises a P* area underneath said P+ region for avalanche energy improvement with lighter dose than said P+ region. | 04-15-2010 |
20100096693 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars. | 04-22-2010 |
20100096694 | PLANAR EXTENDED DRAIN TRANSISTOR AND METHOD OF PRODUCING THE SAME - A planar extended drain transistor ( | 04-22-2010 |
20100102385 | Semiconductor Devices Including Transistors Having Recessed Channels - Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein. | 04-29-2010 |
20100123191 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region. | 05-20-2010 |
20100140691 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench. | 06-10-2010 |
20100140692 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING MULTIPLE CHANNEL TRANSISTORS AND SEMICONDUCTOR DEVICES FABRICATED THEREBY - In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region. | 06-10-2010 |
20100155835 | Castellated gate MOSFET tetrode capable of fully-depleted operation - A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascade structure. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming regions. Both the primary and secondary channel-forming regions include pluralities of thin, spaced, vertically-orientated semiconductor channel elements that span longitudinally along the device between the source and drain regions. First and second gate structures are provided in the form of pluralities of spaced, castellated first and second gate elements interposed between the primary and secondary channel elements, respectively, with first and second top gate members interconnecting the first and second gate elements at their upper vertical ends to cover the primary and secondary channel elements. The adjoined primary and secondary channel elements are super-self-aligned from the first and second gate elements to the source and drain regions. Finally, first and second dielectric layers separate the primary and secondary channel elements from their respective gate structures. | 06-24-2010 |
20100176445 | Metal schemes of trench MOSFET for copper bonding - A trench MOSFET with improved metal schemes is disclosed. The improved contact structure applies a buffer layer to minimize the bonding damage to semiconductor when bonding copper wire upon front source and gate metal without additional cost. | 07-15-2010 |
20100237409 | SEMICONDUCTOR COMPONENT - A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material. | 09-23-2010 |
20100301409 | VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF - Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. | 12-02-2010 |
20100308402 | 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described. | 12-09-2010 |
20110024832 | Semiconductor apparatus and manufacturing method thereof - A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions. | 02-03-2011 |
20110037120 | Shielded gate trench MOSFET device and fabrication - A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 02-17-2011 |
20110057258 | DUAL STRESS DEVICE AND METHOD - A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. | 03-10-2011 |
20110062513 | OVERLAPPING TRENCH GATE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer. | 03-17-2011 |
20110068393 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate electrode includes material having a second work function, wherein the second work function is higher than that of the spacers. | 03-24-2011 |
20110079843 | POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH Embedded Dielectric Layers Containing Permanent Charges - Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region. | 04-07-2011 |
20110084334 | BILATERAL CONDUCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A bilateral conduction semiconductor device and a manufacturing method thereof are provided. The bilateral conduction semiconductor device includes an epitaxial layer having a first conductive type and a first trench, a first gate conductive layer disposed on a sidewall of the first trench, a second gate conductive layer disposed opposite to the first gate conductive layer, and a doped region having the first conductive type. The doped region is disposed in the epitaxial layer between the first gate conductive layer and the second gate conductive layer, and a doped concentration of the doped region is larger than a doped concentration of the epitaxial layer. | 04-14-2011 |
20110089488 | Power Device with Improved Edge Termination - A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. | 04-21-2011 |
20110095359 | Field Boosted Metal-Oxide-Semiconductor Field Effect Transistor - A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions. | 04-28-2011 |
20110108912 | METHODS FOR FABRICATING TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS - A method for fabricating a cellular trench metal oxide semiconductor field effect transistor (MOSFET) includes depositing a first photoresist atop a first epitaxial (epi) layer to pattern a trench area, depositing a second photoresist atop a first gate conductor layer to pattern a mesa area, etching away part of the first gate conductor layer in the mesa area to form a second gate conductor layer with a hump, and titanizing crystally the second gate conductor layer to form a Ti-gate conductor layer. Edges of the mesa area are aligned to edges of the trench area. Hence, approximately more than half of polysilicon in the second gate conductor layer is titanized crystally. A spacer can be formed to protect corners of the first gate conductor layer and to make the gate conductor structure more robust for mechanical support. | 05-12-2011 |
20110121385 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION - Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure. | 05-26-2011 |
20110127602 | Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation - A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor. | 06-02-2011 |
20110127603 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region. | 06-02-2011 |
20110133270 | MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS - A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell. | 06-09-2011 |
20110156139 | Super-Junction trench mosfet with resurf step oxide and the method to make the same - A super-junction trench MOSFET with Resurf Stepped Oxide is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . . Furthermore, the fabrication method can be implemented more reliably with lower cost. | 06-30-2011 |
20110186924 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is directed to reduce a leakage current generated by parasitic field effects and increase or improve operational reliability by forming an insulating layer inside a word line. An embodiment of the present invention provides a semiconductor device comprising a gate pattern over an active region and a device isolation structure, wherein the gate pattern comprises a first gate pattern over the active region and a second gate pattern over the device isolation structure, the first and the second gate patterns having a different structure. | 08-04-2011 |
20110193159 | SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a silicon pillar formed substantially perpendicular to a principal surface of a silicon substrate, a first impurity diffusion layer and a second impurity diffusion layer arranged below and above the silicon pillar, respectively, a gate electrode arranged to penetrate through the silicon pillar in a horizontal direction, a gate dielectric film arranged between the gate electrode and the silicon pillar, a back-gate electrode arranged adjacent to the silicon pillar, and a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar. | 08-11-2011 |
20110198689 | SEMICONDUCTOR DEVICES CONTAINING TRENCH MOSFETS WITH SUPERJUNCTIONS - Semiconductor devices combining a MOSFET architecture with a PN super-junction structure and methods for making such devices are described. The MOSFET architecture can be made using a trench configuration containing a gate that is sandwiched between thick dielectric layers in the top and the bottom of the trench. The PN junction of the super-junction structure is formed between n-type dopant regions in the sidewalls of the trench and a p-type epitaxial layer. The gate of the trench MOSFET is separated from the super-junction structure using a gate insulating layer. Such semiconductor devices can have a lower capacitance and a higher breakdown voltage relative to shield-based trench MOSFET devices and can replace such devices in medium to high voltage ranges. Other embodiments are described. | 08-18-2011 |
20110204438 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a first insulating film; a second insulating film; a first gate electrode; a second gate electrode; and a first semiconductor region. The semiconductor substrate has first and second grooves crossing each other in plan view. The first insulating film covers an inner surface of the first groove. The second insulating film covers an inner surface of the second groove. The first gate electrode fills at least a bottom portion of the first groove. The second gate electrode fills at least a bottom portion of the second groove. The first semiconductor region is positioned in the semiconductor substrate. The first semiconductor region contains a first impurity. The first semiconductor region is adjacent to a first portion of the second insulating film. The first portion of the second insulating film covers at least a bottom region of the second groove. | 08-25-2011 |
20110204439 | SEMICONDUCTOR DEVICE - Embodiments provide a semiconductor device including an N-type semiconductor layer | 08-25-2011 |
20110210391 | SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor device includes a drift region including a semiconductor of a first conductivity type; a first semiconductor region of a second conductivity type provided adjacently to the drift region; a main electrode, a plurality of first gate electrodes and a second gate electrode. The main electrode is provided adjacently to the first semiconductor region and electrically connected to the first semiconductor region, the first semiconductor region being disposed between the drift region and the main electrode. The first gate electrodes are provided along a boundary between the drift region and the first semiconductor region. The first gate electrode has a trench structure and faces the drift region and the first semiconductor region via a first gate insulating film. The second gate electrode of the trench structure is provided along the boundary between the drift region and the first semiconductor region. The second gate electrode is disposed between the two first gate electrodes and faces the drift region and the first semiconductor region via a second gate insulating film. A first portion facing the first semiconductor region in the second gate electrode is shorter than a second portion facing the first semiconductor region in the first gate electrode in a direction from the boundary to the main electrode. The main electrode is extended to a position close to the second gate electrode in the trench provided in the direction from the main electrode to the second gate electrode between the two first gate electrodes. The main electrode is in contact with the first semiconductor region exposed to an inner wall surface of the trench between an end of the first gate electrode on the main electrode side and an end of the second gate electrode on the main electrode side. | 09-01-2011 |
20110215399 | P-CHANNEL POWER MOSFET - In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p | 09-08-2011 |
20110233663 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A body contact layer | 09-29-2011 |
20110233664 | Semiconductor device and a method of manufacturing the same - A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p | 09-29-2011 |
20110248339 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device. | 10-13-2011 |
20110260242 | TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a transistor of a semiconductor device and a method for manufacturing the same. A gate induced drain leakage (GIDL) current is reduced by decreasing a work function at an upper portion of a gate electrode, and a threshold voltage of the transistor is maintained by maintaining a work function at a lower portion of the gate electrode at a high level, thereby reducing a leakage current of the transistor and reducing a read time and a write time of the semiconductor device. The transistor of the semiconductor device includes: a recess with a predetermined depth in a semiconductor substrate; a first gate electrode disposed within the recess; and a second gate electrode disposed on the first gate electrode into which ions of one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) are doped. | 10-27-2011 |
20110284953 | POWER TRENCH MOSFET RECTIFIER - A trench MOSFET rectifier includes oxide layers having different thicknesses formed in different regions of the devices. The rectifying device also includes a source region of first conductivity type at a surface of each mesa region and a body region of a second conductivity type beneath each source region. The rectifying device also includes a dielectric layer lining the bottom and sidewall surfaces of the trenches, the portion of the dielectric layer on the bottom surface being thicker than the portion on the sidewall surface. A doped region underlies each of the first plurality of trenches. A polycrystalline silicon region filling each of the first plurality of trenches to form a gate region in each trench. A conductive material fills a plurality of contact trenches and forms ohmic contacts with the source region, body region, and gate region. | 11-24-2011 |
20110284954 | LOW Qgd TRENCH MOSFET INTEGRATED WITH SCHOTTKY RECTIFIER - An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions. | 11-24-2011 |
20110298045 | SELF-ALIGNED CONTACT FOR TRENCH MOSFET - The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased. | 12-08-2011 |
20110298046 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines. | 12-08-2011 |
20120001259 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess. | 01-05-2012 |
20120025304 | Trench Semiconductor Device and Method of Manufacturing - A semiconductor device includes a semiconductor body including a trench with first and second opposing sidewalls. A first electrode is arranged in a lower portion of the trench and a second electrode in an upper portion of the trench. A dielectric structure is arranged in the trench, including a first portion between the electrodes. The first portion includes, in sequence along a lateral direction from the first sidewall to the second sidewall, a first part including a first dielectric material, a second part including a second dielectric material selectively etchable to the first dielectric material, a third part including the first dielectric material, the first dielectric material of the third part being continuously arranged along a vertical direction from a top side of the first electrode to a bottom side of the second electrode, a fourth part including the second dielectric material and a fifth part including the first dielectric material. | 02-02-2012 |
20120043605 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a trench formed in the device isolation film and the active region, a gate electrode formed at the bottom of the trench, and a high dielectric material layer formed not only over the top of the gate electrode but also over a surface of the trench. As a result, although the gate electrode does not overlap with the junction region, the semiconductor device prevents channel resistance from being increased, resulting in an increase in semiconductor device characteristics. | 02-23-2012 |
20120061753 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches. | 03-15-2012 |
20120061754 | SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND SPLIT GATE ELECTRODES - A super-junction trench MOSFET with Resurf Stepped Oxide and split gate electrodes is disclosed. The inventive structure can apply additional freedom for better optimization of device performance and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. Furthermore, the fabrication method can be implemented more reliably with lower cost. | 03-15-2012 |
20120068261 | Replacement Metal Gate Structures for Effective Work Function Control - A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures. | 03-22-2012 |
20120080748 | TRENCH MOSFET WITH SUPER PINCH-OFF REGIONS - A trench MOSFET with short channel length and super pinch-off regions is disclosed, wherein the super pinch-off regions are implemented by forming at least two type pinch-off regions for punch-through prevention: a first type pinch-off region with a wide mesa width generated between lower portion of two adjacent trenched gates and below an anti-punch through region surrounding bottom of a trenched source-body contact filled with metal plug; a second type pinch-off region with a narrow mesa width generated below a body region and between upper portion of one trenched gate and the anti-punch-through region along sidewall of the trenched source-body contact. | 04-05-2012 |
20120098060 | SEMICONDUCTOR DEVICE - A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode. | 04-26-2012 |
20120119290 | SEMICONDUCTOR DEVICE INCLUDING PROTRUSION TYPE ISOLATION LAYER - A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion. | 05-17-2012 |
20120126317 | ACCUFET WITH INTEGRATED CLAMPING CIRCUIT - The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates. | 05-24-2012 |
20120146136 | VERTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical semiconductor device includes a first pillar and a second pillar, a first bit line contact formed at a lower portion of a first sidewall of the first pillar, a second bit line contact formed at a lower portion of a second sidewall of the second pillar which face the first sidewall of the first pillar, a bit line commonly connected to the first bit line contact and the second bit line contact, and a gate formed at both sides of the first pillar and the second pillar to be crossed with the bit line. | 06-14-2012 |
20120153383 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other. | 06-21-2012 |
20120153384 | Semiconductor Power Device Having A Top-side Drain Using A Sinker Trench - A semiconductor package device houses a die which comprises a power device, and the die further includes a silicon region over a substrate, a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the sinker trench extending from a top surface of the die through the silicon region, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the sinker trench. | 06-21-2012 |
20120161228 | VERTICAL TRANSISTOR STRUCTURE - A vertical transistor structure includes a substrate, a source, a first gate, a first insulating layer, a second gate, a gate insulating layer, a drain, a second insulating layer, and a semiconductor channel layer. The source is configured on the substrate. The first gate is configured on the source and has at least one first through hole. The first insulating layer is between the first gate and the source. The second gate is configured on the first gate and has at least one second through hole. The gate insulating layer is between the first and second gates and has at least one third through hole. The first, second, and third through holes are communicated with one another. The drain is configured on the second gate. The second insulating layer is configured between the second gate and the drain. The semiconductor channel layer fills the first, second, and third through holes. | 06-28-2012 |
20120161229 | DRAM CELL UTILIZING A DOUBLY GATED VERTICAL CHANNEL - A double-gate vertical channel transistor (DGVC) structure is described which is particularly well suited for Dynamic RAM (DRAM) memory (e.g., capacitorless DRAM) wherein the memory cell occupies a small cell area of 4F | 06-28-2012 |
20120187477 | SUPER-JUNCTION TRENCH MOSFET WITH MULTIPLE TRENCHED SOURCE-BODY CONTACTS - A super-junction trench MOSFET with split gate electrodes is disclosed for high voltage device by applying multiple trenched source-body contacts with narrow CDs in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement | 07-26-2012 |
20120187478 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring. | 07-26-2012 |
20120199902 | TRENCH MOS BARRIER SCHOTTKY (TMBS) HAVING MULTIPLE FLOATING GATES - A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate. | 08-09-2012 |
20120205737 | SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode. | 08-16-2012 |
20120235230 | MOSFET DEVICE WITH THICK TRENCH BOTTOM OXIDE - In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench. | 09-20-2012 |
20120235231 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. A second area is disposed between first and third areas. An epitaxial layer is on a substrate. A body layer is in the epitaxial layer in first and second areas. First and second gates are in the body layer and in a portion of the epitaxial layer. The first gate is in the substrate and partially in first and second areas. The second gate is in the substrate and partially in second and third areas. A first contact plug is in a portion of the body layer in the first area. A second contact plug is at least in the epitaxial layer in the third area and contacts the epitaxial layer and the second gate. The first contact plug is electrically connected to the second contact plug. A first doped region is in the body layer between the first contact plug and the first gate. | 09-20-2012 |
20120241852 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, plural stacked bodies, an insulating side wall, an interlayer insulating layer, and a contact. Plural stacked bodies are provided on the semiconductor substrate so as to extend in parallel to one another. Each of the plural stacked bodies includes a gate insulating layer, a gate electrode, and an insulating layer. The insulating side wall covers a side face of the gate electrode in an upper end part thereof and does not cover the side face of the gate electrode in a part thereof contacting the gate insulating layer. The interlayer insulating layer is provided on the semiconductor substrate and covers the stacked bodies. The contact is provided in the interlayer insulating layer between the stacked bodies and is connected to the semiconductor substrate. | 09-27-2012 |
20120241853 | SEMICONDUCTOR DEVICE - A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position. | 09-27-2012 |
20120241854 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film. | 09-27-2012 |
20120241855 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n | 09-27-2012 |
20120241856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n | 09-27-2012 |
20120241857 | DUAL STRESS DEVICE AND METHOD - A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. | 09-27-2012 |
20120267711 | MULTI-LEVEL OPTIONS FOR POWER MOSFETS - This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor. | 10-25-2012 |
20120267712 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region on a semiconductor substrate. The active region is defined by a device isolation layer and includes gate-recesses. The semiconductor device further includes gate electrodes in the gate-recesses, a contact recess in the active region between the gate-recesses, a cell pad that covers at least a portion of the active region between the gate-recesses and that fills at least a portion of the contact recess, and a bit line electrically connected to the cell pad. | 10-25-2012 |
20120280314 | Gate Pullback at Ends of High-Voltage Vertical Transistor Structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 11-08-2012 |
20120286357 | SENSE-AMP TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed. | 11-15-2012 |
20120292694 | HIGH SWITCHING TRENCH MOSFET - A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost. | 11-22-2012 |
20120299090 | Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods - A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed. | 11-29-2012 |
20120306008 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device. | 12-06-2012 |
20120319197 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 12-20-2012 |
20120326229 | Trench Transistor and Manufacturing Method of the Trench Transistor - A semiconductor device includes a semiconductor body including a first surface and a second surface. The semiconductor device further includes a trench structure extending into the semiconductor body from the first surface. The trench structure includes a first gate electrode part and a first gate dielectric part in a first part of the trench structure, and a second gate electrode part and a second gate dielectric part in a second part of the trench structure. A width of the trench structure in the first part is equal to the width of the trench structure in the second part. The semiconductor device further includes a body region adjoining the first and second gate dielectric parts at a side wall of the trench structure. A distance d | 12-27-2012 |
20130001682 | SEMICONDUCTOR STRUCTURES INCLUDING BODIES OF SEMICONDUCTOR MATERIAL, DEVICES INCLUDING SUCH STRUCTURES AND RELATED METHODS - Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material. | 01-03-2013 |
20130009241 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drain layer, a drift, a base, a source region, a plurality of gates provided on the drift region, the base, and the source region, and arranged in a manner spaced apart from each other, a first interlayer insulating film arranged between the plurality of gates on the source region, a gate interconnection film provided on the first interlayer insulating film and the gate, a second interlayer insulating film provided on the gate interconnection film, an inetconnection film provided on the second interlayer insulating film and connected in common to the source region, the interconnection film filling the contact hole provided between each of the gates in the second interlayer insulating film, the gate interconnection film and the first interlayer insulating film and an insulating film arranged between the gate interconnection film and the interconnection film in the contact hole. | 01-10-2013 |
20130009242 | MOS DEVICE WITH LOW INJECTION DIODE - A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction. | 01-10-2013 |
20130026561 | Vertical Transistor with Improved Robustness - A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface. | 01-31-2013 |
20130037882 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench. | 02-14-2013 |
20130069151 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a substrate; a first conductive portion extending in a first direction perpendicular to a major surface of the substrate; a second conductive portion extending in the first direction; a semiconductor portion provided between the first and the second conductive portions and including a first semiconductor region; a first electrode portion extending in the first direction between the first and the second conductive portions; a second electrode portion extending in the first direction between the first and the second conductive portions; a first insulting portion provided between the first electrode portion and the semiconductor portion and having a first thickness; and a second insulating portion provided between the second electrode portion and the semiconductor portion and having a second thickness greater than the first thickness. | 03-21-2013 |
20130082324 | LATERAL STACK-TYPE SUPER JUNCTION POWER SEMICONDUCTOR DEVICE - A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure. | 04-04-2013 |
20130105890 | VERTICAL NON-DYNAMIC RAM STRUCTURE | 05-02-2013 |
20130119462 | SEMICONDUCTOR DEVICE FOR INCREASING BIT LINE CONTACT AREA, AND MODULE AND SYSTEM INCLUDING THE SAME - A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented from occurring in a bit line contact. | 05-16-2013 |
20130119463 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate. | 05-16-2013 |
20130168764 | TRENCH SEMICONDUCTOR POWER DEVICE HAVING ACTIVE CELLS UNDER GATE METAL PAD - A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction. | 07-04-2013 |
20130193510 | SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING - A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension. | 08-01-2013 |
20130200451 | NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT - A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region. | 08-08-2013 |
20130234243 | Checkerboarded High-Voltage Vertical Transistor Layout - In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 09-12-2013 |
20130240987 | SEMICONDUCTOR FIELD EFFECT POWER SWITCHING DEVICE - A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first trench portion and a second trench portion and extending from the first surface into the semiconductor body is provided. The semiconductor body further includes a pn-junction formed between a first semiconductor region and a second semiconductor region. The first trench portion includes an insulated gate electrode which is connected to the source metallization, and the second trench portion includes a conductive plug which is connected to the source metallization and to the second semiconductor region. | 09-19-2013 |
20130248992 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN HAVING A CONTACT WITHIN A SCHOTTKY REGION AND A PROCESS OF FORMING THE SAME - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate, wherein the patterned semiconductor layer defines first and second trenches. The electronic device can also include a first conductive structure within the first trench, a gate electrode within the first trench and overlying the first conductive structure, a first insulating member within the second trench, and a second conductive structure within the second trench. The second conductive structure can include a first portion and a second portion overlying the first portion, the first insulating member can be disposed between the patterned semiconductor layer and the first portion of the second conductive structure; and the second portion of the second conductive structure can contact the patterned semiconductor layer at a Schottky region. Processes of forming the electronic device can take advantage of integrating formation of the Schottky region into a contact process flow. | 09-26-2013 |
20130256789 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions. | 10-03-2013 |
20130256790 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes buried gates formed in a semiconductor substrate in which active regions and an isolation layer are defined. A bit line is coupled to an active region between the buried gates and disposed to cross the buried gates. In the 6F | 10-03-2013 |
20130256791 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view. | 10-03-2013 |
20130264637 | SEMICONDUCTOR DEVICE - Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer. | 10-10-2013 |
20130270631 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer. | 10-17-2013 |
20130270632 | SEMICONDUCTOR DEVICE HAVING A FLOATING SEMICONDUCTOR ZONE - A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region. | 10-17-2013 |
20130307065 | SEMICONDUCTOR DEVICE - The substrate is made of a compound semiconductor and has a plurality of first recesses, each of which opens at one main surface thereof and has a first side wall surface. The gate insulating film is disposed on and in contact with the first side wall surface. The gate electrode is disposed on and in contact with the gate insulating film. The substrate include: a source region having first conductivity type and disposed to face itself with a first recess interposed therebetween, when viewed in a cross section along the thickness direction; and a body region having second conductivity type and disposed to face itself with the first recess interposed therebetween. Portions of the source region facing each other are connected to each other in a region interposed between the first recess and another first recess adjacent to the first recess, when viewed in a plan view. | 11-21-2013 |
20130307066 | TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION - A semiconductor power device with trenched floating gates having thick bottom oxide as termination is disclosed. The gate charge is reduced by forming a HDP oxide layer padded by a thermal oxide layer on trench bottom and a top surface of mesa areas between adjacent trenched gates. Therefore, only three masks are needed to achieve the device structure. | 11-21-2013 |
20130320441 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics. | 12-05-2013 |
20130334596 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a substrate comprising a trench; a first electrode disposed below the trench; a second electrode disposed above the trench, a first insulating layer being disposed between the first electrode and the second electrode; a first contact arranged in a first direction of the substrate and connected to the first electrode; and a second contact arranged in second direction that is different from the first direction, the second contact being connected to the second electrode. | 12-19-2013 |
20140015043 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes active regions defined by a device isolation layer, gates disposed in the active regions of cell channel regions, word lines disposed on the gates and extending along a first direction, and gate contacts configured to connect the gates to the word lines. The gates have a box shape which extends over two active regions. | 01-16-2014 |
20140015044 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region. | 01-16-2014 |
20140021538 | Replacement Gate Fin First Wire Last Gate All Around Devices - In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided. | 01-23-2014 |
20140027844 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first buried gate structure in a peripheral circuit area of a semiconductor substrate, and a second gate structure formed on the semiconductor substrate. A gate insulating layer of a program transistor is thinly formed to be easily ruptured, and a gate insulating layer of a select transistor is thickly formed to improve reliability of the select transistor. | 01-30-2014 |
20140027845 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor section, a control electrode, and a first electrode. The semiconductor section extends in a first direction. The control electrode is provided across a first insulating film from the semiconductor section in a second direction. The semiconductor section includes first, second, third, and fourth semiconductor regions. The first semiconductor region has a first conductivity type. The second semiconductor region has a second conductivity type, and is provided on the first semiconductor region to oppose the control electrode. The third semiconductor region has the first conductivity type, and is provided on the second semiconductor region. The fourth semiconductor region has the second conductivity type, and is provided together with the third semiconductor region. The first electrode is provided on the semiconductor section. The fourth semiconductor region is provided displaced to opposite side of the semiconductor section from the control electrode. | 01-30-2014 |
20140042533 | Segmented Pillar Layout for a High-Voltage Vertical Transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 02-13-2014 |
20140048872 | AVALANCHE CAPABILITY IMPROVEMENT IN POWER SEMICONDUCTOR DEVICES USING THREE MASKS PROCESS - A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved. | 02-20-2014 |
20140048873 | SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively. | 02-20-2014 |
20140054689 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate with a cell region, a second pad region, and a first pad region between the second pad region and the cell region, a first buried gate buried in a trench of the semiconductor substrate, and extended from the cell region to the second pad region, and a second buried gate buried in the trench of the semiconductor substrate, disposed over and spaced apart from an upper part of the first buried gate, and extended from the cell region to the first pad region. | 02-27-2014 |
20140054690 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a fabricating method thereof are provided, in which the semiconductor device includes a semiconductor substrate with a trench formed therein, a bottom electrode placed at a lower inner portion of the trench, the bottom electrode having an uneven upper surface, an insulating layer formed on an upper portion of the bottom electrode and on a sidewall of the trench, and a top electrode placed at an upper portion of the bottom electrode inside the trench, the top electrode having a top electrode which is uneven, in which the top electrode is so configured that the top electrode is inclined toward a center portion. | 02-27-2014 |
20140054691 | FIELD EFFECT TRANSISTOR WITH GATED AND NON-GATED TRENCHES - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 02-27-2014 |
20140061781 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method for manufacturing the same are capable of improving GIDL in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode. | 03-06-2014 |
20140061782 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to example embodiments, a semiconductor device may include a substrate having an upper surface defining a groove and an active region, a device isolation layer in the groove, and a contact structure on the active region. The device isolation exposes the active region and may have a top surface that is higher than a top surface of the active region. The contact structure may include a first portion filling a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, the contact structure may include and a second portion on the device isolation layer so the second portion overlaps with the device isolation layer in a plan view. | 03-06-2014 |
20140117441 | POWER DEVICE STRUCTURES AND METHODS - Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling. | 05-01-2014 |
20140131793 | RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure. | 05-15-2014 |
20140159149 | SHORT CHANNEL TRENCH MOSFETS - A trench MOSFET with a short channel length is disclosed for reducing channel resistance, wherein at least one field relief region is formed underneath the body region in an epitaxial layer between every two adjacent gate trenches and self-aligned with a trenched source-body contact for prevention of drain/source punch-through issue. | 06-12-2014 |
20140183626 | DEVICES WITH CAVITY-DEFINED GATES AND METHODS OF MAKING THE SAME - Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity. | 07-03-2014 |
20140203357 | Semiconductor Device and Method of Manufacturing the Same - According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched. A top surface of the etched portion of the substrate between the grooves is higher than a bottom surface of the groove. A conductive layer is formed to fill the grooves. The conductive layer is etched to form conductive patterns in the grooves, respectively. | 07-24-2014 |
20140217498 | RECESSED ACCESS DEVICES AND GATE ELECTRODES - Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode. | 08-07-2014 |
20140252466 | Electronic Device Including a Conductive Electrode and a Process of Forming the Same - An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer. | 09-11-2014 |
20140264572 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASK LAYERS - A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures. | 09-18-2014 |
20140264573 | METHOD FOR FORMING ACCUMULATION-MODE FIELD EFFECT TRANSISTOR WITH IMPROVED CURRENT CAPABILITY - An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region including a channel region adjacent to but insulated from each of the plurality of gates. | 09-18-2014 |
20140284711 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a drain region of a first-conductivity type, a drain electrode electrically coupled to the drain region, and a semiconductor layer of the first-conductivity type formed onto the drain region and having a first impurity concentration. The semiconductor apparatus further includes: a source region of the first-conductivity type formed on the semiconductor layer and having a second impurity concentration; a first source electrode electrically coupled to the source region; and a gate electrode formed via an insulating layer. The one end of the gate electrode is in a depth of the source region, and the other end is in a depth of the semiconductor layer or the drain region. A second source electrode is provided in the semiconductor layer under the gate electrodes via an insulating layer. A second spacing between the second source electrodes is larger than a first spacing between the gate electrodes. | 09-25-2014 |
20140291758 | SEMICONDUCTOR DEVICE HAVING PLANAR SOURCE ELECTRODE - A semiconductor device includes a channel layer on a substrate; cell trench patterns in the channel layer; and a source pattern on the cell trench patterns. The source pattern includes: grooves, each having inclined sidewalls and bottom that extends in a horizontal direction in a portion of the channel layer between the cell trench patterns, source regions at the inclined sidewalls of the grooves, source isolation regions at the bottoms of the grooves, and a source electrode at interior regions of the grooves and that has a planar upper surface. | 10-02-2014 |
20140319605 | NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT - A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region. | 10-30-2014 |
20140353745 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL - A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented. | 12-04-2014 |
20140353746 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer, a source region and a drain region formed in a surface of the semiconductor layer, both having a first conductivity type, a plurality of gate trenches each formed so as to extend across the source region and the drain region, in a plan view observed in a direction of a normal to the surface of the semiconductor layer, a channel region of a first conductivity type made of the semiconductor layer sandwiched by the gate trenches adjacent to each other, having a channel length along a direction extending from the drain region to the source region, and a gate electrode buried in the gate trench via a gate insulating film, and the channel region has a thickness in the plan view not more than two times a width of a depletion layer to be generated due to a built-in potential between the channel region and the gate electrode. | 12-04-2014 |
20150008516 | SEMICONDUCTOR DEVICE WITH BURIED GATE ELECTRODE STRUCTURES - A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner. | 01-08-2015 |
20150014766 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 01-15-2015 |
20150028415 | SEMICONDUCTOR COMPONENT HAVING A TRANSITION REGION - A semiconductor component is disclosed. One embodiment provides a semiconductor component including a semiconductor body having a cell array region with trenches and an edge region with pn junction. A transition region with at least one trench is formed between the cell array region and the edge region. | 01-29-2015 |
20150028416 | SEMICONDUCTOR COMPONENT WITH DYNAMIC BEHAVIOR - One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches. | 01-29-2015 |
20150041889 | MULTI-GATE VDMOS TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate. | 02-12-2015 |
20150048445 | Semiconductor Chip with Integrated Series Resistances - A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region. | 02-19-2015 |
20150048446 | REDUCTION OF OXIDE RECESSES FOR GATE HEIGHT CONTROL - An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height. | 02-19-2015 |
20150054068 | SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD - In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor. | 02-26-2015 |
20150061001 | SEMICONDUCTOR DEVICE - A semiconductor device which includes a microfabricated transistor with buried gate electrodes. In the semiconductor device, a gate electrode is formed over a substrate, extending in the direction parallel to the first side of a device formation region. The gate electrode lies across the device formation region. A plurality of buried gate electrodes are buried in the device formation region of the substrate and in a plan view, the gate electrode partially overlap them. The buried gate electrodes extend obliquely to the first side of the device formation region and are parallel to each other. In each buried gate electrode, the first end opposite to the first side and the second end opposite to the second end of the device formation region are both parallel to the first side. | 03-05-2015 |
20150061002 | TRENCH MOSFET AND METHOD FOR FABRICATING THE SAME - The present disclosure relates to a trench MOSFET and a method for fabricating the same. The method comprises: providing a substrate with an epitaxy layer; forming a trench in the epitaxy layer; forming a first insulating layer, a first gate, a second insulating layer, and a second gate successively in the trench by deposition and etching; forming a well and a source region at both sides of the trench by ion implantation, and forming a trench-type contact and a metal plug. By forming the first gate and the second gate which are separated from each other, the first insulating layer between a lower portion of the first gate and the epitaxy layer has a thickness larger than that of the second insulating layer between the second gate and the well and the source region. The two separate gates are connected with each other by the metal plug. The resultant MOSFET has an increased breakdown voltage and stable performance while its manufacturer cost is lowered because the manufacturer process is simplified. | 03-05-2015 |
20150069504 | SEMICONDUCTOR DEVICE - This device includes a first semiconductor layer of the first conduction-type. A second semiconductor layer of the first conduction-type is provided above the first semiconductor layer. Gate electrodes respectively have one end located at the second semiconductor layer and other end located at the first semiconductor layer. The gate electrodes extend at a first direction. Gate dielectric films are provided between the first semiconductor layer and the gate electrodes. A plurality of first insulating films are provided between the second semiconductor layer and the gate electrodes and are thicker than the gate dielectric films. A first electrode is provided at a shallower position than the other end between adjacent ones of the gate electrodes and contacts the first and the second semiconductor layer and the first insulating films. A second electrode is provided at an opposite side of the first layer against to the second semiconductor layer. | 03-12-2015 |
20150097232 | DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH - A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench. | 04-09-2015 |
20150102403 | SEMICONDUCTOR DEVICE HAVING A PATTERNED GATE DIELECTRIC - In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses. | 04-16-2015 |
20150108568 | SEMICONDUCTOR STRUCTURE WITH HIGH ENERGY DOPANT IMPLANTATION - A semiconductor device has an epitaxial layer grown over a substrate, each having a first dopant type. A structure disposed within the epitaxial layer has multiple trenches, each of which has a gate and a source electrode disposed within a shield oxide matrix. Multiple mesas each isolate a pair of the trenches from each other. A body region with a second dopant type is disposed above the epitaxial layer and bridges each of the mesas. A region of elevated concentration of the first dopant type is implanted at a high energy level between the epitaxial layer and the body region, which reduces resistance spreading into a channel of the device. A source region having the first dopant type is disposed above the body region. | 04-23-2015 |
20150115355 | SUPERJUNCTION DEVICE AND SEMICONDUCTOR STRUCTURE COMPRISING THE SAME - The present disclosure relates to a superjunction device and a semiconductor structure having the same. The superjunction device includes a body region of a second conduction type, a drain region of a first conduction type, a drift region located between said body region and said drain region. The drift region includes first regions of a first conduction type and second regions of a second conduction type arranged alternately along a direction being perpendicular to the direction from the body region to the drain region, and a plurality of trench gate structures, each of them comprising a trench extending into said drift region from an upper surface of said body region and a gate electrode in said trench surrounded by a first dielectric layer filling said trench, and a source region of a first conduction type embedded into said body region. There is no source region along at least 10% of the total interface length between the first dielectric layer and the body region. | 04-30-2015 |
20150137223 | Transistor Component - A transistor component includes a semiconductor body, a first main electrode, a gate contact electrode, a plurality of transistor cells, and a plurality of gate electrodes. The semiconductor body has a drain region and a drift region of a first conduction type, and a body region of a second conduction type. The first main electrode is on a top side of the semiconductor body. The plurality of gate electrodes is electrically connected to the gate contact electrode and arranged successively in a first lateral direction. In the plurality, a first gate electrode is next to a second gate electrode. The first main electrode includes a first trench contact finger, between the first gate electrode and the second gate electrode, and a second trench contact finger, between the first gate electrode and the second gate electrode, electrically connecting the first main electrode to the body region. | 05-21-2015 |
20150137224 | Semiconductor Device, Integrated Circuit and Method of Forming a Semiconductor Device - A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface. | 05-21-2015 |
20150137225 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process. | 05-21-2015 |
20150145029 | SEMICONDUCTOR DEVICE HAVING BURIED GATE ELECTRODE STRUCTURES - A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure. | 05-28-2015 |
20150295077 | Apparatus and Method for Power MOS Transistor - An apparatus comprises a buried layer over a substrate, an epitaxial layer over the buried layer, a first trench extending through the epitaxial layer and partially through the buried layer, a second trench extending through the epitaxial layer and partially through the buried layer, a dielectric layer in a bottom portion of the first trench, a first gate region in an upper portion of the first trench, a second gate region in the second trench, wherein the second gate region is electrically coupled to the first gate region, a drain region in the epitaxial layer and a source region on an opposite side of the first trench from the drain region. | 10-15-2015 |
20150311288 | MULTI-GATE VDMOS TRANSISTOR - Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate. | 10-29-2015 |
20150311295 | SPLIT POLY CONNECTION VIA THROUGH-POLY-CONTACT (TPC) IN SPLIT-GATE BASED POWER MOSFETS - Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-29-2015 |
20150311297 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF - Provided are a semiconductor device and a method of forming thereof. The semiconductor device includes a substrate having an isolating trench defining active areas, gate structures formed in the active area and crossing the isolating trench, a first protection layer formed on the active area of the substrate, and a second protection layer formed on the first protection layer, wherein, in a first isolating area in which the gate structure and the isolating trench cross, the first protection layer is conformally formed on an inner wall and bottom of the isolating trench, and the second protection layer is formed on the first protection layer formed on the bottom of the isolating trench. | 10-29-2015 |
20150349057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench. | 12-03-2015 |
20150349113 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, includes a first semiconductor layer of a first conductivity, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity. A first plurality of source elements are spaced from each other and a first gate electrode extends continuously between the source elements. A source electrode is electrically connected to the source elements, and a drain electrode is on the first semiconductor layer such that the first semiconductor layer is between the second semiconductor layer and the drain electrode. By employing this structure, an inactive region decreases, and an active area ratio increases. Thereby, a breakdown voltage can be maintained while an on-resistance can be reduced. | 12-03-2015 |
20150372090 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced. | 12-24-2015 |
20150372132 | SEMICONDUCTOR DEVICE WITH COMPOSITE TRENCH AND IMPLANT COLUMNS - A metal insulator semiconductor field effect transistor (MISFET) such as a super junction metal oxide semiconductor FET with high voltage breakdown is realized by, in essence, stacking a relatively low aspect ratio column (trenches filled with dopant, e.g., p-type dopant) on top of a volume or volumes formed by implanting the dopant in lower layers. Together, the low aspect ratio column and the volume(s) form a continuous high aspect ratio column. | 12-24-2015 |
20150380545 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region. | 12-31-2015 |
20160013311 | Semiconductor Device Having a Dense Trench Transistor Cell Array | 01-14-2016 |
20160020287 | Semiconductor Device with Field Electrode and Field Dielectric - A semiconductor device includes a field electrode structure that includes a field electrode and a field dielectric surrounding the field electrode. The field dielectric includes a first dielectric layer and a second dielectric layer having a smaller band gap and/or a lower conduction band edge than the first dielectric layer. A semiconductor body includes a transistor section that surrounds the field electrode structure and directly adjoins the first dielectric layer. The transistor section includes a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section. | 01-21-2016 |
20160049484 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductivity-type second semiconductor layer selectively provided on a first conductivity-type first semiconductor layer, a first conductivity-type third semiconductor layer provided on the second semiconductor layer, and at least one control electrode that is spaced from the second semiconductor layer and the third semiconductor layer by an insulating film. In addition, the semiconductor device further includes a second conductivity-type fourth semiconductor layer provided on a side of the control electrode opposite to a side thereof where the second semiconductor layer is located, and a semiconductor region that is provided between the first semiconductor layer and the fourth semiconductor layer, the first semiconductor layer making contact in the insulating film at the bottom of the control electrode, and containing at least one type of electrically inactive element in at least any one of the first semiconductor layer and the fourth semiconductor layer. | 02-18-2016 |
20160049509 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer having a first surface and a second surface opposed to the first surface, a control electrode provided on the second surface side of the semiconductor layer, and a conductor provided on the second surface which is electrically connected to the control electrode. The conductor includes a first portion provided on the second surface, and at least one second portion reaching from the first portion into the semiconductor layer. | 02-18-2016 |
20160056160 | SEMICONDUCTOR DEVICE HAVING PASSING GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region. | 02-25-2016 |
20160064496 | Semiconductor Device with Field Electrode and Contact Structure - A semiconductor device includes a field electrode structure with a field electrode and a field dielectric surrounding the field electrode. A semiconductor body includes a transistor section surrounding the field electrode structure and including a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section. A gate structure surrounds the field electrode structure and includes a gate electrode and a gate dielectric separating the gate electrode and the body zone. A contact structure directly adjoins the source and body zones and surrounds the field electrode structure equably with respect to the field electrode structure. | 03-03-2016 |
20160064548 | Semiconductor Device with a Termination Mesa Between a Termination Structure and a Cell Field of Field Electrode Structures - A semiconductor device includes a cell field with a plurality of field electrode structures and cell mesas. The field electrode structures are arranged in lines. The cell mesas separate neighboring ones of the field electrode structures from each other. Each field electrode structure includes a field electrode and a field dielectric separating the field electrode from a semiconductor body. A termination structure surrounds the cell field, extends from a first surface into the semiconductor body, and includes a termination electrode and a termination dielectric separating the termination electrode from the semiconductor body. The termination and field dielectrics have the same thickness. A termination mesa, which is wider than the cell mesas, separates the termination structure from the cell field. | 03-03-2016 |
20160071940 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a first electrode over the first semiconductor layer, second and third electrodes extending in the first semiconductor layer in a direction from the first electrode to the first semiconductor layer, a second semiconductor layer of a second conductivity type on the first semiconductor layer. The device further includes third semiconductor layers of the second conductivity type between the first semiconductor layer and each of the second electrode and the third electrode, first insulating films between one of the third semiconductor layers and the second electrode and between the other of the third semiconductor layers and the third electrode, a fourth semiconductor layer of the first conductivity type on the second semiconductor layer, and a fourth electrode extending through the fourth semiconductor layer and the second semiconductor layer to the first semiconductor layer. | 03-10-2016 |
20160099308 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. | 04-07-2016 |
20160099325 | DUAL OXIDE TRENCH GATE POWER MOSFET USING OXIDE FILLED TRENCH - A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness greater than the first thickness. | 04-07-2016 |
20160099351 | SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD - This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt. | 04-07-2016 |
20160104782 | TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a transistor structure includes a step of implanting a light dosage into a substrate at a bit line junction and two cell side junctions, and a step of implanting a light dosage into the bit line junction an additional time. A uniform region having a substantially uniform dopant concentration is formed at the bit line junction. The dopant concentration of the uniform region is higher than that of the cell side junctions and higher than that of the region of the bit line junction under the uniform region. | 04-14-2016 |
20160104797 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench. | 04-14-2016 |
20160133479 | ISOLATION STRUCTURE INTEGRATED WITH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing an isolation structure integrated with semiconductor device includes following steps. A substrate is provided. A plurality of trenched gates is formed in the substrate. A first insulating layer and a second insulating layer are sequentially deposited on the substrate. A first etching process is performed to remove portions of the second insulating layer to expose portions of the first insulating layer. A second etching process is then performed to remove the exposed second insulating layer to expose the trenched gates and to define at least an active region. | 05-12-2016 |
20160163806 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film. | 06-09-2016 |
20160163858 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto. | 06-09-2016 |
20160172483 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 06-16-2016 |
20160181379 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 06-23-2016 |
20160181417 | Transistor Device with Field-Electrode | 06-23-2016 |
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