Class / Patent application number | Description | Number of patent applications / Date published |
257201000 | Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs | 63 |
20090050939 | III-NITRIDE DEVICE - A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body. | 02-26-2009 |
20090057721 | SEMICONDUCTOR DEVICE, EPITAXIAL WAFER, AND METHOD OF MANUFACTURING THE SAME - A manufacturing method and a semiconductor device produced by the method are provided, in which the semiconductor device can easily be manufactured while the hydrogen concentration is decreased. An N-containing InGaAs layer | 03-05-2009 |
20090065812 | COMPOUND SEMICONDUCTOR SUBSTRATE - Provides is a compound semiconductor substrate about which the thickness of its nitride semiconductor single crystal layer can be made large while the generation of cracks, crystal defects or the like is restrained in the nitride semiconductor single crystal layer. The substrate has a first intermediate layer | 03-12-2009 |
20090146187 | Nitride semiconductor element and process for producing the same - An undoped GaN layer, a silicon film, an n type GaN layer, an MQW active layer and a p type GaN layer are stacked sequentially in this order on an AlN buffer layer formed on a sapphire substrate. In this manner, the silicon film is formed in the mid-section of the GaN layers. The AlN buffer layer is crystal-grown at a high temperature. The construction is formed such that a reflectivity of light from a crystal-growing surface is once decreased in a crystal-growing process of the n type GaN layer formed on the silicon film, and the reflectivity of light is increased from the crystal-growing surface in a crystal-growing process of a nitride semiconductor layer to be formed on the n type GaN layer. | 06-11-2009 |
20090184342 | METHOD FOR ENHANCING GROWTH OF SEMI-POLAR (AL,IN,GA,B)N VIA METALORGANIC CHEMICAL VAPOR DEPOSITION - A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film. | 07-23-2009 |
20090194793 | III-NITRIDE WAFER AND DEVICES FORMED IN A III-NITRIDE WAFER - A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body. | 08-06-2009 |
20090206371 | NITRIDE SEMICONDUCTOR DEVICE AND POWER CONVERSION APPARATUS INCLUDING THE SAME - A nitride semiconductor device includes a first, a second, and a third nitride semiconductor layers that are laminated on a foundation semiconductor layer in stated order, the third nitride semiconductor layer having a wider band gap as compared with the second nitride semiconductor layer, a recess area that is dug from an upper surface of the third nitride semiconductor layer down to a middle of the second nitride semiconductor layer, a first electrode and a second electrode respectively formed on one side and the other side of the recess area so as to be in contact with one of the third nitride semiconductor layer and the second nitride semiconductor layer, a dielectric film formed on the third nitride semiconductor layer and an inner surface of the recess area, and a control electrode formed on the dielectric film in the recess area. | 08-20-2009 |
20090230433 | Nitride semiconductor device - A nitride semiconductor device includes an n-type layer made of a group III nitride semiconductor and a layer made of a group III nitride semiconductor containing a p-type impurity laminated and formed in contact with the n-type layer, and Al is contained in a portion of the n-type layer in contact with the layer containing the p-type impurity. | 09-17-2009 |
20090250725 | OHMIC METAL CONTACT PROTECTION USING AN ENCAPSULATION LAYER - A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step. | 10-08-2009 |
20090309135 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device ( | 12-17-2009 |
20100032719 | PROBES FOR SCANNING PROBE MICROSCOPY - Disclosed are probes for scanning probe microscopy comprising a semiconductor heterostructure and methods of making the probes. The semiconductor heterostructure determines the optical properties of the probe and allows for optical imaging with nanometer resolution. | 02-11-2010 |
20100052016 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE OF SAME - A method of manufacturing a nitride semiconductor structure includes disposing a semiconductor substrate in a molecular beam epitaxy reactor; growing a wetting layer comprising Al | 03-04-2010 |
20100065889 | Porous device for optical and electronic applications and method of fabricating the porous device - A porous device for optical and electronic applications comprises a single crystal substrate and a porous single crystal structure epitaxially disposed on the substrate, where the porous single crystal structure includes a three-dimensional arrangement of pores. The three-dimensional arrangement may also be a periodic arrangement. A method of fabricating such a device includes forming a scaffold comprising interconnected elements on a single crystal substrate, where the interconnected elements are separated by voids. A first material is grown epitaxially on the substrate and into the voids. The scaffold is then removed to obtain a porous single crystal structure epitaxially disposed on the substrate, where the single crystal structure comprises the first material and includes pores defined by the interconnected elements of the scaffold. | 03-18-2010 |
20100065890 | Semiconductor Substrate of GaAs and Semiconductor Device - A semiconductor substrate, of GaAs with a semiconductor layer sequence applied on top of the substrate. The semiconductor layer sequence comprises a plurality of semiconductor layers of Al | 03-18-2010 |
20100102360 | Method for producing group III nitride semiconductor and template substrate - The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate. The thickness of the buffer film is regulated to be smaller than that of a buffer film which is employed for epitaxially growing the Group III nitride semiconductor on a planar growth substrate uniformly in a direction perpendicular to the growth substrate. The growth temperature is regulated to be lower than a temperature at which the Group III nitride semiconductor is epitaxially grown on a planar growth substrate uniformly in a direction perpendicular to the growth substrate. The growth temperature is preferably 1,020 to 1,100° C. The buffer film employed is an AlN film having a thickness of 150 Å or less. | 04-29-2010 |
20100193843 | MANUFACTURE METHOD OF MULTILAYER STRUCTURE HAVING NON-POLAR A-PLANE III-NITRIDE LAYER - A manufacture method of a multilayer structure having a non-polar a-plane {11-22} III-nitride layer includes forming a nucleation layer on a r-plane substrate, wherein the nucleation layer is composed of multiple nitride layers; and forming a non-polar a-plane {11-20} III-nitride layer on the nucleation layer. The nucleation layer features reduced stress, reduced phase difference of lattice, blocked elongation of dislocation, and reduced density of dislocation. Thus, the non-polar a-plane {11-20} III-nitride layer with flat surface can be formed. | 08-05-2010 |
20100207166 | Gallium Nitride Heterojunction Schottky Diode - A gallium nitride based semiconductor diode includes a substrate, a GaN layer formed on the substrate, an AlGaN layer formed on the GaN layer where the GaN layer and the AlGaN layer forms a cathode region of the diode, a metal layer formed on the AlGaN layer forming a Schottky junction therewith where the metal layer forms an anode electrode of the diode, and a high barrier region formed in the top surface of the AlGaN layer and positioned under an edge of the metal layer. The high barrier region has a higher bandgap energy than the AlGaN layer or being more resistive than the AlGaN layer. | 08-19-2010 |
20100207167 | COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive. | 08-19-2010 |
20100213513 | Hyperabrupt Diode Structure And Method For Making Same - A hyperabrupt diode structure includes a substrate formed from a low-ohmic contact material, a graded semiconductor layer comprising gallium arsenide, an offset layer comprising indium gallium phosphide over the graded semiconductor layer, a contact layer comprising gallium arsenide over the offset layer, a first electrical contact on the substrate, the first electrical contact forming a cathode of the hyperabrupt diode structure, and a second electrical contact over the contact layer, the second electrical contact forming an anode of the hyperabrupt diode structure. | 08-26-2010 |
20100224912 | Chromium doped diamond-like carbon - A heterojunction is provided for spin electronics applications. The heterojunction includes an n-type silicon semiconductor and a hydrogenated diamond-like carbon film deposited on the n-type silicon semiconductor. The hydrogenated diamond-like carbon film is doped with chromium. The concentration of the chromium dopant in the chromium doped diamond-like carbon film may be configured such that the heterojunction has an increase in forward bias current ranging from about 50% to about 150% in a small magnetic field at about room temperature. The heterojunction has spin electronics properties at about room temperature. | 09-09-2010 |
20100244100 | Compound semiconductor substrate - The present invention provides a compound semiconductor substrate, including: a single-crystal silicon substrate having a crystal face with (111) orientation; a first buffer layer which is formed on the single-crystal silicon substrate and is constituted of an Al | 09-30-2010 |
20100244101 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a method for fabricating a semiconductor device capable of setting carbon concentration within crystal to a desirable value while improving electron mobility. The carbon concentration within a buffer layer is controlled by introducing material gas of hydrocarbon or organic compounds containing carbon such as propane as a dopant in forming the buffer layer by introducing trimethylgallium (TMGa) and ammonium (NH | 09-30-2010 |
20100264463 | SEMICONDUCTOR HETEROSTRUCTURE AND METHOD FOR FORMING SAME - The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a | 10-21-2010 |
20100270592 | SEMICONDUCTOR DEVICE - Semiconductor devices having at least one barrier layer with a wide energy band gap are disclosed. In some embodiments, a semiconductor device includes at least one active layer, and at least one barrier layer disposed on at least one surface of the at least one active layer. The at least one barrier layer has a wider energy band gap than the energy band gap of the at least one active layer. The compounds of the active layer and the barrier layer may be selected to reduce relaxation time of an electron or hole in the active layer. | 10-28-2010 |
20100289063 | EPITAXIAL SOLID-STATE SEMICONDUCTING HETEROSTRUCTURES AND METHOD FOR MAKING SAME - A method for producing a solid-state semiconducting structure, includes steps in which:
| 11-18-2010 |
20100314666 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a first layer made of a first nitride semiconductor; a second layer provided on the first layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a first electrode electrically connected to the second layer; a second electrode provided on the second layer and juxtaposed to the first electrode in a first direction; and a floating electrode provided on the second layer, the floating electrode including: a portion sandwiched by the second electrode in a second direction orthogonal to the first direction; and a portion protruding from the second electrode toward the first electrode. | 12-16-2010 |
20100320506 | Ultra-Low Dislocation Density Group III - Nitride Semiconductor Substrates Grown Via Nano- Or Micro-Particle Film - A high quality Group III-Nitride semiconductor crystal with ultra-low dislocation density is grown epitaxially on a substrate via a particle film with multiple vertically-arranged layers of spheres with innumerable micro- and/or nano-voids formed among the spheres. The spheres can be composed of a variety of materials, and in particular silica or silicon dioxide (SiO2). | 12-23-2010 |
20110024799 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A method for manufacturing a compound semiconductor device includes forming a first compound semiconductor layer over a first substrate, the first compound semiconductor layer containing Al | 02-03-2011 |
20110031534 | PROCESS FOR PRODUCING Si(1-v-w-x)CwAlxNv BASE MATERIAL, PROCESS FOR PRODUCING EPITAXIAL WAFER, Si(1-v-w-x)CwAlxNv BASE MATERIAL, AND EPITAXIAL WAFER - There are provided a Si | 02-10-2011 |
20110042721 | PHOTOVOLTAIC DEVICES - Implementations of quantum well photovoltaic devices are provided. In one embodiment, a photovoltaic device includes an active layer that includes a first barrier layer, a well layer located on the first barrier layer and made of a nitride semiconductor, and a second barrier layer located on the well layer. A metal layer is located adjacent to the active layer. | 02-24-2011 |
20110049572 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode. | 03-03-2011 |
20110049573 | GROUP III NITRIDE SEMICONDUCTOR WAFER AND GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of Al | 03-03-2011 |
20110049574 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode. | 03-03-2011 |
20110084311 | Group III-V semiconductor device with strain-relieving interlayers - According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer. | 04-14-2011 |
20110089469 | Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound - The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance. | 04-21-2011 |
20110127581 | HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS - The present invention relates to a support for the epitaxy of a layer of a material of composition Al | 06-02-2011 |
20110133251 | Gated algan/gan heterojunction schottky device - Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode. | 06-09-2011 |
20110193135 | Methods of Forming Contact Structures Including Alternating Metal and Silicon Layers and Related Devices - A method of forming a semiconductor device, the method comprising providing a semiconductor layer, and providing a first layer of a first metal on the semiconductor layer. A second layer may be provided on the first layer of the first metal. The second layer may include a layer of silicon and a layer of a second metal, and the first and second metals may be different. The first metal may be titanium and the second metal may be nickel. Related devices, structures, and other methods are also discussed. | 08-11-2011 |
20110220967 | PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound. | 09-15-2011 |
20110254057 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING OF THE SAME - Disclosed herein is a nitride based semiconductor device. The nitride based semiconductor device includes: a base substrate; an epitaxial growth layer disposed on the base substrate and having a defect generated due to lattice disparity with the base substrate; a leakage current barrier covering the epitaxial growth layer while filling the defect; and an electrode part disposed on the epitaxial growth layer. | 10-20-2011 |
20110272744 | Laterally Varying II-VI Alloys and Uses Thereof - Described herein are semiconductor structures comprising laterally varying II-VI alloy layer formed over a surface of a substrate. Further, methods are provided for preparing laterally varying II-VI alloy layers over at least a portion of a surface of a substrate comprising contacting at least a portion of a surface of a substrate within a reaction zone with a chemical vapor under suitable reaction conditions to form a laterally varying II-VI alloy layer over the portion of the surface of the substrate, wherein the chemical vapor is generated by heating at least two II-VI binary compounds; and the reaction zone has a temperature gradient of at least 50-100° C. along an extent of the reaction zone. Also described here are devices such as lasers, light emitting diodes, detectors, or solar cells that can use such semiconductor structures. In the case of lasers, spatially varying wavelength can be realized while in the case of solar cells and detectors multiple solar cells can be achieved laterally where each cell absorbs solar energy of a given wavelength range such that entire solar spectrum can be covered by the said solar cell structure. For LED applications, spatial variation of alloy composition can be used to engineer colors of light emission. | 11-10-2011 |
20120018782 | SEMICONDUCTOR DEVICE - An objective is to provide a semiconductor device capable of utilizing properties of a high-mobility electron transport layer with a thin film stacked structure having large ΔEc, high electron mobility, and simplified element fabrication process even when the substrate material and the electron transport layer greatly differ in lattice constant. The semiconductor device includes: a semiconductor substrate ( | 01-26-2012 |
20120126293 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - An epitaxial substrate, in which a group of group-III nitride layers is formed on a single-crystal silicon substrate so that a crystal plane is approximately parallel to a substrate surface, comprises: a first group-III nitride layer formed of AlN on the base substrate; a second group-III nitride layer formed of In | 05-24-2012 |
20120132962 | Method of Manufacturing Semiconductor Device and Semiconductor Device - A method of manufacturing a semiconductor device, in which a second semiconductor layer of Al | 05-31-2012 |
20120161205 | GROUP III NITRIDE SEMICONDUCTOR WAFER AND GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of Al | 06-28-2012 |
20120175682 | OHMIC CONTACT TO SEMICONDUCTOR DEVICE - Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm). | 07-12-2012 |
20120187454 | NITRIDE SUBSTRATES, THIN FILMS, HETEROSTRUCTURES AND DEVICES FOR ENHANCED PERFORMANCE, AND METHODS OF MAKING THE SAME - The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors. | 07-26-2012 |
20120241821 | HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS - A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10 | 09-27-2012 |
20120280281 | GALLIUM NITRIDE OR OTHER GROUP III/V-BASED SCHOTTKY DIODES WITH IMPROVED OPERATING CHARACTERISTICS - A semiconductor device includes a first Group III/V layer and a second Group III/V layer over the first Group III/V layer. The first and second Group III/V layers are configured to form an electron gas layer. The semiconductor device also includes a Schottky electrical contact having first and second portions. The first portion is in sidewall contact with the electron gas layer. The second portion is over the second Group III/V layer and is in electrical connection with the first portion of the Schottky electrical contact. The first portion of the Schottky electrical contact and the first or second Group III/V layer can form a Schottky barrier, and the second portion of the Schottky electrical contact can reduce an electron concentration near the Schottky barrier under reverse bias. | 11-08-2012 |
20130001648 | Gated AlGaN/GaN Schottky Device - Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode. | 01-03-2013 |
20130037858 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer. | 02-14-2013 |
20130043508 | Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound - The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance. | 02-21-2013 |
20130341682 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers. | 12-26-2013 |
20140048851 | SUBSTRATE COMPRISING SI-BASE AND INAS-LAYER - The present invention relates to a substrate ( | 02-20-2014 |
20140097473 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an electron transit layer formed on a substrate and of a group III nitride-based compound semiconductor; an electron supply layer formed on the electron transit layer and of a group III nitride-based compound semiconductor having a higher band gap energy than the transit layer; a field plate layer formed on the supply layer, formed of a non-p-type group III nitride-based compound semiconductor, and having a lower band gap energy than the supply layer; a first electrode forming an ohmic contact with a two-dimensional electron gas layer in the transit layer at an interface thereof with the supply layer; and a second electrode forming a Schottky contact with the electron gas layer. The second electrode forms an ohmic contact, at a side wall of the field plate layer, with two-dimensional hole gas in the field plate layer at an interface thereof with the supply layer. | 04-10-2014 |
20140264459 | High Mobility Transport Layer Structures for Rhombohedral Si/Ge/SiGe Devices - An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhomhohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions. | 09-18-2014 |
20140332855 | REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. | 11-13-2014 |
20150041863 | MULTIJUNCTION PHOTOVOLTAIC DEVICE HAVING AN SI BARRIER BETWEEN CELLS - A photovoltaic device comprises an interface ( | 02-12-2015 |
20150041864 | SEMICONDUCTOR DIODES WITH LOW REVERSE BIAS CURRENTS - A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents. | 02-12-2015 |
20150137187 | SEMICONDUCTOR WAFER, MANUFACTURING METHOD OF SEMICONDUCTOR WAFER AND METHOD FOR MAUNFACTURING COMPOSITE WAFER - A semiconductor wafer comprises, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer in this order, wherein both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent. | 05-21-2015 |
20150333192 | VARACTOR DIODE WITH HETEROSTRUCTURE - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device, such as a varactor diode. The IC device includes a composite collector and heterostructure. A layer of wider band gap material is included as part of the collector at the collector/base interface. The presence of the wide band gap material may increase breakdown voltage and allow for increased hyperabrupt doping profiles in the narrower band gap portion of the collector. This may allow for increased tuning range and improved intermodulation (IMD) performance without the decreased breakdown performance associated with homojunction devices. Other embodiments may also be described and/or claimed. | 11-19-2015 |
20150357417 | Device Isolation for III-V Substrates - Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided. | 12-10-2015 |
20150372097 | METHOD OF FORMING III-V CHANNEL - Embodiments of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one embodiment, a first trench is formed in a dielectric layer formed on a substrate to expose a surface of the substrate, a multi-stack layer structure is formed within the first trench, and a third semiconductor compound layer is formed on the second semiconductor compound layer, wherein the second semiconductor compound layer has an etching resistance against an etchant lower than that of the first and third semiconductor compound layers, a second trench is formed in the dielectric layer to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer, and the second semiconductor compound layer is selectively removed so that the first semiconductor compound layer is isolated from the third semiconductor compound layer by an air gap. | 12-24-2015 |