Entries |
Document | Title | Date |
20080203394 | Method for fabrication of active-matrix display panels - The present invention provides a method of an active-matrix thin film transistor array, comprising of two levels of metallic interconnections formed from one layer of metallic conductor; and thin-film transistors with source, drain and gate electrodes either fully or partially replaced with metal, and wherein the pixel electrodes are polycrystalline silicon. | 08-28-2008 |
20080210945 | Thin film transistor, manufacturing method thereof, and semiconductor device - By a laser crystallization method, a crystalline semiconductor film in which grain boundaries are all in one direction is provided as well as a manufacturing method thereof. In crystallizing a semiconductor film formed over a substrate with linear laser light, a phase-shift mask in which trenches are formed in a stripe form is used. The stripe-form trenches formed in the phase-shift mask are formed so as to make a nearly perpendicular angle with a major axis direction of the linear laser light. CW laser light is used as the laser light, and a scanning direction of the laser light is nearly parallel to a direction of the stripe-form trenches (grooves). By changing luminance of the laser light periodically in the major axis direction, a crystal nucleation position in a semiconductor that is completely melted can be controlled. | 09-04-2008 |
20080217623 | OPTICAL SENSOR ELEMENT AND METHOD FOR DRIVING THE SAME - An optical sensor element includes: an n-type semiconductor region formed on a substrate; an i-type semiconductor region which is formed on the substrate between the p-type semiconductor region and the n-type semiconductor region and which is lower in impurity concentration than the p-type semiconductor region and the n-type semiconductor region; an anode electrode formed on the insulation film and connected to the p-type semiconductor region; and a cathode electrode formed on the insulation film and connected to the n-type semiconductor region. A reverse bias voltage V | 09-11-2008 |
20080224145 | Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof - A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr. | 09-18-2008 |
20080237599 | MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels. | 10-02-2008 |
20080237600 | Thin film transistor - One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode, a gate insulating layer and a semiconductor layer including an oxide, these three elements being formed over the insulating substrate in this order, and the gate insulating layer including: a lower gate insulating layer, the lower gate insulating layer being in contact with the insulating substrate and being an oxide including any one of the elements In, Zn or Ga; and an upper gate insulating layer provided on the lower gate insulating layer, the upper gate insulating layer comprising at least one layer; and a source electrode and a drain electrode formed on the semiconductor layer. | 10-02-2008 |
20080237601 | TRANSISTORS AND SEMICONDUCTOR CONSTRUCTIONS - A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer. | 10-02-2008 |
20080246035 | Semiconductor device and display appliance using the semiconductor device - In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally. As for a signal outputted from the correcting circuit, when a transistor in the objective digital circuit is required to be turned OFF, the correcting circuit outputs a corresponding signal, namely a first power source potential. At this time, the transistor is turned OFF. On the other hand, when the transistor is required to be turned ON, the correcting circuit outputs a first input potential. Consequently, the objective digital circuit is turned OFF when it is required to be in an OFF state while turned ON when it is required to be in an ON state. Thereby, the objective digital circuit can be normally operated. | 10-09-2008 |
20080277665 | SEMICONDUCTOR DEVICE, NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a conductive layer including a first and a second polysilicon layers having different grain boundaries, wherein a portion or an entire region of the first polysilicon layer is crystallized and wherein a grain boundary in a crystallized region is bigger than the grain boundary of the second polysilicon layer. | 11-13-2008 |
20080277666 | Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device - A thin film transistor (TFT) may include a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, and a semiconductor layer on the gate insulating layer. The semiconductor layer may include a top surface, a channel area aligned in a vertical direction with the gate electrode, a plurality of doped areas proximate to the channel area, and a plurality of non-doped areas. Source and drain electrodes may be on the top surface of the semiconductor layer aligned above respective ones of the plurality of non-doped areas of the semiconductor layer. A planarization layer may be on the gate insulating layer, the source and drain electrodes and the semiconductor layer channel area, and may include a plurality of openings respectively exposing the plurality of doped areas of the semiconductor layer and a portion of the source electrode and the drain electrode. | 11-13-2008 |
20080283839 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer. | 11-20-2008 |
20080283840 | THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE - The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film. | 11-20-2008 |
20080296579 | NANOSILICON SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD AND SEMICONDUCTOR CIRCUIT DEVICE USING NANOSILICON SEMICONDUCTOR SUBSTRATE MANUFACTURED BY THE METHOD - This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate. | 12-04-2008 |
20080296580 | SILICON OXIDE FILM, PRODUCTION METHOD THEREFOR AND SEMICONDUCTOR DEVICE HAVING GATE INSULATION FILM USING THE SAME - The present invention provides a high-performance silicon oxide film as a gate insulation film and a semiconductor device having superior electric characteristics. The silicon oxide film according to the present invention includes CO | 12-04-2008 |
20080303027 | Semiconductor Device Made by the Method of Producing Hybrid Orientnation (100) Strained Silicon with (110) Silicon - There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate. | 12-11-2008 |
20080303028 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source and drain electrodes overlap a source region and a drain region of the active layer, respectively, and a thin film of SiN | 12-11-2008 |
20080308809 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE THIN FILM TRANSISTOR, AND DISPLAY DEVICE INCLUDING THE THIN FILM TRANSISTOR - A thin film transistor (TFT), a method of fabricating the TFT, and a display device including the TFT are provided. The TFT includes a semiconductor layer having a channel region and source and drain regions is crystallized using a crystallization-inducing metal. The crystallization-inducing metal is gettered by either a metal other than the crystallization-inducing metal or a metal silicide of a metal other than the crystallization-inducing metal. A length and width of the channel region of the semiconductor layer and a leakage current of the semiconductor layer satisfy the following equation: Ioff/W=3.4E-15 L | 12-18-2008 |
20080315206 | Highly Scalable Thin Film Transistor - Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels. | 12-25-2008 |
20080315207 | METHOD OF FABRICATING POLYCRYSTALLINE SILICON, TFT FABRICATED USING THE SAME, METHOD OF FABRICATING THE TFT, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE TFT - A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 Å on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process. | 12-25-2008 |
20090001377 | PIXEL STRUCTURE AND FABRICATION METHOD THEREOF - A pixel structure and a fabrication method thereof are provided, wherein a semiconductor pattern and a data line are defined simultaneously by performing a half-tone or grey-tone masking process. In addition, a self-alignment manner is further adopted to fabricate a lightly doped region with symmetric lengths on two sides of a channel region through steps such as photoresist ashing and etching, so as to prevent the problem of misalignment of mask generated when a mask is used to define the lightly doped region in the conventional art. Furthermore, a source pattern and a drain pattern are made to directly contact a source region and a drain region of the semiconductor pattern, such that a process of fabricating a via is omitted. Besides, in the present invention, a common line pattern surrounding the peripheral of the pixel region is also formed to improve the aperture ratio of the pixel structure. | 01-01-2009 |
20090014725 | Ion doping apparatus, ion doping method, semiconductor device and method of fabricating semiconductor device - An ion doping apparatus includes: a chamber | 01-15-2009 |
20090020760 | Methods for forming materials using micro-heaters and electronic devices including such materials - Nano-sized materials and/or polysilicon are formed using heat generated from a micro-heater, the micro-heater may include a substrate, a heating element unit formed on the substrate, and a support structure formed between the substrate and the heating element unit. Two or more of the heating element units may be connected in series. | 01-22-2009 |
20090020761 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A separation layer is formed over a substrate, an insulating film | 01-22-2009 |
20090026460 | VERTICAL NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer are formed on a substrate sequentially. The first and the third semiconductor layers have a first conductive state, while the second semiconductor layer has a second conductive state. Several strips of active stacked structures are formed by removing portions of the first, second and third semiconductor layers, and portions of the first and second barrier on the substrate. After forming a storage structure on the substrate, the storage structure is covered with a conductive layer filling spaces among the active stacked structures. A portion of the conductive layer is removed to form word lines across the active stacked structures. | 01-29-2009 |
20090045406 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device which can realize a diode function is provided with a manufacturing process of a polysilicon thin film transistor and without adding a dedicated process. A semiconductor device is provided having a semiconductor layer comprising a low-concentration p-type polysilicon region formed over a substrate, the semiconductor device comprising a high-concentration p-type polysilicon region and a high-concentration n-type polysilicon region which are formed over the substrate on both sides of the low-concentration p-type polysilicon region, an insulating film which is formed over the high-concentration p-type polysilicon region, the low-concentration p-type polysilicon region, and the high-concentration n-type polysilicon region, and a control electrode which is formed over the insulating film and over the low-concentration p-type polysilicon region, wherein the control electrode is electrically connected to one of the high-concentration p-type polysilicon region and the high-concentration n-type polysilicon region. | 02-19-2009 |
20090050891 | PHOTODIODE AND DISPLAY DEVICE - Disclosed is a photodiode having a silicon film ( | 02-26-2009 |
20090057678 | Method of Forming an Integrated Circuit and Integrated Circuit - A method of forming an integrated circuit, the method including forming at least one patterned gate stack on a substrate including a substrate surface; forming an amorphous substrate region in the substrate by implanting a first material in the substrate; and implanting a getter material to form a getter region within the amorphous substrate region; forming doped implant regions extending from the substrate surface in to the substrate by implanting a second material; and thermally recrystallizing the amorphous substrate region. | 03-05-2009 |
20090057679 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A manufacturing method of a TFT is provided. A polysilicon island, a gate insulating layer and a gate are sequentially formed on a substrate. LDD regions are formed in the polysilicon island below two sides of the gate, while the polysilicon island below the gate is a channel region. A metal oxidation process is performed to form a gate oxidation layer on the gate. A source and a drain are formed in the polysilicon island below two sides of the gate oxidation layer. A dielectric layer is formed on the gate insulating layer. Portions of the dielectric layer and the gate insulating layer are removed to expose a portion of the source and drain, and a patterned dielectric layer and a patterned gate insulating layer are formed. A source and a drain conductive layers electrically respectively connected to the source and the drain are formed on the patterned dielectric layer. | 03-05-2009 |
20090057680 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the thin film integrated circuit. A manufacturing method of a semiconductor device includes the steps of forming a first insulating film over one surface of a silicon substrate, forming a layer having at least two thin film integrated circuits over the first insulating film, forming a resin layer so as to cover the layer having the thin film integrated circuit, forming a film so as to cover the resin layer, grinding a backside of one surface of the silicon substrate which is formed with the layer having the thin film integrated circuit, and polishing the ground surface of the silicon substrate. | 03-05-2009 |
20090065779 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a silicon substrate; a gate insulation film formed on the silicon substrate; and a gate electrode formed on the gate insulation film; wherein the gate electrode has a first doped polysilicon film formed on the gate insulation film, and a second doped polysilicon film formed on the first doped polysilicon film; wherein the first doped polysilicon film includes first impurities; and wherein the second doped polysilicon film includes second impurities that has the opposite conductivity type from the first impurities. | 03-12-2009 |
20090085036 | LIGHT SENSOR - A light sensor includes an intrinsic layer, a first ion doping area disposed one side of the intrinsic layer, a second ion doping area disposed at the other side of the intrinsic layer, an oxide insulating layer on the intrinsic layer, and a gate metal on the oxide insulating layer. The first and second ion doping areas have the same P type or N type doped ions. The intrinsic layer further includes a first light sensing region close to the first ion doping area. The first light sensing region is used for generating electron-hole pairs based on luminance of incident light. | 04-02-2009 |
20090090913 | DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC) - A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth. | 04-09-2009 |
20090090914 | SEMICONDUCTOR THIN FILM, METHOD FOR PRODUCING THE SAME, AND THIN FILM TRANSISTOR - A transparent semiconductor thin film | 04-09-2009 |
20090090915 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes the impurity element which serves as a donor. | 04-09-2009 |
20090090916 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor. | 04-09-2009 |
20090095958 | THIN FILM TRANSISTOR ARRAY AND DISPLAYING APPARATUS - A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate electrodes via a gate insulation film so that the source electrodes cross the gate electrodes in a planar view, plural drain electrodes formed at corresponding positions surrounded by the gate electrodes and the source electrodes in a planar view in the same layer as that of the source electrodes, semiconductor layers formed via the gate insulation film to face the gate electrodes for forming corresponding channel regions between the source electrodes and the drain electrodes. The plural gate electrodes are linearly formed, and the channel regions are disposed to face the gate electrodes. | 04-16-2009 |
20090101910 | Thin-film transistor - A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking lay r and a gate insulator of the transistor. | 04-23-2009 |
20090101911 | Thin film transistor, display device having the same, and associated methods - A thin film transistor (TFT), including a substrate, an active layer and a gate electrode on the substrate, and a first gate insulating layer and a second gate insulating layer between the active layer and the gate electrode. Each of the first gate insulating layer and the second gate insulating layer may have a thickness between approximately 200 Å and approximately 400 Å, inclusive. | 04-23-2009 |
20090108265 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer. | 04-30-2009 |
20090127560 | Poly-crystalline thin film, thin film transistor formed from a poly-crystalline thin film and methods of manufacturing the same - Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer. | 05-21-2009 |
20090127561 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND MOBILE DEVICE - A semiconductor device of the present invention includes an insulating substrate, a nonvolatile memory formed above the insulating substrate and having a memory holding portion, and at least one light-shielding body covering an upper side, an under side, or both sides of the memory holding portion, wherein at least one of the light-shielding bodies is installed in such a way that a protrusion degree of the light-shielding body, which is defined by (a length of the light-shielding body protruded from the memory holding portion)/(a distance between the light-shielding body and the memory holding portion), is 0.1 or more. | 05-21-2009 |
20090134394 | CRYSTAL SILICON ARRAY, AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR - A crystal silicon array includes a crystallized unit region obtained by crystallizing at least a part of a non-single crystal semiconductor film. The crystallized unit region includes at least one square two-dimensional crystal portion having a size of 7 μm square or more, and at least one needle crystal portion having a grain length of 3.5 μm or more. | 05-28-2009 |
20090140256 | THIN FILM TRANSISTOR AND SEMICONDUCTOR DEVICE - An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region. | 06-04-2009 |
20090140257 | FILM FORMATION METHOD, THIN-FILM TRANSISTOR AND SOLAR BATTERY - After a gate oxide film | 06-04-2009 |
20090140258 | TRANSISTOR AND DISPLAY AND METHOD OF DRIVING THE SAME - A field-effect transistor including an electrically conductive substrate; a first insulating film coating the electrically conductive substrate; a gate electrode disposed on the electrically conductive substrate with the first insulating film interposed therebetween; a source electrode; a drain electrode opposing the source electrode with the channel therebetween; a second insulating film covering the gate electrode; and a semiconductor layer having a width larger than a width of the gate electrode in the channel width direction and being partly provided on the gate electrode with the second insulating film interposed therebetween so that the gate electrode, the second insulating film, and the semiconductor layer are laminated in the channel. | 06-04-2009 |
20090152558 | Semiconductor device and method of manufacturing the same - Provided is a lateral semiconductor device with a trench structure for improving driving capability. A trench portion is formed in a well to give concave and convex portions in a gate width direction. A gate electrode is formed inside and above the trench portion with an insulating film therebetween. A source region is formed on one side of the gate electrode in a gate length direction, and a drain region is formed on the other side, both formed by impurity diffusion from polycrystalline silicon containing an impurity and filling the inside of the trench portion, deep enough to reach vicinity of the bottom of the gate electrode (vicinity of bottom of trench portion). By thus forming a deep source region and a deep drain region, current flow that would otherwise concentrate on a shallow part in the gate electrode becomes uniform throughout the trench portion and widening of an effective gate width owing to the concave and convex portions formed in the well lowers ON resistance, improving the driving capability. | 06-18-2009 |
20090152559 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND MANUFACTURING METHOD OF DISPLAY DEVICE - A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured. | 06-18-2009 |
20090159891 | MODIFYING A SURFACE IN A PRINTED TRANSISTOR PROCESS - A method of forming an electronic device includes depositing a dielectric, forming a first functional material layer having a first surface energy, depositing at least one first at least semiconductive feature of the device, forming a second functional material layer to provide a surface having a second surface energy, and depositing at least one second at least semiconductive feature of the device to connect to the first at least semiconductive feature of the device. A method of forming an electronic device includes depositing a first, dielectric material, depositing a second material, depositing at least one first at least semiconductive feature of the device on the second material, altering the second material to form a altered second material, and depositing at least one at least semiconductive feature from solution to connect the first semiconductive feature of the device. An electronic device has a substrate, a dielectric layer, a first functional layer having a first surface energy, at least one first at least semiconductive feature on the first functional layer, a second functional layer in a region between adjacent to the first at least semiconductive features, and at least one second at least semiconductive feature on the second functional layer. | 06-25-2009 |
20090159892 | Array substrate for liquid crystal display device and method of fabricating the same - An array substrate for an LCD device includes a first TFT including a first semiconductor layer, a first gate electrode, wherein the first gate electrode is directly over the first semiconductor layer; a first protrusion extending from the first gate electrode along an edge of the first semiconductor layer; a second TFT including a second semiconductor layer, a second gate electrode, wherein the second gate electrode is directly over the second semiconductor layer; a second protrusion extending from the second gate electrode along an edge of the second semiconductor layer; a third TFT connected to crossed data and gate lines including a third semiconductor layer, a third gate electrode, wherein the third gate electrode is directly over the third semiconductor layer; a third protrusion extending from the third gate electrode along an edge of the third semiconductor layer; and a pixel electrode. | 06-25-2009 |
20090159893 | LIGHT-RECEIVING ELEMENT AND DISPLAY DEVICE - A light-receiving element includes: a first-conductivity-type semiconductor region configured to be formed over an element formation surface; a second-conductivity-type semiconductor region configured to be formed over the element formation surface; an intermediate semiconductor region configured to be formed over the element formation surface between the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region, and have an impurity concentration lower than impurity concentrations of the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region. The light-receiving element further includes: a first electrode configured to be electrically connected to the first-conductivity-type semiconductor region; a second electrode configured to be electrically connected to the second-conductivity-type semiconductor region; and a control electrode configured to be formed in an opposed area that exists on the element formation surface. | 06-25-2009 |
20090173944 | THIN FILM TRANSISTOR, ACTIVE DEVICE ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - A thin film transistor (TFT) includes a substrate, a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate and the gate dielectric layer covers the gate. The channel layer is disposed on the gate dielectric layer over the gate, and the source and the drain are respectively disposed on a portion of the channel layer at both sides of the gate. At least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from the material of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å. | 07-09-2009 |
20090173945 | METHOD FOR FORMING CONDUCTIVE FILM, THIN-FILM TRANSISTOR, PANEL WITH THIN-FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR - A conductive film having high adhesion and low specific resistance is formed. A target containing copper as a main component is sputtered in vacuum ambience while an oxygen gas introduced, and then, a conductive film containing copper as a main component and additive metals, such as Ti or Zr, is formed. Such a conductive film has high adhesion to a silicon layer and a glass substrate and is hardly peeled off from the substrate. Furthermore, the specific resistance is low and the contact resistance to a transparent conductive film is also low. Thus, no deterioration in the electric characteristics occurs even when the conductive film is used for an electrode film. Accordingly, the conductive film formed by the present invention suited for TFT, and electrode films and barrier films of semiconductor elements, in particular. | 07-09-2009 |
20090184321 | MICROCRYSTALLINE SILICON THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability. | 07-23-2009 |
20090184322 | ELECTROCONDUCTIVE FILM-FORMING METHOD, A THIN FILM TRANSISTOR, A THIN FILM TRANSISTOR-PROVIDED PANEL AND A THIN FILM TRANSISTOR-PRODUCING METHOD - An electroconductive film having high adhesion and a low resistivity is formed. An electroconductive film composed mainly of copper and containing an addition metal such as Ti is formed by sputtering a target composed mainly of copper in a vacuum atmosphere into which a nitriding gas is introduced. Such an electroconductive film has high adhesion to a silicon layer and a substrate, and is hardly peeled from the substrate. Further, since the electroconductive film has a low resistivity and a low contact resistance to a transparent electroconductive film, the electric characteristics do not degrade even when it is used as an electrode film. The electroconductive film formed by the present invention is suitable particularly as a barrier film for an electrode of a TFT or a semiconductor element. | 07-23-2009 |
20090189160 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE TFT - A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT, the TFT including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer and crystallized using a metal catalyst, and source and drain electrodes disposed on the semiconductor layer and electrically connected to source and drain regions of the semiconductor layer. A second metal is diffused into a surface region of the semiconductor layer, to getter the metal catalyst from a channel region of the semiconductor layer. The second metal can have a lower diffusion coefficient in silicon than the metal catalyst. | 07-30-2009 |
20090194769 | CRYSTALLIZING METHOD, THIN-FILM TRANSISTOR MANUFACTURING METHOD, THIN-FILM TRANSISTOR, AND DISPLAY DEVICE - A crystallizing method of causing a phase shifter to phase-modulate a laser beam whose wavelength is 248 nm or 300 nm or more from an excimer laser unit into a laser beam with a light intensity profile having a plurality of inverted triangular peak patterns in cross section and of irradiating the pulse laser beam onto a substrate to be crystallized for crystallization. The substrate to be crystallized is such that one or more silicon oxide films which present absorption properties to the laser beam and differ in the relative proportions of Si and O are provided on a laser beam incident face. | 08-06-2009 |
20090200557 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer including a channel region, and a first region and a second region to which an impurity element is introduced to make the first region and the second region a source and a drain, a third region, and a gate electrode provided to partly overlap with the semiconductor layer with a gate insulating film interposed therebetween In the semiconductor layer, the first region is electrically connected to the gate electrode through a first electrode to which an AC signal is input, the second region is electrically connected to a capacitor element through a second electrode, the third region overlaps with the gate electrode and contains an impurity element at lower concentrations than each of the first region and the second region. | 08-13-2009 |
20090206341 | Solution-processed high mobility inorganic thin-film transistors - Fluid media comprising inorganic semiconductor components for fabrication of thin film transistor devices. | 08-20-2009 |
20090212292 | Layer-selective laser ablation patterning - A method of fabricating an organic electronic device is provided. The organic electronic device has a structure including an upper conductive layer and an underlying layer immediately beneath said upper conducting layer and having at least one solution process able semiconducting layer. The upper conducting layer preferably has a thickness of between 10 nm and 200 nm. The method includes patterning said upper conductive layer of said structure by: laser ablating said upper conductive layer using a pulsed laser to remove regions of upper conductive layer from said underlying layer for said patterning; and wherein said laser ablating uses a single pulse of said laser to substantially completely remove a said region of said upper conductive layer to expose said underlying layer beneath | 08-27-2009 |
20090212293 | Semiconductor device and method for fabricating the same - A semiconductor device, comprising a substrate, a semiconductive layer and a gate electrode is provided. The semiconductive layer having a crystallization promoting material is formed over the substrate. The semiconductive layer has a channel region, a first doped region and a second doped region. The first doped region has a donor and an acceptor, and the second doped region has a dopant which is selected from one of the donor and the acceptor. The second doped region is disposed between the first doped region and the channel region. The gate electrode is insulated from the channel region. | 08-27-2009 |
20090212294 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. | 08-27-2009 |
20090212295 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile. | 08-27-2009 |
20090224252 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film. | 09-10-2009 |
20090224253 | CRYSTALLIZATION METHOD, THIN FILM TRANSISTOR MANUFACTURING METHOD, THIN FILM TRANSISTOR, DISPLAY, AND SEMICONDUCTOR DEVICE - According to a crystallization method, in the crystallization by irradiating a non-single semiconductor thin film of 40 to 100 nm provided on an insulation substrate with a laser light, a light intensity distribution having an inverse peak pattern is formed on the surface of the substrate, a light intensity gradient of the light intensity distribution is controlled, a crystal grain array is formed in which each crystal grain is aligned having a longer shape in a crystal growth direction than in a width direction and having a preferential crystal orientation (100) in a grain length direction, and a TFT is formed in which a source region and a drain region are formed so that current flows across a plurality of crystal grains of the crystal grain array in the crystal growth direction. | 09-10-2009 |
20090230400 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF - A method for fabricating a thin film transistor is described. The method includes: providing a substrate; forming a sacrificial layer on the substrate; forming a polysilicon pattern layer on the substrate to surround the sacrificial layer; forming a gate insulation layer to cover at least the polysilicon pattern layer; forming a gate pattern on the gate insulation layer above the polysilicon pattern layer; forming a source region, a drain region, and an active region in the polysilicon pattern layer, wherein the active region is between the source region and the drain region; forming a passivation layer to cover the gate pattern and a portion of the gate insulation layer; forming a source conductive layer and a drain conductive layer on the passivation layer, wherein the source conductive layer and the drain conductive layer are electrically connected to the source region and the drain region of the polysilicon pattern layer respectively. | 09-17-2009 |
20090236602 | Integrated Circuit, Semiconductor Device Comprising the Same, Electronic Device Having the Same, and Driving Method of the Same - An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated. | 09-24-2009 |
20090242890 | SEMICONDUCTOR DEVICE, ELECTROOPTICAL APPARATUS, AND ELECTRONIC SYSTEM - A semiconductor device on a flexible substrate includes a semiconductor layer constituting a plurality of bottom-gate thin-film transistors, first wiring lines, second wiring lines, a first insulating layer, and a gate insulating film. The first insulating layer and the gate insulating film are present below the semiconductor layer, the first wiring lines, and the second wiring lines and are partially removed in regions where the semiconductor layer, the first wiring lines, and the second wiring lines are not disposed. | 10-01-2009 |
20090242891 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A thin-film semiconductor device including a transparent insulating substrate, an island semiconductor layer formed on the transparent insulating substrate and including a source region containing a first-conductivity-type impurity and a drain region containing a first-conductivity-type impurity and spaced apart from the source region, a gate insulating film and a gate electrode which are formed on a portion of the island semiconductor layer, which is located between the source region and the drain region, a sidewall spacer having a 3-ply structure including a first oxide film, a nitride film and a second oxide film, which are respectively formed on a sidewall of the gate electrode, and an interlayer insulating film covering the island semiconductor layer and the gate electrode. | 10-01-2009 |
20090242892 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface. Hydrogen is introduced into The active layer. A thin film comprising SiO | 10-01-2009 |
20090250700 | Crystalline Semiconductor Stripe Transistor - A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, a transistor active semiconductor region is formed including a plurality of crystalline semiconductor stripes oriented along parallel axes. In one aspect, a channel region is formed from the plurality of oriented crystalline semiconductor stripes, and the method forms a gate dielectric overlying the channel region, with a gate electrode overlying the gate dielectric. In another aspect, forming the transistor active semiconductor region includes forming source, drain, and channel regions from the plurality of oriented crystalline semiconductor stripes. | 10-08-2009 |
20090256154 | Flexible substrate, method of fabricating the same, and thin film transistor using the same - A flexible substrate for a TFT includes a metal substrate having a predetermined coefficient of thermal expansion, and a buffer layer on the metal substrate, the buffer layer including a silicon oxide or a silicon nitride, wherein the predetermined coefficient of thermal expansion of the metal substrate satisfies an equation as follows, | 10-15-2009 |
20090283770 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer includes a carbon nanotube layer, and the carbon nanotube layer comprises a plurality of semiconducting carbon nanotubes. | 11-19-2009 |
20090283771 | Thin film transistor - A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer comprises at least two stacked carbon nanotube films, and each carbon nanotube film comprises a plurality of carbon nanotubes primarily oriented along a same direction, and the carbon nanotubes in at least two adjacent carbon nanotube films are aligned along different directions. | 11-19-2009 |
20090289258 | Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same - A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same, which allow a size of a grain of a channel region to be increased, can effectively protect the channel region of a semiconductor layer at the time of etching process, and can reduce processing cost. The thin film transistor includes a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer pattern disposed on the gate insulating layer and including a channel region, a source region and a drain region, an etch stop layer pattern disposed on the channel region of the semiconductor layer pattern and having a thickness of 20 to 60nm, and source and drain electrodes disposed on the source and drain regions of the semiconductor layer pattern, respectively. | 11-26-2009 |
20090302321 | Thin Film Transistor Substrate and Method of Manufacturing the Same - A thin film transistor substrate includes; a substrate, an organic layer disposed on the substrate and including a trench formed by etching a predetermined region of an upper portion of the organic layer, a gate electrode disposed in the trench, an insulating layer disposed on the organic layer and the gate electrode, a semiconductor layer disposed on the insulating layer, a source electrode disposed on the semiconductor layer, and a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode. | 12-10-2009 |
20090302322 | Method of Forming a Thin Film Transistor - A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer. | 12-10-2009 |
20090315034 | Thin Film Transistor (TFT), method of fabricating the TFT, and Organic Light Emitting Diode (OLED) display including the TFT - A Thin Film Transistor (TFT) includes: a substrate, a buffer layer arranged on the substrate, a gate electrode arranged on the buffer layer, a gate insulating layer arranged on the gate electrode, a semiconductor layer arranged on the gate insulating layer to correspond to the gate electrode, a heat transfer sacrificial layer arranged on the semiconductor layer, and source and drain electrodes connected to the semiconductor layer. A method of fabricating the TFT and a method of fabricating an Organic Light Emitting Diode (OLED) display having the TFT is also provided. | 12-24-2009 |
20090321742 | THIN FILM TRANSISTOR - A thin film transistor (TFT) including a substrate, a buffer layer, a patterned poly-silicon layer, a gate dielectric layer, and a number of gate electrodes is provided. The patterned poly-silicon layer is disposed on the buffer layer and the substrate. The patterned poly-silicon layer includes a number of channel regions, at least one heavily doped region, two lightly doped regions, a source region, and a drain region. The heavily doped region connects two adjacent channel regions. The source region connects one of the two outmost channel regions through one of the lightly doped regions. The drain region connects the other outmost channel region through the other lightly doped region. The gate dielectric layer covers the patterned poly-silicon layer. The gate electrodes are disposed on the gate dielectric layer and electrically connected to one another. Each gate is disposed above each channel region and a part of the heavily doped region. | 12-31-2009 |
20090321743 | THIN FILM TRANSISTOR, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced. | 12-31-2009 |
20090321744 | BUFFER LAYER FOR PROMOTING ELECTRON MOBILITY AND THIN FILM TRANSISTOR HAVING THE SAME - A buffer layer for promoting electron mobility. The buffer layer comprises amorphous silicon layer (a-Si) and an oxide-containing layer. The a-Si has high enough density that the particles in the substrate are prevented by the a-Si buffer layer from diffusing into the active layer. As well, the buffer, having thermal conductivity, provides a good path for thermal diffusion during the amorphous active layer's recrystallization by excimer laser annealing (ELA). Thus, the uniformity of the grain size of the crystallized silicon is improved, and electron mobility of the TFT is enhanced. | 12-31-2009 |
20100001280 | TFT MONOS OR SONOS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 01-07-2010 |
20100001281 | TFT SAS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 01-07-2010 |
20100001282 | TFT FLOATING GATE MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 01-07-2010 |
20100001283 | TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION - An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit. | 01-07-2010 |
20100006847 | SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, PHOTO-ELECTRICAL APPARATUS, AND METHOD FOR FABRICATING THE SAME - A semiconductor device and the method for fabricating the same are disclosed. The fabrication method includes forming a PMOS device and an NMOS device on a substrate, wherein the PMOS device includes a first poly-silicon island, a gate dielectric layer covering the first poly-silicon island, and a first gate on the gate dielectric layer. The method of fabrication the PMOS device includes performing a P-type ion implantation process on the first poly-silicon island to form a plurality of P-type heavily doped regions and a plurality of P-type lightly doped regions. The length of the channel region is substantially less than 3 micron, and the length of at least one of the P-type lightly doped regions substantially is 10%-80% of the length of the channel region. The P-type lightly doped regions are used to improve the short channel effect of the PMOS device. | 01-14-2010 |
20100006848 | SEMICONDUCTOR DEVICE - To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element. | 01-14-2010 |
20100006849 | Thin Film Transistors - A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency. | 01-14-2010 |
20100006850 | BEOL COMPATIBLE FET STRUCTURE - This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration. | 01-14-2010 |
20100012942 | Poly-si thin film transistor and method of manufacturing the same - Provided may be a Poly-Si thin film transistor (TFT) and a method of manufacturing the same. The Poly-Si TFT may include a first Poly-Si layer on an active layer formed of Poly-Si and doped with a low concentration; and a second Poly-Si layer on the first Poly-Si layer and doped with the same concentration as the first Poly-Si layer or with a higher concentration than the first Poly-Si layer, wherein lightly doped drain (LDD) regions capable of reducing leakage current may be formed in inner end portions of the first Poly-Si layer. | 01-21-2010 |
20100012943 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention relates to a thin film transistor and a manufacturing method thereof. A thin film transistor according to an exemplary embodiment of the present invention includes: a first electrode arranged on a substrate; a second electrode arranged on the substrate and separated from the first electrode; a first ohmic contact arranged on an upper surface of the first electrode; a second ohmic contact arranged on an upper surface of the second electrode; a first buffer member covering a lateral surface of the first electrode and the second electrode; a semiconductor member contacted with an upper surface of the first buffer member, and the first ohmic contact and the second ohmic contact; an insulating layer arranged on the semiconductor member; and a third electrode arranged on the insulating layer, and disposed on the semiconductor member. | 01-21-2010 |
20100025690 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes an insulating plate, a plurality of fan-out lines arranged on the insulating plate and including at least a pair of adjacent fan-out lines, a plurality of signal lines connected to the plurality of fan-out lines, and a plurality of thin film transistors connected to the plurality of signal lines. The adjacent fan-out lines partially overlap with each other, and each overlapping area of the adjacent fan-out lines is the same. | 02-04-2010 |
20100032675 | Component Comprising a Thin-Film Transistor and CMOS-Transistors and Methods for Production - An electrical component, in the crystalline semiconductor body of which several CMOS transistors in high-voltage or low-voltage technology are formed. The individual CMOS transistors are separated from one another by insulation regions. On one insulation region, a thin-film transistor is formed, having a gate that is realized simultaneously with the gates of the CMOS transistors from the same polysilicon layer. The gate oxide of the thin-film transistor, just like a second polysilicon layer for source drain and body of the thin-film transistor, can be produced together with the structural elements already present in the CMOS process. | 02-11-2010 |
20100032676 | Semiconductor integrated circuit device and a manufacturing method for the same - Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design. | 02-11-2010 |
20100059756 | Thin film transistor and method of manufacturing the same - Disclosed is a thin film transistor (TFT). The TFT may include an intermediate layer between a channel and a source and drain. An increased off current, which may occur to a drain area of the TFT, is reduced due to the intermediate layer. Accordingly, the TFT may be stably driven. | 03-11-2010 |
20100072480 | Thin film transistor and method of manufacturing the same - A thin film transistor (TFT) and a method of manufacturing the same are provided, the TFT including a gate insulating layer on a gate. A channel may be formed on a portion of the gate insulating layer corresponding to the gate. A metal material may be formed on a surface of the channel. The metal material crystallizes the channel. A source and a drain may contact side surfaces of the channel. | 03-25-2010 |
20100078644 | INSULATING FILM PATTERN, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE USING THE SAME - In an insulating film pattern, a first pattern part is formed at one surface of the insulating film pattern to form a source electrode, a drain electrode, and a semiconductor layer of the thin film transistor. The first pattern part is recessed in one surface of the insulating film pattern. The insulating film pattern is formed on a substrate through an imprint scheme, and is deposited on a base substrate having a gate electrode and a gate line through a contact print scheme. A source electrode, drain electrode, and semiconductor layer of a thin film transistor are formed through an inkjet print scheme using a first pattern part of the insulating film pattern. A gate electrode and gate line may be formed using a second pattern part of the insulating film pattern | 04-01-2010 |
20100078645 | SEMICONDUCTOR DEVICE COMPRISING A BURIED POLY RESISTOR - An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance. | 04-01-2010 |
20100090222 | THIN FILM TRANSISTOR; METHOD OF MANUFACTURING SAME; AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE THIN FILM TRANSISTOR - A thin film transistor according to one or more embodiments of the present invention includes: an insulation substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a semiconductor formed on the gate insulating layer and having a pair of openings facing each other; ohmic contact layers formed in the openings and including a conductive impurity; and a source electrode and a drain electrode in contact with their respective ohmic contact layers. An organic light emitting device in accordance with an embodiment includes: a first signal line and a second signal line intersecting each other on an insulation substrate; a switching thin film transistor connected to the first signal line and the second signal line; a driving thin film transistor connected to the switching thin film transistor; and a light emitting diode (LED) connected to the driving thin film transistor. | 04-15-2010 |
20100096637 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer. | 04-22-2010 |
20100102324 | SWITCHING ELEMENT AND MANUFACTURING METHOD THEREOF - Disclosed is a switching element provided with a gate dielectric film and an active layer disposed in contact with the gate dielectric film. The active layer includes carbon nanotubes, and the gate dielectric film includes non-conjugated polymer containing an aromatic ring in a side chain. | 04-29-2010 |
20100102325 | VACUUM CHANNEL TRANSISTOR AND DIODE EMITTING THERMAL CATHODE ELECTRONS, AND METHOD OF MANUFACTURING THE VACUUM CHANNEL TRANSISTOR - Provided are a transistor and a method of manufacturing the transistor, and more particularly, a vacuum channel transistor emitting thermal cathode electrons and a method of manufacturing the vacuum channel transistor. The vacuum channel transistor includes: a motherboard; a micro heater member having a thin-film structure formed on the motherboard; a cathode member having a thin-film structure spaced apart from a center part of the micro heater member by a first interval and formed on the micro heater member; a gate member formed on both outer walls of upper parts of the cathode member; and an anode member spaced apart from the cathode member by a second interval through spacers disposed on the gate member, wherein a vacuum electron passing area is interposed between the cathode member and the anode member by the second interval. | 04-29-2010 |
20100109012 | STRESS TRANSFER ENHANCEMENT IN TRANSISTORS BY A LATE GATE RE-CRYSTALLIZATION - A gate electrode structure of a transistor may be formed so as to exhibit a high crystalline quality at the interface formed with a gate dielectric material, while upper portions of the gate electrode may have an inferior crystalline quality. In a later manufacturing stage after implementing one or more strain-inducing mechanisms, the gate electrode may be re-crystallized, thereby providing increased stress transfer efficiency, which in turn results in an enhanced transistor performance. | 05-06-2010 |
20100117089 | LIQUID CRYSTAL DISPLAY DEVICE HAVING DRIVE CIRCUIT AND FABRICATING METHOD THEREOF - A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a second active layer in the peripheral region by etching the polycrystalline silicon film, forming a first gate electrode over the first active layer, a second gate electrode over the second active layer and a gate line connected to the first gate electrode, and forming first source and drain electrodes connected to the first active layer, second source and drain electrodes connected to the second active layer and data line connected to the first source electrode. Further, the second gate electrode overlaps the first active layer to form a first channel region, and the first channel region is formed inside one of the grains. | 05-13-2010 |
20100127268 | THIN FILM TRANSISTORS AND HIGH FILL FACTOR PIXEL CIRCUITS AND METHODS FOR FORMING SAME - A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures. | 05-27-2010 |
20100127269 | METHOD AND STRUCTURE FOR ESTABLISHING CONTACTS IN THIN FILM TRANSISTOR DEVICES - The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general. | 05-27-2010 |
20100127270 | THIN FILM TRANSISTOR - A thin film transistor is provided. The thin film transistor includes a gate, at least one inorganic material layer, at least one dielectric layer, a source, a drain and an active layer. The gate is disposed on the substrate. The inorganic material layer covers the gate. The dielectric layer including at least one organic material covers the substrate and has an opening exposing the inorganic material layer on the gate. The source and the drain are disposed on the dielectric layer and a part of the inorganic layer exposed by the opening respectively. A channel region exists between the source and the drain. The active layer is disposed on the channel region. | 05-27-2010 |
20100133544 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF - A thin film transistor (TFT) includes a poly-silicon island, a gate insulating layer, a gate stack layer, and a dielectric layer. The poly-silicon island includes a source region and a drain region. The gate insulating layer covers the poly-silicon island. The gate stack layer is disposed on the gate insulating layer and includes a first conductive layer and a second conductive layer. A length of the first conductive layer is less than a length of the second conductive layer. The dielectric layer covers the gate insulating layer and the gate stack layer, and therefore a number of cavities are formed between the second conductive layer and the gate insulating layer. | 06-03-2010 |
20100148181 | NANOCRYSTAL SILICON LAYER STRUCTURES FORMED USING PLASMA DEPOSITION TECHNIQUE, METHODS OF FORMING THE SAME, NONVOLATILE MEMORY DEVICES HAVING THE NANOCRYSTAL SILICON LAYER STRUCTURES, AND METHODS OF FABRICATING THE NONVOLATILE MEMORY DEVICES - Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a substrate and forming a nanocrystal silicon layer on the buffer layer by a plasma deposition technique using silicon (Si)-containing gas and hydrogen (H | 06-17-2010 |
20100163884 | SWITCHING DEVICE STRUCTURE OF ACTIVE MATRIX DISPLAY - A switching device structure of active matrix display is provided. The switching device structure includes a substrate, a plurality of switching-device gate connection lines disposed on the substrate along a first direction and a plurality of switching devices disposed on the substrate along the first direction. Each switching device includes a gate electrode electrically connected to the any two adjacent switching-device gate connection lines, and the gate electrode protrudes from at least one side of the switching-device gate connection line along a second direction. | 07-01-2010 |
20100171122 | PHOTOELECTRIC CONVERSION DEVICE, ELECTRO-OPTIC DEVICE, AND ELECTRONIC DEVICE - The photoelectric conversion device includes: a photoelectric conversion element in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order; and a thin film transistor (TFT) connected to the first electrode of the photoelectric conversion element via a contact hole, wherein the photoelectric conversion layer including a first photoelectric conversion layer disposed at a location which does not overlap with the contact hole and a second photoelectric conversion layer disposed at a location which overlaps with the contact hole, the first photoelectric conversion layer and the second photoelectric conversion layer are separated from each other by a separation groove, and the second electrode is selectively formed on the first photoelectric conversion layer, and the photoelectric conversion element is formed by the first electrode, the first photoelectric conversion layer, and the second electrode. | 07-08-2010 |
20100181573 | GATED CO-PLANAR POLY-SILICON THIN FILM DIODE - A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate. | 07-22-2010 |
20100187535 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND MANUFACTURING METHOD OF DISPLAY DEVICE - To provide a method for manufacturing a thin film transistor and a display device using a small number of masks, a thin film transistor is manufactured in such a manner that a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked; then, a resist mask is formed thereover; first etching is performed to form a thin-film stack body; second etching in which the first conductive film is side-etched is performed by dry-etching to form a gate electrode layer; and a source electrode, a drain electrode, and the like are formed. Before the dry etching, it is preferred that at least a side surface of the etched semiconductor film be oxidized. | 07-29-2010 |
20100193796 | Semiconductor device - The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer. | 08-05-2010 |
20100193797 | Stacked transistors and electronic devices including the same - Stacked transistors and electronic devices including the stacked transistors. An electronic device includes a substrate, a first transistor on the substrate and including a first active layer, a first gate, and a first gate insulating layer between the first active layer and the first gate, a first metal line spaced apart from the first gate on the substrate, a first insulating layer covering the first transistor and the first metal line, and a second transistor on the first insulating layer between the first transistor and the first metal line, and including a second active layer, a second gate, and a second gate insulating layer between the second active layer and the second gate. | 08-05-2010 |
20100200860 | Thin Film Transistor Array Panel and Manufacturing Method Thereof - A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region. | 08-12-2010 |
20100237351 | METHOD OF MANUFACTURING A DOUBLE GATE TRANSISTOR - A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region ( | 09-23-2010 |
20100237352 | ELECTRONIC DEVICE AND A METHOD OF MANUFACTURING AN ELECTRONIC DEVICE - The invention relates to an electronic device comprising a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT comprising a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device. | 09-23-2010 |
20100237353 | Thin Film Transistor, Method of Fabricating the Same, and Method of Fabricating Liquid Crystal Display Device Having the Same - A thin film transistor includes a gate electrode, a gate insulation layer on the gate electrode, source and drain electrodes formed on the gate insulation layer, a polysilicon channel layer overlapping the ohmic contact layers and on the gate insulation layer between the source and drain electrodes, ohmic contact regions over the source and drain electrodes for contacting the polysilicon channel to the source and drain electrodes, and doping layers over the source and drain electrodes. | 09-23-2010 |
20100237354 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light. | 09-23-2010 |
20100258808 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor and a manufacturing method thereof are provided. A bottom gate, a gate insulating layer and an amorphous semiconductor layer are formed on a substrate. The amorphous semiconductor layer has an uneven upper surface. A laser annealing process is performed on the amorphous semiconductor layer through the uneven upper layer to transform the amorphous semiconductor layer into a polycrystalline semiconductor layer having a smaller-crystallizing-section and a greater-crystallizing-section. Another gate insulating layer, an upper gate and patterned photoresist layer are formed on the polycrystalline semiconductor layer. Patterns of the upper gate and the bottom gate are defined by the same photo-mask. A source/drain is formed in the polycrystalline semiconductor layer. An etching process with etching selectivity is performed on the upper gate and the patterned photoresist layer to make a length of the upper gate shorter than that of the bottom gate. | 10-14-2010 |
20100258809 | METHOD OF MANUFACTURING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES IN A BULK SEMIDONDUCTOR WAFER - A method of forming a localized SOI structure in a substrate ( | 10-14-2010 |
20100264420 | Semiconductor Device and Manufacturing Method Thereof - An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate, a gate insulating film over the gate electrode, a first source or drain electrode over the gate insulating film, an island-shaped semiconductor film over the first source or drain electrode, and a second source or drain electrode over the island-shaped semiconductor film and the first source or drain electrode. Further, the second source or drain electrode is in contact with the first source or drain electrode, and the island-shaped semiconductor film is sandwiched between the first source or drain electrode and the second source or drain electrode. Moreover, the present invention relates to a manufacturing method of the semiconductor device. | 10-21-2010 |
20100270557 | METHODS OF PRODUCING HIGH UNIFORMITY IN THIN FILM TRANSISTOR DEVICES FABRICATED ON LATERALLY CRYSTALLIZED THIN FILMS - Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films are described. A thin film transistor (TFT) includes a channel area disposed in a crystalline substrate, which has grain boundaries that are approximately parallel with each other and are spaced apart with approximately equal spacings. The shape of the channel area includes a non-equiangular polygon that has two opposing side edges that are oriented substantially perpendicular to the grain boundaries. The polygon further has an upper edge and a lower edge. At least a portion of each of the upper and lower edges is oriented at a tilt angle with respect to the grain boundaries. The tilt angles are selected such that the number of grain boundaries covered by the polygon is independent of the location of the channel area within the crystalline substrate. | 10-28-2010 |
20100270558 | FABRICATING METHOD OF POLYCRYSTALLINE SILICON THIN FILM, POLYCRYSTALLINE SILICON THIN FILM FABRICATED USING THE SAME - Provided are a method of fabricating a polycrystalline silicon thin film using high temperature heat generated by Joule heating induced by application of an electrical field to a conductive layer, which can ensure process stability at high temperature and thus processing time can be reduced and a polycrystalline silicon thin film having excellent crystallinity can be obtained, a polycrystalline thin film using the method and a thin film transistor including the polycrystalline thin film. The method includes providing a substrate, forming a metal or metal alloy layer having a melting point of 13000 C or more on the substrate, forming an insulating layer on the metal or metal alloy layer, forming an amorphous silicon (a-Si) thin film, an amorphous/polycrystalline composite silicon thin film, or a poly-Si thin film on the insulating layer, and applying an electrical filed to the metal or metal alloy layer to induce Joule heating and generate high temperature heat, and crystallizing and annealing the amorphous silicon (a-Si) thin film, the amorphous/polycrystalline composite silicon thin film, or the poly-Si thin film using the high temperature heat. | 10-28-2010 |
20100276693 | FINFET FIELD EFFECT TRANSISTOR INSULATED FROM THE SUBSTRATE - A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates. | 11-04-2010 |
20100283059 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: an insulating substrate; a stepwise layer arranged on the insulating substrate and having an end portion whose inclination angle is equal to or greater than 60°; an insulating layer formed on the insulating substrate and the stepwise layer so as to be elevated on the stepwise layer; a first semiconductor layer arranged at a portion adjacent to the elevated insulating layer; and a second semiconductor layer structured with a material identical to that of the first semiconductor layer, and formed in an island shape on the elevated insulating layer. | 11-11-2010 |
20100301343 | Metal oxynitride thin film transistors and circuits - Thin film transistors and circuits having improved mobility and stability are disclosed in this invention to have metal oxynitrides as the active channel layers. In one embodiment, the charge carrier mobility in the thin film transistors is increased by using the metal oxynitrides as the active channel layers. In another embodiment, a thin film transistor having a p-type metal oxynitride active channel layer and a thin film transistor having an n-type metal oxynitride active channel layer are fabricated to forming a CMOS circuit. In yet another embodiment, thin film transistor circuits having metal oxynitrides as the active channel layers are provided. | 12-02-2010 |
20100301344 | DIELECTRIC LAYER FOR AN ELECTRONIC DEVICE - A dielectric layer for an electronic device, such as a thin-film transistor, is provided. The dielectric layer comprises a molecular glass. The resulting dielectric layer is very thin, pure, and stable. Processes and compositions for fabricating such a dielectric layer are also disclosed. | 12-02-2010 |
20100314624 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element. | 12-16-2010 |
20110017997 | Diffusion Barrier Coated Substrates and Methods of Making the Same - Semiconductor devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The semiconductor devices include a metal substrate, a diffusion barrier layer on the metal substrate, an insulator layer on the diffusion barrier layer, and a semiconductor layer on the insulator layer. The method includes forming a diffusion barrier layer on the metal substrate, forming an insulator layer on the diffusion barrier layer; and forming a semiconductor layer on the insulator layer. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into a semiconductor device formed thereon. | 01-27-2011 |
20110017998 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 01-27-2011 |
20110037073 | METHODS OF FABRICATING THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME - A thin film transistor (TFT), an OLED device having the TFT and a method of fabricating the same and a method of fabricating an organic light emitting diode (OLED) display device that includes the TFT. The method of fabricating a TFT includes providing a substrate, forming a buffer layer on the substrate, forming an amorphous silicon layer pattern on the buffer layer, forming a metal layer on an entire surface of the substrate, forming a semiconductor layer by applying an electrical field to the metal layer to crystallize the amorphous silicon layer pattern, forming source and drain electrodes connected to the semiconductor layer by patterning the metal layer, forming a gate insulating layer on the entire surface of the substrate, forming a gate electrode on the gate insulating layer to correspond to the semiconductor layer and forming a protective layer on the entire surface of the substrate. | 02-17-2011 |
20110068342 | Laser Process for Minimizing Variations in Transistor Threshold Voltages - A laser method is provided for minimizing variations in transistor threshold voltages. The method supplies a wafer with a laser-crystallized active semiconductor film having a top surface with a first surface roughness. The method laser anneals the active semiconductor film, and in response to the laser annealing, melts the top surface of the active semiconductor film. The result is a top surface with a second roughness, less than the first roughness. More explicitly, the wafer active semiconductor film is crystallized using a laser with a first fluence, and then laser annealed with a second fluence, less than the first fluence. As compared with complementary metal-oxide-semiconductor field-effect (CMOSFET) thin-film transistor (TFT) structures formed in unprocessed regions of the active semiconductor film, the TFT threshold voltage standard deviation for TFTs in laser annealed portions of the active film are 60% less for n-channel and 30% less for p-channel TFTs. | 03-24-2011 |
20110068343 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - To achieve TFT having a high light-resistance characteristic with a suppressed light leak current at low cost by simplifying the manufacturing processes. The TFT basically includes: a light-shielding film formed on a glass substrate that serves as an insulating substrate; an insulating film formed on the light-shielding film; a semiconductor film formed on the insulating film; and a gate insulating film formed on the semiconductor film. Each layer of a laminate that is configured with three layers of the light-shielding film, the insulating film, and the semiconductor film is patterned simultaneously. Further, each layer of the laminate is configured with silicon or a material containing silicon. | 03-24-2011 |
20110068344 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region lying adjacent to the primary surface, an underlying doped region spaced apart from the primary surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. In another embodiment, the transistor can include a gate dielectric layer, wherein the field-effect transistor is designed to have a maximum gate voltage of approximately 20 V, a maximum drain voltage of approximately 30 V, and a figure of merit no greater than approximately 30 mΩ*nC. | 03-24-2011 |
20110084283 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor and a manufacturing method thereof are provided. An insulating pattern layer having at least one protrusion is formed on a substrate. Afterwards, at least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. Later, the spacer and the amorphous semiconductor patterns are crystallized. Subsequently, the protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. Then, a carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer. | 04-14-2011 |
20110089425 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH | 04-21-2011 |
20110089426 | Integrated Circuit, Semiconductor Device Comprising the Same, Electronic Device Having the Same, and Driving Method of the Same - An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated. | 04-21-2011 |
20110089427 | SECURITIES, CHIP MOUNTING PRODUCT, AND MANUFACTURING METHOD THEREOF - The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design. | 04-21-2011 |
20110101364 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 05-05-2011 |
20110101365 | ELECTRONIC DEVICE INCLUDING GRAPHENE THIN FILM AND METHODS OF FABRICATING THE SAME - Provided are an electronic device and methods of fabricating the same, the electronic device include a device-substrate, a stacked structure, and an electrode. The stacked structure includes a graphene thin film between a first insulator and a second insulator. The electrode is disposed over the stacked structure. | 05-05-2011 |
20110101366 | PAPER INCLUDING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Paper embedded with a semiconductor device capable of communicating wirelessly is realized, whose unevenness of a portion including the semiconductor device does not stand out and the paper is thin with a thickness of less than or equal to 130 μm. A semiconductor device is provided with a circuit portion and an antenna, and the circuit portion includes a thin film transistor. The circuit portion and the antenna are separated from a substrate used during manufacturing, and are interposed between a flexible base and a sealing layer and protected. The semiconductor device can be bent, and the thickness of the semiconductor device itself is less than or equal to 30 μm. The semiconductor device is embedded in a paper in a papermaking process. | 05-05-2011 |
20110101367 | Semiconductor Device and A Method of Manufacturing the Same - A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable III can be obtained. | 05-05-2011 |
20110121305 | THIN FILM TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME - A thin film transistor device and method of making the same are provided. The thin film transistor device includes a crystalline semiconductor layer and a patterned heavily doped semiconductor layer. The patterned heavily doped semiconductor layer includes a first heavily doped semiconductor layer and a second heavily doped semiconductor layer. The first heavily doped semiconductor layer covers a first side surface and a portion of a top surface of the crystalline semiconductor layer; the second heavily doped semiconductor layer covers a second side surface and a portion of the top surface of the crystalline semiconductor layer. | 05-26-2011 |
20110121306 | Systems and Methods for Non-Periodic Pulse Sequential Lateral Solidification - The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart. | 05-26-2011 |
20110121307 | LIQUID CRYSTAL DISPLAY DEVICE - It is an object of the present invention to provide a liquid crystal display device which has a wide viewing angle and less color-shift depending on an angle at which a display screen is seen and can display an image favorably recognized both outdoors in sunlight and dark indoors (or outdoors at night). The liquid crystal display device includes a first portion where display is performed by transmission of light and a second portion where display is performed by reflection of light. Further, a liquid crystal layer includes a liquid crystal molecule which rotates parallel to an electrode plane when a potential difference is generated between two electrodes of a liquid crystal element provided below the liquid crystal layer. | 05-26-2011 |
20110121308 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - Provided are a thin film transistor including a polycrystalline silicon layer having improved crystallinity by applying Joule heat to form stress gradient in a glass substrate that is disposed under an amorphous silicon layer from a surface to a predetermined depth of the glass substrate, thereby crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and a method of fabricating the same. The film transistor includes a glass substrate having stress gradient from an upper surface to a predetermined depth, a semiconductor layer disposed on the glass substrate, and formed of a polycrystalline silicon layer crystallized by Joule heating, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer, and electrically connected to source and drain regions of the semiconductor layer. | 05-26-2011 |
20110133198 | THIN FILM TRANSISTOR, DISPLAY DEVICE INCLUDING THE SAME AND MANUFACTURING METHOD THEREOF - A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity. | 06-09-2011 |
20110140118 | Backside stress compensation for gallium nitride or other nitride-based semiconductor devices - A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate. | 06-16-2011 |
20110156045 | CRYSTAL MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A crystal manufacturing apparatus capable of manufacturing a crystal in a desired position on a substrate is provided. A spring has one end fixed to a mount and the other end coupled to a magnetic body. The magnetic body has one end coupled to the spring and the other end coupled to a piston. A coil is wound around the magnetic body and electrically connected between a power supply circuit and a ground node (GND). The piston has a linear member inserted in a cylinder. The cylinder has a hollow columnar shape and a small hole at a bottom surface. The cylinder holds a silicon melt. A substrate is supported by an XY stage to be opposed to the small hole of the cylinder. The power supply circuit passes pulse shaped current through the coil to move the piston in an up-down direction (DR | 06-30-2011 |
20110175100 | Infrared sensor - The infrared sensor ( | 07-21-2011 |
20110198603 | THIN FILM TRANSISTOR AND METHOD OF FORMING THE SAME - Disclosed are a thin film transistor and a method of forming the thin film transistor. | 08-18-2011 |
20110198604 | FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer. | 08-18-2011 |
20110204374 | THIN FILM DIODE AND METHOD FOR FABRICATING THE SAME | 08-25-2011 |
20110215334 | PHOTOCURABLE POLYMERIC DIELECTRICS AND METHODS OF PREPARATION AND USE THEREOF - Disclosed are polymer-based dielectric compositions (e.g., formulations) and materials (e.g. films) and associated devices. The polymers generally include photocrosslinkable pendant groups; for example, the polymers can include one or more coumarin-containing pendant groups. | 09-08-2011 |
20110220904 | MASK FOR SEQUENTIAL LATERAL SOLIDIFICATION AND SEQUENTIAL LATERAL SOLIDIFICATION APPARATUS HAVING THE SAME - A mask for sequential lateral solidification (SLS) which is capable of preventing an overlapping region and a diagonal stain based on a crystallization pattern of an active layer. The mask for SLS, which moves in a first direction and selectively transmits a laser beam emitted by a laser emitting device, includes slits which are formed such that the width of a slit in the first direction is smaller than the width of the slit in a second direction, which is perpendicular to the first direction. Each of the slits is tilted by a predetermined angle with respect to the first direction. | 09-15-2011 |
20110220905 | SEMICONDUCTOR DEVICE - In an inverted staggered thin film transistor, a microcrystalline silicon film and a silicon carbide film are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the silicon carbide film is formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity. | 09-15-2011 |
20110233556 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together. | 09-29-2011 |
20110248277 | METHOD OF CRYSTALIZING AMORPHOUS SILICON LAYER, METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME, AND THIN FILM TRANSISTOR USING THE MANUFACTURING METHOD - A method of crystallizing an amorphous silicon layer, a method of manufacturing a thin film transistor using the same, and a thin film transistor using the manufacturing method, the crystallizing method including: forming an amorphous silicon layer; positioning crystallization catalyst particles on the amorphous silicon layer to be separated from each other; selectively removing the crystallization catalyst particles from a portion of the amorphous silicon layer; and crystallizing the amorphous silicon layer by a heat treatment. | 10-13-2011 |
20110248278 | SINGLE SCAN IRRADIATION FOR CRYSTALLIZATION OF THIN FILMS - A method of processing a polycrystalline film on a substrate includes generating laser pulses, directing the laser pulses through a mask to generate patterned laser beams, each having a length l′, a width w′, and a spacing between adjacent beams d′; irradiating a region of the film with the patterned beams, said beams having an intensity sufficient to melt and to induce crystallization of the irradiated portion of the film, wherein the film region is irradiated n times; and after irradiation of each film portion, translating the film and/or the mask, in the x- and y-directions. The distance of translation in the y-direction is about l′/n−δ, where δ is a value selected to overlap the beamlets from one irradiation step to the next. The distance of translation in the x-direction is selected such that the film is moved a distance of about λ′ after n irradiations, where λ′=w′+d′. | 10-13-2011 |
20110254010 | Wide Band-Gap MOSFETs Having a Heterojunction Under Gate Trenches Thereof and Related Methods of Forming Such Devices - Semiconductor switching devices include a first wide band-gap semiconductor layer having a first conductivity type. First and second wide band-gap well regions that have a second conductivity type that is opposite the first conductivity type are provided on the first wide band-gap semiconductor layer. A non-wide band-gap semiconductor layer having the second conductivity type is provided on the first wide band-gap semiconductor layer. First and second wide band-gap source/drain regions that have the first conductivity type are provided on the first wide band-gap well region. A gate insulation layer is provided on the non-wide band-gap semiconductor layer, and a gate electrode is provided on the gate insulation layer. | 10-20-2011 |
20110272700 | THIN FILM TRANSISTOR, ELECTRONIC DEVICE HAVING THE SAME, AND METHOD FOR MANUFACTURING THE SAME - An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode. Expansion or shrinkage of a glass substrate during the heat treatment can be prevented from affecting misalignment in patterning since the gate insulating film and the semiconductor film are simultaneously processed into element shapes after the heat treatment. | 11-10-2011 |
20110272701 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor. | 11-10-2011 |
20110278580 | METHODOLOGY FOR FABRICATING ISOTROPICALLY SOURCE REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. | 11-17-2011 |
20110278581 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n | 11-17-2011 |
20110278582 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having favorable electric characteristics with high productivity is provided. A first microcrystalline semiconductor film is formed over an oxide insulating film under a first condition that mixed phase grains with high crystallinity are formed at a low particle density. After that, a second microcrystalline semiconductor film is stacked over the first microcrystalline semiconductor film under a second condition that a space between the mixed phase grains are filled by the crystal growth of the mixed phase grains of the first microcrystalline semiconductor film. | 11-17-2011 |
20110284859 | Growth of group III nitride- based structures and integration with conventional CMOS processing tools - A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools. | 11-24-2011 |
20110284860 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A method for producing a semiconductor device includes a step of forming a first insulation film, a step of forming a separation layer in a base layer, a step of forming a light-blocking film on the surface of the first insulation film, a step of forming a second insulation film such that the light-blocking film is covered, a step of affixing the base layer provided with the light-blocking film to a substrate, a step of separating and removing along the separation layer a portion of the base layer affixed to the substrate, and a step of forming a semiconductor layer such that at least a portion thereof overlaps with the light-blocking film. | 11-24-2011 |
20110291100 | DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material. | 12-01-2011 |
20110297949 | Organic light emitting display and method of fabricating the same - An organic light emitting display and method of fabricating thereof, the display including a substrate including a first thin film transistor region and a second thin film transistor region; a buffer layer on the substrate; a first and a second semiconductor layer on the buffer layer; a gate insulating layer on the substrate; gate electrodes on the gate insulating layer and corresponding to the first semiconductor layer and the second semiconductor layer, respectively; source/drain electrodes insulated from the gate electrode and being connected to the first semiconductor layer and the second semiconductor layer, respectively; an insulating layer on the substrate; a first electrode connected to the source/drain electrode electrically connected to the first semiconductor layer; an organic layer on the first electrode; and a second electrode on the organic layer, wherein portions of the buffer layer corresponding to a source/drain region of the first semiconductor layer include a metal catalyst. | 12-08-2011 |
20110297950 | CRYSTALLINE SEMICONDUCTOR FILM MANUFACTURING METHOD, SUBSTRATE COATED WITH CRYSTALLINE SEMICONDUCTOR FILM, AND THIN-FILM TRANSISTOR - To provide a method of manufacturing a crystalline semiconductor film having a crystal structure with favorable in-plane uniformity. The method includes: irradiating an amorphous semiconductor film with a continuous-wave laser beam to increase a temperature of the amorphous semiconductor film to a range of 600° C. to 1100° C., the continuous-wave laser beam having a light intensity distribution continuously convex upward on each of major and minor axes; crystallizing the amorphous semiconductor film at the temperature increased to the range of 600° C. to 1100° C.; and increasing a crystal grain size of the crystallized amorphous semiconductor film, as a result of an increase in an in-plane temperature of the crystallized amorphous film to a range of 1100° C. to 1414° C. by latent heat released in the crystallizing of the amorphous semiconductor film. | 12-08-2011 |
20110315992 | PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION OF CRYSTALLINE GERMANIUM - In a method of depositing a crystalline germanium layer on a substrate, a substrate is placed in the process zone comprising a pair of process electrodes. In a deposition stage, a crystalline germanium layer is deposited on the substrate by introducing a deposition gas comprising a germanium-containing gas into the process zone, and forming a capacitively coupled plasma of the deposition gas by coupling energy to the process electrodes. In a subsequent treatment stage, the deposited crystalline germanium layer is treated by exposing the crystalline germanium layer to an energized treatment gas or by annealing the layer. | 12-29-2011 |
20120001190 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING SAME - The invention provides a thin film transistor that can improve its operating speed by improving crystallinity near a bottom surface of a channel layer. Of laser light irradiated onto an amorphous silicon layer, light transmitted through the amorphous silicon layer is absorbed by a gate electrode | 01-05-2012 |
20120018730 | STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES - Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. | 01-26-2012 |
20120025196 | ORGANIC THIN FILM TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT - An organic thin film transistor includes an organic semiconductor layer, a source electrode and a drain electrode which are separated from each other and are individually in contact with the organic semiconductor layer, a gate insulating film which is in contact with the organic semiconductor layer between the source and drain electrodes, and a gate electrode which is opposed to the organic semiconductor layer and is in contact with the gate insulating film. In the organic thin film transistor, a high-concentration region of the organic semiconductor layer which is located near the source electrode has an impurity concentration set higher than an impurity concentration of a low-concentration region of the organic semiconductor layer, the low-concentration region being located near the gate electrode in the thickness direction of the organic semiconductor layer between the source and drain electrodes. | 02-02-2012 |
20120037915 | Method of Making an Organic Thin Film Transistor - A method of forming an organic thin film transistor the method comprising:
| 02-16-2012 |
20120043549 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element. | 02-23-2012 |
20120056187 | METHOD OF FORMING POLYCRYSTALLINE SILICON LAYER, AND THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE POLYCRYSTALLINE SILICON LAYER - A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor. | 03-08-2012 |
20120074418 | SEMICONDUCTOR DEVICE - NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT. | 03-29-2012 |
20120091461 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor display substrate and a method of manufacturing the same are provided. The thin film transistor substrate includes a gate electrode formed on a display substrate, an active layer formed on the gate electrode to overlap with the gate electrode and including polycrystalline silicon, a first ohmic contact layer formed on the active layer, a second ohmic contact layer formed on the first ohmic contact layer, and a source electrode and a drain electrode each formed on the second ohmic contact layer. | 04-19-2012 |
20120091462 | TFT MONOS OR SONOS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N | 04-19-2012 |
20120097962 | POLYSILICON THIN FILM TRANSISTOR HAVING COPPER BOTTOM GATE STRUCTURE AND METHOD OF MAKING THE SAME - Provided is a polysilicon thin film transistor having a bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed layer that is formed in the same pattern as that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; the gate electrode that is formed of copper on the seed layer; a planarization layer that is formed on the transparent insulation substrate in the same level as that of the gate electrode in the vicinity of the gate electrode; a gate insulation film formed on the upper portion of the gate electrode and the planarization layer, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film. | 04-26-2012 |
20120097963 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel foaming range would be formed on respective crystal regions extending from the plurality of convex end portions. A semiconductor region adjacent to the channel forming region is eliminated. | 04-26-2012 |
20120097964 | Semiconductor Device and Manufacturing Method Thereof - An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate, a gate insulating film over the gate electrode, a first source or drain electrode over the gate insulating film, an island-shaped semiconductor film over the first source or drain electrode, and a second source or drain electrode over the island-shaped semiconductor film and the first source or drain electrode. Further, the second source or drain electrode is in contact with the first source or drain electrode, and the island-shaped semiconductor film is sandwiched between the first source or drain electrode and the second source or drain electrode. Moreover, the present invention relates to a manufacturing method of the semiconductor device. | 04-26-2012 |
20120104402 | ARCHITECTURE OF ANALOG BUFFER CIRCUIT - In one aspect of the invention, an analog buffer circuit includes a p-channel field effect transistor (PTFT) and an n-channel field effect transistor (NTFT). Each of the PTFT and NTFT has a source region and a drain region defining a channel region therebetween, formed on a substrate such that the drain regions of the PTFT and the NTFT are in substantial contact with each other, a gate layer formed over and insulated from the corresponding channel region, a source electrode insulated from the gate layer and electrically connected to the corresponding source region, and a common drain electrode insulated from the gate layer and the source electrode, and is electrically connected to the drain regions of both the PTFT and the NTFT through a via defined over the depletion region. | 05-03-2012 |
20120104403 | THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THE SAME - An object of the present invention is to provide a thin film transistor having a gate insulating film for suppressing a shift amount of a threshold voltage generated by use under a high temperature environment. In a thin film transistor having a channel layer made of microcrystalline silicon, a gate insulating film | 05-03-2012 |
20120132919 | SEMICONDUCTOR DEVICE - It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region. | 05-31-2012 |
20120138944 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film. | 06-07-2012 |
20120153291 | Vertical Memory Devices Including Indium And/Or Gallium Channel Doping - A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed. | 06-21-2012 |
20120161144 | POLYSILICON THIN FILM TRANSISTOR HAVING TRENCH TYPE COPPER BOTTOM GATE STRUCTURE AND METHOD OF MAKING THE SAME - Provided is a polysilicon thin film transistor having a trench type bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed pattern that is formed in a pattern corresponding to that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; a trench type guide portion having a trench type contact window in which an upper portion of the seed pattern is exposed; the gate electrode that is formed by electrodepositing copper on a trench of the exposed seed pattern; a gate insulation film formed on the upper portions of the gate electrode and the trench type guide portion, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film. | 06-28-2012 |
20120161145 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor. | 06-28-2012 |
20120175623 | TRANSISTOR INCLUDING MULTIPLE REENTRANT PROFILES - A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer. | 07-12-2012 |
20120175624 | IMPLEMENTING VERTICAL SIGNAL REPEATER TRANSISTORS UTILIZING WIRE VIAS AS GATE NODES - A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor. | 07-12-2012 |
20120175625 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the steps of: forming a base insulating over a substrate; forming an oxide semiconductor film over the base insulating film; forming a conductive film over the oxide semiconductor film; processing the conductive film to form a source electrode and a drain electrode; processing the oxide semiconductor film; forming a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and forming a gate electrode over the gate insulating film. The aforementioned manufacturing method allows the formation of a transistor in which a side surface of the oxide semiconductor film is not in direct contact with bottom surfaces of the source electrode and the drain electrode, which contributes to the extremely small leak current of the transistor. | 07-12-2012 |
20120187410 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate. | 07-26-2012 |
20120193633 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate ( | 08-02-2012 |
20120199840 | SEMICONDUCTOR DEVICE HAVING A PIXEL MATRIX CIRCUIT THAT INCLUDES A PIXEL TFT AND A STORAGE CAPACITOR - In a CMOS circuit formed on a substrate | 08-09-2012 |
20120205658 | SEMICONDUCTOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT. | 08-16-2012 |
20120223314 | Solution-Processed High Mobility Inorganic Thin-Film Transistors - Thin film transistor devices comprising a dielectric component and an inorganic semiconductor component coupled thereto, wherein said coupled inorganic semiconductor component is obtainable by a process that comprises contact of said dielectric component and a fluid medium comprising said inorganic semiconductor component. | 09-06-2012 |
20120228622 | LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING THEREOF AND ELECTRONIC APPLIANCE - An object of the invention is to provide a method for manufacturing a light emitting device capable of reducing deterioration of elements due to electrostatic charge caused in manufacturing the light emitting device. Another object of the invention is to provide a light emitting device in which defects due to the deterioration of elements caused by the electrostatic charge are reduced. The method for manufacturing the light emitting device includes a step of forming a top-gate type transistor for driving a light emitting element. In the step of forming the top-gate type transistor, when processing a semiconductor layer, a first grid-like semiconductor layer extending in rows and columns is formed over a substrate. The plurality of second island-like semiconductor layers are formed between the first semiconductor layer. The plurality of second island-like second semiconductor layers serve as an active layer of the transistor. | 09-13-2012 |
20120235152 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions. | 09-20-2012 |
20120241749 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CIRCUIT MADE FROM SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized After the crystallization, a patterning step is carried out to form an active layer with a desired shape. The present invention is also characterized by forming a semiconductor film through a sputtering method, subsequently forming an insulating film. Next, the semiconductor film is crystallized through the insulating film, so that a crystalline semiconductor film is formed. According this structure, it is possible to obtain a thin film transistor with a good electronic property and a high reliability in a safe processing environment. | 09-27-2012 |
20120261669 | PHOTO DETECTOR CONSISTING OF TUNNELING FIELD-EFFECT TRANSISTORS AND THE MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors. | 10-18-2012 |
20120267633 | METHOD FOR MAKING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS OBTAINED BY THE METHOD, METHOD FOR MAKING THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE OBTAINED BY THE METHOD, AND METHOD FOR MAKING DISPLAY APPARATUS AND DISPLAY APPARATUS OBTAINED BY THE METHOD - A semiconductor apparatus having a substrate and a laminate structure formed on the substrate, the laminate structure including an insulating film made of a metal oxide and a semiconductor thin film, both the insulating film and the semiconductor thin film being crystallized. | 10-25-2012 |
20120273790 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming an amorphous semiconductor film on a substrate. The method further includes annealing the amorphous semiconductor film by irradiating the substrate with a microwave to form a polycrystalline semiconductor film from the amorphous semiconductor film. The method further includes forming a transistor whose channel is the polycrystalline semiconductor film. | 11-01-2012 |
20120273791 | METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME - A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode. | 11-01-2012 |
20120286279 | THIN FILM TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - A thin film transistor device includes a first conductivity type thin film transistor and a second conductivity type thin film transistor. The first conductivity type thin film transistor includes a first patterned doped layer, a first gate electrode, a first source electrode, a first drain electrode and a first semiconductor pattern. The second conductivity type thin film transistor includes a second patterned doped layer, a second gate electrode, a second source electrode, a second drain electrode and a second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern form a patterned semiconductor layer. The first patterned doped layer is disposed under the first semiconductor pattern, and the second patterned doped layer is disposed on the second semiconductor pattern. | 11-15-2012 |
20120299005 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel that extends from a substrate in a vertical direction and includes a first portion including an impurity doped region and a second portion disposed under the first portion; and a plurality of memory cells and a selection transistor that are stacked over the substrate along the channel, where the impurity doped region includes a second impurity doped region that forms a side surface and an upper surface of the first portion and a first impurity doped region that covers the second impurity doped region, and a bandgap energy of the second impurity doped region is lower than a bandgap energy of the first impurity doped region. | 11-29-2012 |
20120305928 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE REGIONS OF CMOS TRANSISTORS - A Field Effect Transistor (FET) device includes a gate stack formed over a channel region, a source region adjacent to the channel region, wherein a portion of a boundary between the source region and the channel region is defined along a plane defined by a sidewall of the gate stack, a drain region adjacent to the channel region, a portion of the drain region arranged below the gate stack, a native oxide layer disposed over a portion of the source region, along sidewalls of the gate stack, and over a portion of the drain region, a spacer arranged over a portion of the native oxide layer above the source region and the drain region and along the native oxide layer along the sidewalls of the gate stack. | 12-06-2012 |
20120305929 | BEOL COMPATIBLE FET STRUCTRURE - This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration. | 12-06-2012 |
20120313103 | RADIOACTIVE-RAY IMAGING APPARATUS, RADIOACTIVE-RAY IMAGING DISPLAY SYSTEM AND TRANSISTOR - Disclosed herein is a transistor including: a semiconductor layer; a first gate insulation film and a first interlayer insulation film which are provided on a specific surface side of the semiconductor layer; a first gate electrode provided at a location between the first gate insulation film and the first interlayer insulation film; an insulation film provided on the other surface side of the semiconductor layer; source and drain electrodes provided by being electrically connected to the semiconductor layer; and a shield electrode layer provided in such a way that at least portions of the shield electrode layer face edges of the first gate electrode, wherein at least one of the first gate insulation film, the first interlayer insulation film and the insulation film include a silicon-oxide film. | 12-13-2012 |
20120319120 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The disclosure involves a semiconductor device and a manufacturing method thereof. First, a dielectric layer and a stack comprising a Si layer and at least one SiGe layer located on the Si layer are formed in sequence on a substrate. Then the stack and the dielectric layer are patterned to form a dummy gate and a gate dielectric layer, respectively. Next, sidewall spacers are formed on opposite sides of the dummy gate, and source and drain regions with embedded SiGe are formed. Then, the dummy gate is removed to form an opening, in which a gate material such as metal is filled. In RMG techniques, by adopting the stack consisting of Si and SiGe layers as a dummy gate, the method can further increase the compressive stress in the channel of a MOS device and thus improve carrier mobility as compared to traditional polysilicon dummy gate process. | 12-20-2012 |
20120319121 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES, AND CORRESPONDING STRUCTURE - A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes. | 12-20-2012 |
20120326155 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET. | 12-27-2012 |
20130001574 | FIELD TRANSISTOR STRUCTURE MANUFACTURED USING GATE LAST PROCESS - According to embodiments of the invention, a field transistor structure is provided. The field transistor structure includes a semiconductor substrate, a metal gate, a polycrystalline silicon (polysilicon) layer, and first and second metal portions. The polysilicon layer has first, second, third, and fourth sides and is disposed between the semiconductor substrate on the first side and the metal gate on the second side. The polysilicon layer is also disposed between the first and second metal portions on the third and fourth sides. According to some embodiments of the present invention, the field transistor structure may also include a thin metal layer disposed between the polysilicon layer and the semiconductor substrate. The thin metal layer may be electronically coupled to each of the first and second metal portions. | 01-03-2013 |
20130001575 | METHODS FOR STRESSING TRANSISTOR CHANNELS OF A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE - The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. | 01-03-2013 |
20130001576 | SEMICONDUCTOR DEVICE INCLUDING METAL SILICIDE LAYER AND METHOD FOR MANUFACTURING THE SAME - A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon. | 01-03-2013 |
20130020576 | SHIELDED GATE MOSFET-SCHOTTKY RECTIFIER-DIODE INTEGRATED CIRCUITS WITH TRENCHED CONTACT STRUCTURES - A trench shielded gate MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage, lower cost and improved performance. The present semiconductor device achieve low Vf and reverse leakage current for embedded Schottky rectifier, having over-voltage protection and avalanche protection between gate and source and between gate and drain. | 01-24-2013 |
20130020577 | MOSFET-SCHOTTKY RECTIFIER-DIODE INTEGRATED CIRCUITS WITH TRENCH CONTACT STRUCTURES - A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode. | 01-24-2013 |
20130020578 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region. | 01-24-2013 |
20130026479 | SEMICONDUCTOR THIN-FILM FORMING METHOD, SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE, AND THIN-FILM SUBSTRATE - A semiconductor thin-film manufacturing method includes: forming, above a substrate, an amorphous silicon film (precursor film) having a photoluminescence (PL) intensity greater than or equal to 0.65 when photon energy is 1.1 eV in a PL spectrum normalized to have a maximum PL intensity of 1; and annealing the amorphous silicon film to form a crystalline silicon film. | 01-31-2013 |
20130037816 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device ( | 02-14-2013 |
20130049000 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device and method of making the same are provided. The method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased. | 02-28-2013 |
20130056742 | MICROCRYSTALLINE SILICON FILM, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive. | 03-07-2013 |
20130075741 | Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers - A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance. | 03-28-2013 |
20130075742 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element. | 03-28-2013 |
20130075743 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer. | 03-28-2013 |
20130082268 | IMPLEMENTING VERTICAL SIGNAL REPEATER TRANSISTORS UTILIZING WIRE VIAS AS GATE NODES - A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor. | 04-04-2013 |
20130087799 | BIPOLAR TRANSISTOR MANUFACTURING METHOD, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT - Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate ( | 04-11-2013 |
20130105807 | SYSTEMS AND METHODS FOR NON-PERIODIC PULSE PARTIAL MELT FILM PROCESSING | 05-02-2013 |
20130112982 | METHOD FOR FORMING NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator. A second source/drain region is formed in a top portion of the fin. Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern. Other aspects are provided herein. | 05-09-2013 |
20130119391 | THIN-FILM TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR DEVICE - A thin-film transistor device includes: a gate electrode above a substrate; a gate insulating film on the gate electrode; a crystalline silicon thin film including a channel region which is provided on the gate insulating film; semiconductor films on at least the channel region; an insulating film made of an organic material which is provided over the channel region and above the semiconductor films; a source electrode over at least an end portion of the insulating film; and a drain electrode over at least the other end portion of the insulating film and facing the source electrode. The semiconductor films include at least a first semiconductor film and a second semiconductor film provided on the first semiconductor film. A relationship E | 05-16-2013 |
20130126880 | Method Of Forming Polysilicon, Thin Film Transistor Using The Polysilicon, And Method Of Fabricating The Thin Film Transistor - A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s). | 05-23-2013 |
20130126881 | IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS - A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. | 05-23-2013 |
20130134429 | THIN-FILM TRANSISTOR AND THIN-FILM TRANSISTOR MANUFACTURING METHOD - A thin-film transistor according to the present disclosure includes: a substrate; a gate electrode above the substrate; a gate insulating layer on the gate electrode; a channel layer on the gate insulating layer which is located on the gate electrode; a source electrode above the channel layer; a drain electrode above the channel layer; and a barrier layer between the channel layer and the source electrode and between the channel layer and the drain electrode. Each of the source electrode and the drain electrode is made of a metal including copper, and the barrier layer contains nitrogen and molybdenum and has a density greater than 7.5 g/cm | 05-30-2013 |
20130140576 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction. | 06-06-2013 |
20130146883 | SEMICONDUCTOR THIN FILM, THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND MANUFACTURING EQUIPMENT OF SEMICONDUCTOR THIN FILM - A method for manufacturing a semiconductor thin film is provided which can form its crystal grains having a uniform direction of crystal growth and being large in size and a manufacturing equipment using the above method, and a method for manufacturing a thin film transistor. In the above method, by applying an energy beam partially intercepted by a light shielding element, melt and re-crystallization occur with a light-shielded region as a starting point. The irradiation of the beam gives energy to the light-shielded region of the silicon thin film so that melt and re-crystallization occur with the light-shielded region as the starting point and so that a local temperature gradient in the light-shielded region is made to be 1200° C./μm or more. In the manufacturing method, a resolution of an optical system used to apply the energy beam is preferably 4 μm or less. | 06-13-2013 |
20130153913 | Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor - A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost. | 06-20-2013 |
20130161629 | ZERO SHRINKAGE SMOOTH INTERFACE OXY-NITRIDE AND OXY-AMORPHOUS-SILICON STACKS FOR 3D MEMORY VERTICAL GATE APPLICATION - Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550° C.; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600° C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700° C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods. | 06-27-2013 |
20130161630 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THIN-FILM SEMICONDUCTOR DEVICE - A method for fabricating a thin-film semiconductor device according to the present disclosure includes: preparing a glass substrate; forming, above the glass substrate, an undercoat layer including a nitride film; forming a barrier layer above the undercoat layer; forming a molybdenum metal layer above the barrier layer; forming a gate electrode from the molybdenum metal layer; forming a gate insulating film above the gate electrode; forming a non-crystalline silicon layer as a non-crystalline semiconductor layer above the gate insulating film; forming a polycrystalline semiconductor layer including a polysilicon layer by annealing the non-crystalline silicon layer using a continuous-wave (CW) laser, the non-crystalline silicon layer being crystallized by the annealing; and forming a source electrode and a drain electrode above the polysilicon layer. Part of the barrier layer changes into a layer including oxygen atoms as a major component by the annealing when forming the polysilicon layer. | 06-27-2013 |
20130168683 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; a semiconductor layer disposed on the gate insulating layer; and a source electrode and a drain electrode disposed on a portion of the semiconductor layer, wherein the semiconductor layer includes an ohmic contact layer, a channel layer, and a buffer layer, the buffer layer disposed between the channel layer and the ohmic contact layer, and the source electrode and the drain electrode contact a surface of the ohmic contact layer. | 07-04-2013 |
20130175534 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are disclosed. In one embodiment, the semiconductor device includes a substrate, a first silicon nitride layer formed over the substrate, a first silicon oxide layer formed directly on the first silicon nitride layer and having a thickness of about 1000 Å or less, and a hydrogenated polycrystalline silicon layer formed directly on the first silicon oxide layer. | 07-11-2013 |
20130175535 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device ( | 07-11-2013 |
20130187166 | LIGHT-EMITTING DEVICE - According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor. | 07-25-2013 |
20130200383 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD FOR THE SAME - The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method. | 08-08-2013 |
20130200384 | ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL - A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH | 08-08-2013 |
20130221360 | THIN FILM TRANSISTOR HAVING ATOMIC-DOPING LAYER - A thin film transistor includes a substrate, a source electrode and a drain electrode formed on the substrate, a channel layer formed between the source electrode and the drain electrode, an insulative layer covering the channel layer and a gate electrode formed on the insulative layer. An atomic-doping layer is formed in the channel layer. The atomic-doping layer is delta-doping with no more than one layer of atom. | 08-29-2013 |
20130228785 | LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE - An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support | 09-05-2013 |
20130248871 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of is the first region is larger than an effective work function of the second region. | 09-26-2013 |
20130256675 | Method for Consuming Silicon Nanoparticle Film Oxidation - A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing. | 10-03-2013 |
20130270568 | THIN FILM TRANSISTOR - Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole. | 10-17-2013 |
20130270569 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor. | 10-17-2013 |
20130277677 | METHOD FOR FORMING POLYCRYSTALLINE FILM, POLYCRYSTALLINE FILM AND THIN FILM TRANSISTOR FABRICATED FROM THE POLYCRYSTALLINE FILM - A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer. | 10-24-2013 |
20130277678 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A thin-film semiconductor device manufacturing method according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating film above the substrate; forming an amorphous film (amorphous silicon film) above the substrate; forming a crystalline film (crystalline silicon film) including a first crystal and a second crystal, by crystallizing the amorphous film, the first crystal (i) containing subgrains formed with different crystal orientations in a single crystal and (ii) including a subgrain boundary formed by plural crystal planes between the subgrains, the second crystal having an average crystal grain size smaller than an average crystal grain size of the first crystal; thinning the crystalline film; and forming a source electrode and a drain electrode above the substrate. | 10-24-2013 |
20130299834 | BURIED CHANNEL TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device may include a plurality of memory cells. The memory cells may be formed with respective fin shaped active regions with respective recesses formed therein. Thicknesses of the fins may be made relatively thicker around the recesses, such as by selective epitaxial growth around the recesses. The additional thicknesses may be asymmetrical so that portions of the fin on one side are larger than an opposite side. Related methods and systems are also disclosed. | 11-14-2013 |
20130299835 | Semiconductor Device with an Integrated Poly-Diode - A field effect semiconductor device includes a semiconductor body having a main horizontal surface and a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the main horizontal surface, an insulating layer arranged on the main horizontal surface, and a first metallization arranged on the insulating layer. The first and second semiconductor regions form a pn-junction. The semiconductor body further has a deep trench extending from the main horizontal surface vertically below the pn-junction and including a conductive region insulated from the first semiconductor region and the second semiconductor region, and a narrow trench including a polycrystalline semiconductor region extending from the first metallization, through the insulating layer and at least to the conductive region. A vertical poly-diode structure including a horizontally extending pn-junction is arranged at least partly in the narrow trench. | 11-14-2013 |
20130299836 | ILLUMINATION APPARATUS - A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate. | 11-14-2013 |
20130299837 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a thin-film semiconductor device, a semiconductor layer has a bandgap energy of 1.6 eV or less, an insulating layer formed above the semiconductor layer includes: a first insulating layer region placed outside of a first contact opening and above one end of a gate electrode; a second insulating layer region placed outside of a second contact opening and above the other end of the gate electrode which opposes the one end; and a third insulating layer region being rectangular and placed between the first contact opening and the second contact opening. | 11-14-2013 |
20130306975 | Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-Layer Charge-Trapping Region - Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed | 11-21-2013 |
20140001477 | SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH DRAIN AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF | 01-02-2014 |
20140014964 | Semiconductor Device and Method of Manufacturing the Same - In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage. | 01-16-2014 |
20140021477 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 01-23-2014 |
20140034955 | Nano-MOS Devices and Method of Making - The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance. | 02-06-2014 |
20140034956 | Asymmetric Gate MOS Device and Method of Making - An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. | 02-06-2014 |
20140070222 | THIN-FILM TRANSISTOR AND SOLID-STATE IMAGING APPARATUS - According to one embodiment, a thin-film transistor includes a thin-film semiconductor layer, a first gate electrode provided on the thin-film semiconductor layer through a first gate insulation film without overlapping an edge portion of the thin-film semiconductor layer, a source layer connected to the thin-film semiconductor layer, and a drain layer connected to the thin-film semiconductor layer. | 03-13-2014 |
20140070223 | PLANARIZED SEMICONDUCTOR PARTICLES POSITIONED ON A SUBSTRATE - A device and method of fabricating a device in the form of an array of planarized particles of single crystal silicon or poly crystal silicon wherein the planar surfaces of the particles is used to fabricate an array of electronic devices. This is particularly useful in the manufacture of large displays where single crystal high speed devices are required. The planar surfaces of the array of devices are coplanar when the array is fabricated on a planar substrate. | 03-13-2014 |
20140110718 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND MANUFACTURING METHOD THEREOF - A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings. | 04-24-2014 |
20140117367 | DEVICES, STRUCTURES, AND METHODS USING SELF-ALIGNED RESISTIVE SOURCE EXTENSIONS - Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region. | 05-01-2014 |
20140117368 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 05-01-2014 |
20140131716 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate. | 05-15-2014 |
20140151707 | LIGHT EMITTING DEVICE - The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced. | 06-05-2014 |
20140159044 | THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR - A method for manufacturing a thin-film transistor, includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; removing at least a portion of a region of an altered layer, the region contacting the semiconductor layer, the altered layer being a surface layer of the protective layer that is altered by the dry etching; and forming a passivation layer having a major component identical to a major component of the protective layer so as to contact the semiconductor layer in a region in which the altered layer has been removed. | 06-12-2014 |
20140167055 | METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT - Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor. | 06-19-2014 |
20140197416 | MEMORIES AND METHODS OF FORMING THIN-FILM TRANSISTORS USING HYDROGEN PLASMA DOPING - Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled. | 07-17-2014 |
20140209911 | THIN-FILM TRANSISTOR DEVICE - A thin-film transistor device includes a gate electrode formed above a substrate, a gate insulating film formed on the gate electrode, a crystalline silicon thin film that is formed above the gate insulating film and has a channel region, an amorphous silicon thin film formed on the crystalline silicon thin film, and a source electrode and a drain electrode that are formed above the channel region, and the crystalline silicon thin film has a half-width of a Raman band corresponding to a phonon mode specific to the crystalline silicon thin film of 5.0 or more and less than 6.0 cm | 07-31-2014 |
20140217412 | DISPLAY DEVICE - A display device includes a display area and a terminal area formed outside the display area. The display area has a plurality of scanning lines and a plurality of video signal lines that cross the scanning lines. The terminal area has a first terminal having a semiconductor chip connected thereto, a first line, a second line, and an inspection thin-film transistor. The inspection thin-film transistor has a gate electrode connected to the first line, a source electrode connected to the second line, and a drain electrode. The first terminal is connected to any of the plurality of scanning lines and the plurality of video signal lines. | 08-07-2014 |
20140217413 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer. | 08-07-2014 |
20140231809 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE REGIONS OF CMOS TRANSISTORS - A Field Effect Transistor device includes a buried oxide layer, a silicon layer above the buried oxide layer, an isotropically recessed source region, and a gate stack comprising a gate dielectric, a conductive material, and a spacer. | 08-21-2014 |
20140231810 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor, includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etch stopper disposed on a channel of the semiconductor; a source electrode disposed on the semiconductor; and a drain electrode disposed on the semiconductor. At least one of the source electrode and the drain electrode does not overlap with the etch stopper. At least one dimension of the etch stopper and the channel of the semiconductor are substantially the same. | 08-21-2014 |
20140231811 | SEMICONDUCTOR DEVICE STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND PIXEL STRUCTURE USING THE SAME - A semiconductor device structure is provided. The semiconductor device structure may include a substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The semiconductor layer is adjacent to the first dielectric layer or the second dielectric layer. The semiconductor layer is disposed on the first dielectric layer or the second dielectric layer. The first conductive layer is adjacent to the first dielectric layer or the second dielectric layer. The second conductive layer is disposed on the first dielectric layer or the second dielectric layer. The effective Young's modulus of the second dielectric layer may be smaller than the Young's modulus of the first dielectric layer. | 08-21-2014 |
20140231812 | SUBSTRATE HAVING THIN FILM AND METHOD OF THIN FILM FORMATION - A method of thin film formation includes: preparing a substrate; forming a thin film above the substrate; and crystallizing the thin film by irradiating the thin film with a light beam, in which the crystallizing includes steps of: crystallizing the thin film in a first region into a first crystalline thin film by irradiating the first region while scanning a first light beam relative to the substrate, the first region including at least one of: edge portions of the substrate; and a region through which a cutting line passes when the substrate is cut; and subsequently crystallizing the thin film in a second region into a second crystalline thin film by irradiating at least the second region while scanning a second light beam relative to the substrate, and the thin film has a higher absorption ratio of the second light beam than that of the first crystalline thin film. | 08-21-2014 |
20140231813 | THIN-FILM DEVICE, THIN-FILM DEVICE ARRAY, AND METHOD OF MANUFACTURING THIN-FILM DEVICE - A thin-film device includes: a first device unit having a first gate electrode and a first crystalline silicon thin film located opposite to the first gate electrode; and a second device unit having a second gate electrode and a second crystalline silicon thin film located opposite to the second gate electrode. The first crystalline silicon thin film includes a strip-shaped first area and a second area smaller than the strip-shaped first area in average grain size. The first device unit has, as a channel, at least a part of the strip-shaped first area. The second silicon thin film includes a second crystalline area smaller than the strip-shaped first area in average grain size. The second device unit has the second crystalline area as a channel. The strip-shaped first area includes crystal grains in contact with the second area on each side of the strip-shaped first area. | 08-21-2014 |
20140239303 | SEMICONDUCTOR DEVICES INCLUDING WISX AND METHODS OF FABRICATION - Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices. | 08-28-2014 |
20140252363 | THREE DIMENSIONAL MEMORY STRUCTURE - A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET. | 09-11-2014 |
20140264352 | MASK LAYER AND METHOD OF FORMATION - A semiconductor device includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed over the first semiconductor layer and includes a recess in a vertical direction towards the first semiconductor layer. The third semiconductor layer is formed in the recess of the second semiconductor layer and includes a seam or void in the recess. | 09-18-2014 |
20140264353 | 3D MEMORY ARRAY INCLUDING CRYSTALLIZED CHANNELS - A method for manufacturing a memory device includes forming a plurality of active layers alternating with insulating layers on a substrate where the active layers include an active material, etching the active layers and insulating layers to define a plurality of stacks of active strips, and after the etching, causing crystal growth in the active strips. The substrate can have a single crystalline surface with a crystal structure orientation, and the crystal growth in the active material can form crystallized material having the crystal structure orientation of the substrate at least near side surfaces of the active strips. Causing crystal growth includes depositing a seeding layer over the plurality of stacks and the substrate, where the seeding layer is in contact with the side surfaces of the active strips, and in contact with the substrate. The method can include, after causing crystal growth, removing the seeding layer. | 09-18-2014 |
20140264354 | BUFFER LAYERS FOR METAL OXIDE SEMICONDUCTORS FOR TFT - The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level. | 09-18-2014 |
20140284606 | METHOD OF FABRICATING PIXEL STRUCTURE AND PIXEL STRUCTURE THEREOF - A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided. | 09-25-2014 |
20140284607 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this embodiment, a mask material is formed above a film to be processed, and a plurality of sacrifice films are formed above the mask material, each of the sacrifice films having a columnar shape. Then, a sidewall film is formed on a sidewall of the sacrifice films, and then the sacrifice films are removed. Thereafter, the sidewall films are caused to flow. In addition, a plurality of holes are formed in the mask material using the sidewall film as a mask. Then, isotropic etching is performed for the mask material to etch back the sidewall of the mask material with respect to a sidewall of the sidewall film by a first distance. Thereafter, a deposition layer is deposited inside the plurality of holes to close an opening of the plurality of holes with the deposition layer. Anisotropic etching is conducted to remove the deposition layer in the opening. | 09-25-2014 |
20140299882 | INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR - At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure. | 10-09-2014 |
20140299883 | PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR - A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer. | 10-09-2014 |
20140306225 | THIN FILM TRANSISTOR AND SHIFT REGISTER - Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes. | 10-16-2014 |
20140312349 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF AND ARRAY SUBSTRATE INCLUDING THE THIN FILM TRANSISTOR - An embodiment of the present invention provides a thin film transistor and a manufacturing method thereof and an array substrate comprising the thin film transistor. The method comprises: depositing an amorphous layer on a substrate, and patterning the amorphous layer so as to form an active layer comprising a source region, a drain region and a channel region; forming a gate insulating layer and a gate electrode above the channel region; depositing an induction metal layer on the substrate on which the gate electrode is formed; doping impurity into the source region and the drain region by an ion implanting process and bombarding part of the induction metal into the source region and the drain region; removing the induction metal layer; performing a thermal treatment to the doped active layer so that the impurity is activated and the metal induced crystallization and the metal induced lateral crystallization occur in the active layer due to the induction metal, converting the amorphous silicon to polysilicon in the source region, the drain region and the channel region of the active layer; and forming a source electrode and a drain electrode. | 10-23-2014 |
20140312350 | Large Area Ultrasonic Receiver Array - Devices and methods of creating an image of a biological object are disclosed. In one embodiment of the invention there is a plane wave ultrasonic pulse generator, an ultrasonic wave manipulation device, an ultrasonic detector and an image generator. In a method according to the invention, a biological object is imaged by emitting an unfocussed ultrasonic energy wave front, reflecting at least a portion of the ultrasonic energy wave front from the object, altering a direction of the ultrasonic energy, detecting that energy, and using the detected energy to create an image of the object. | 10-23-2014 |
20140327007 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process. | 11-06-2014 |
20140332815 | SEMICONDUCTOR DEVICE INCLUDING FINFET AND DIODE HAVING REDUCED DEFECTS IN DEPLETION REGION - A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region. | 11-13-2014 |
20140353667 | Semiconductor Device and Manufacturing Method Therefor - A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided. | 12-04-2014 |
20140361303 | THIN-FILM HYBRID COMPLEMENTARY CIRCUITS - Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level. | 12-11-2014 |
20140361304 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and overlapping the gate electrode; a plurality of nano particles disposed on or in the semiconductor layer; a source electrode disposed on the substrate; and a drain electrode disposed on the substrate, where the source electrode and the drain electrode are spaced apart from each other, and the semiconductor layer is disposed between the source electrode and the drain electrode, in which a diameter of each of the nano particles is in a range of about 2 nm to about 5 nm, or a ratio of a plane area of the nano particles per unit area of the semiconductor layer is in a range of about 5% to about 80%. | 12-11-2014 |
20140361305 | THIN-FILM DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING IMAGE DISPLAY APPARATUS - There is provided a method of manufacturing a thin-film device, the method including forming a first substrate on a supporting base by a coating method, the first substrate being formed by using a resin material; forming a second substrate on the first substrate by using any one of a thermosetting resin and energy ray-curable resin; forming an active element on the second substrate; and removing the supporting base from the first substrate. The resin material used to form the first substrate has a glass transition temperature of at least 180° C. | 12-11-2014 |
20140367689 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar. | 12-18-2014 |
20140367690 | ILLUMINATION APPARATUS - A point light source is converted into a plane light source having a satisfactory uniformity. The point light source is converted into a line light source by means of a linear light guiding plate, and further into the plane light source by means of a plane-like light guiding plate. Light from the point light source is reflected at a lamp reflector to be incident on at least two side surfaces of the plane-like light guiding plate. | 12-18-2014 |
20140374761 | Structure, Method for Manufacturing Structure, and illuminating structure of Thin Film Transistor - A structure, a method for manufacturing a structure, and an illuminating structure of a thin film transistor are disclosed. In the method, a substrate is provided, and a patterned first conductor layer is formed on the substrate. A patterned semiconductor layer, a patterned insulation layer, and a patterned second conductor layer are formed after forming the patterned first conductor layer, in which the patterned insulation layer contacts with the patterned second conductor layer. A first permeation barrier layer which covers the patterned second conductor layer and the patterned insulation layer is formed. | 12-25-2014 |
20150008435 | SENSOR AND METHOD FOR FABRICATING THE SAME - Embodiments of the invention disclose a sensor and its fabrication method, the sensor comprises: a base substrate, a group of gate lines and a group of data lines arranged as crossing each other, a plurality of sensing elements arranged in an array and defined by the group of gate lines and the group of data lines, each sensing element comprising a TFT device and a photodiode sensing device, wherein the TFT device is a bottom gate TFT; the photodiode sensing device comprises: a receiving electrode connected with a source electrode, a photodiode disposed on the receiving electrode, a transparent electrode disposed on the photodiode, and a bias line disposed on and connected with the transparent electrode, the bias line is disposed as parallel to the gate line. | 01-08-2015 |
20150008436 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a base substrate, a gate-line on the base substrate, a data-line crossing the gate-line, a pixel area defined on the base substrate, a gate-pad part connected to an end portion of the gate-line and including a gate corrosion member, and a data-pad part connected to an end portion of the data-line and including a data corrosion member. | 01-08-2015 |
20150008437 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon. | 01-08-2015 |
20150041815 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped. | 02-12-2015 |
20150048375 | METHOD OF MANUFACTURING STRETCHABLE SUBSTRATE AND STRETCHABLE SUBSTRATE MANUFACTURED USING THE METHOD - Provided is a method of manufacturing a gradually stretchable substrate. The method includes forming convex regions and concave regions on a top surface of a stretchable substrate by compressing a mold onto the stretchable substrate and forming non-stretchable patterns by filling the concave regions of the stretchable substrate. The stretchable substrate includes a stretchable region defined by the non-stretchable patterns, the non-stretchable patterns have side surfaces in contact with the stretchable region, and the side surfaces of the non-stretchable patterns are formed of protrusions and a non-protrusion between the protrusions repetitively connected to one another. | 02-19-2015 |
20150053985 | MICROMACHINE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced. | 02-26-2015 |
20150060860 | ANODE CONNECTION STRUCTURE OF ORGANIC LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOF - The present invention provides an anode connection structure of an organic light-emitting diode and a manufacture method thereof. The structure includes: a thin-film transistor ( | 03-05-2015 |
20150060861 | GaN Misfets with Hybrid AI203 As Gate Dielectric - Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties. | 03-05-2015 |
20150060862 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line. | 03-05-2015 |
20150069398 | TFT Switch and Method for Manufacturing the Same - The present invention proposes a TFT switch and a method for manufacturing the same. The TFT switch includes a gate, a drain, a source, a semiconductor layer and a fourth electrode. The drain is connected to a first signal, the gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off. | 03-12-2015 |
20150069399 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer. | 03-12-2015 |
20150069400 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of the first region is larger than an effective work function of the second region. | 03-12-2015 |
20150097189 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer. | 04-09-2015 |
20150102345 | ACTIVE DEVICE AND MANUFACTURING METHOD THEREOF - An active device includes a gate, a gate insulation layer, a channel layer, a first passivation layer, a second passivation layer, a source and a drain. The gate insulation layer is disposed on the substrate and covers the gate. The channel layer is disposed on the gate insulation layer and has a semiconductor section disposed corresponding to the gate and a conductive section located around the semiconductor section. The first passivation layer is disposed on the channel layer and covers the semiconductor section. The second passivation layer is disposed on and covers the first passivation layer. The source and the drain are disposed on the gate insulation layer, and extended along peripheries of the conductive section, the first and the second passivation layers to be disposed on the second passivation layer. A portion of the second passivation layer is exposed between the source and the drain. | 04-16-2015 |
20150102346 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole. | 04-16-2015 |
20150102347 | OXIDE SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element having high mobility, which includes an oxide semiconductor layer having crystallinity, is provided. The oxide semiconductor layer includes a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film having a wider band gap than the first oxide semiconductor film, which is in contact with the first oxide semiconductor film. Thus, a channel region is formed in part of the first oxide semiconductor film (that is, in an oxide semiconductor film having a smaller band gap) which is in the vicinity of an interface with the second oxide semiconductor film. Further, dangling bonds in the first oxide semiconductor film and the second oxide semiconductor film are bonded to each other at the interface therebetween. Accordingly, a decrease in mobility resulting from an electron trap or the like due to dangling bonds can be reduced in the channel region. | 04-16-2015 |
20150129878 | SEMICONDUCTOR DEVICE - A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region. | 05-14-2015 |
20150137127 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a gate line disposed on a base substrate and extending in a direction. A data line crosses the gate line. A thin film transistor comprises a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The thin film transistor is connected to the gate line and the data line. A pixel electrode is connected to the thin film transistor. A light blocking pattern overlaps the semiconductor pattern. The light blocking pattern includes a haze-processed material of substantially the same material as the pixel electrode. | 05-21-2015 |
20150144949 | Semiconductor Device and Manufacturing Method Thereof - A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask. | 05-28-2015 |
20150295094 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The method for manufacturing the thin film transistor including: forming an active layer; forming an etch barrier layer on the active layer at a position for forming interlayer via holes subsequently; forming an insulating layer on the active layer and the etch barrier layer, and forming the interlayer via holes in the insulating layer to expose the etch barrier layer. | 10-15-2015 |
20150303213 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES INCLUDING A VERTICAL CHANNEL - Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content. | 10-22-2015 |
20150311350 | TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process. | 10-29-2015 |
20150318394 | Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit - A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed. | 11-05-2015 |
20150318403 | ALUMINUM SUBSTRATE FOR A THIN FILM TRANSISTOR - A substrate comprises of a recrystallized aluminum alloy. An organic polymer layer coats the top surface of the aluminum substrate. A layer of one of: SiO | 11-05-2015 |
20150318404 | Semiconductor device - A manufacturing method of a display device having an array substrate includes the steps of forming a projection of an organic material in a pixel on the array substrate by patterning a photosensitive material or by inkjet, forming a TFT on the array substrate, wherein a source electrode of the TFT is formed to extend on at least part of the upper surface of the projection, forming an inorganic passivation layer over the TFT and over at least part of the upper surface of the projection, forming an organic passivation layer over the inorganic passivation layer, forming an upper insulating layer over at least part of the organic passivation layer, forming a contact hole in the inorganic passivation layer and the upper insulation layer over the upper surface of the projection, and forming a pixel electrode on the upper insulation layer which contacts the source electrode. | 11-05-2015 |
20150325599 | Wireless Processor, Wireless Memory, Information System, And Semiconductor Device - The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna. | 11-12-2015 |
20150348800 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate. | 12-03-2015 |
20150349117 | III-NITRIDE INSULATING-GATE TRANSISTORS WITH PASSIVATION - A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench. | 12-03-2015 |
20150357479 | SEMICONDUCTOR DEVICE - A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions. | 12-10-2015 |
20150364327 | METHOD FOR PREPARING A FILM AND METHOD FOR PREPARING AN ARRAY SUBSTRATE, AND ARRAY SUBSTRATE - The present invention discloses a method for preparing a film and a method for preparing an array substrate, and an array substrate. The method for preparing a film comprises forming an AB alloy film subjected to oxidation treatment and forming a first metal A film, wherein the first metal A film is provided to contact with the AB alloy film subjected to oxidation treatment, wherein A is a first metal and B is a second metal, the second metal is selected from active metals in period 2 to period 4 of group 2, and the AB alloy film subjected to oxidation treatment is formed by forming an alloy film of a first metal A and a second metal B in the presence of an oxygen-containing gas. | 12-17-2015 |
20150364486 | SELF-ALIGNED FLOATING GATE IN A VERTICAL MEMORY STRUCTURE - A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed. | 12-17-2015 |
20150380436 | METHODS OF FORMING PRINTABLE INTEGRATED CIRCUIT DEVICES AND DEVICES FORMED THEREBY - Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer. | 12-31-2015 |
20150380524 | Manufacturing A Submicron Structure Using A Liquid Precursor - A method for manufacturing a submicron semiconductor structure on a substrate, including: forming at least one template layer over a support substrate; forming one or more template structures, including one or more recesses and/or mesas, in the template layer, the one or more template structures including one or more edges extending into or out of the top surface of the template layer; coating at least part of the one or more template structures with a liquid semiconductor precursor; and, annealing and/or exposing the liquid semiconductor precursor coated template structures to light, wherein during the annealing and/or light exposure a part of the liquid semiconductor precursor accumulates by capillary forces against at least part of the one or more edges, the annealing and/or light exposure transforming the accumulated liquid semiconductor precursor into a submicron semiconductor structure extending along at least part of the one or more edges. | 12-31-2015 |
20150380564 | SEMICONDUCTOR DEVICE - It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region. | 12-31-2015 |
20150380686 | ELECTRONIC DEVICE - The present technique provides an electronic device, such as a flexible EL display device, including: first barrier film including a laminate of inorganic film including an inorganic material and polymer film including a polymer material; second barrier film including a laminate of inorganic film including an inorganic material and polymer film including a polymer material; and thin film transistor array device and light emitter both sealed with first and second barrier films. Polymer films each contain at least one type of nano fine particles selected from silica particles, Fe-based particles, montmorillonite particles, silica-coated particles, and zeolite particles, dispersed in the polymer material. | 12-31-2015 |
20160005761 | Data Line Arrangement and Pillar Arrangement in Apparatuses - Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). | 01-07-2016 |
20160013294 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR | 01-14-2016 |
20160020096 | Manufacture Method Of Low Temperature Poly Silicon, Manufacturing Method Of TFT Substrate Utilizing The Method, And TFT Substrate Structure - The present invention provides a manufacture method of Low Temperature Poly Silicon, a manufacture method of a TFT substrate utilizing the method and a TFT substrate structure. The manufacture method of Low Temperature Poly Silicon comprises steps of: step 1, providing a substrate ( | 01-21-2016 |
20160020225 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a plurality of memory strings including a plurality of memory transistors connected in series and a selection transistor disposed on either end of the plurality of memory transistors, which together form a memory cell. The memory transistors and the selection transistors each include a polysilicon layer formed on an insulating film as a channel region thereof. A drain region is in a first diffusion layer region in the polysilicon layer in a location adjacent to a selection transistor at a first end of the memory string, and a source region is in a second diffusion layer region in the polysilicon layer in a location adjacent to a selection transistor at a second end of the memory string. In at least one of the first and the second diffusion regions, the grain size of the polysilicon is smaller than in other portions of the polysilicon. | 01-21-2016 |
20160027873 | THIN FILM TRANSISTOR - The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance. | 01-28-2016 |
20160027890 | ELECTROCHEMICALLY-GATED FIELD-EFFECT TRANSISTOR AND METHOD FOR ITS MANUFACTURE - An electromechanically-gated field-effect transistor includes an arrangement which is placed on top of a substrate. The arrangement includes a first electrode, a second electrode, a transistor channel, an electrolyte, and a gate electrode. The first electrode is placed on top of the substrate and including a first solid or porous metallic conducting body, a second electrode. The second electrode is placed on top of a transistor channel so as to at least partially cover the transistor channel. The transistor channel, which includes a porous semiconducting material, is placed on top of the first electrode so as to at least partially cover the first electrode and located between the first electrode and the second electrode in a manner to prevent any direct electrical contact between the first electrode and the second electrode. | 01-28-2016 |
20160035753 | Complementary Thin Film Transistor and Manufacturing Method Thereof, Array Substrate, Display Apparatus - The present invention provides a complementary thin film transistor and a manufacturing method thereof, an array substrate and a display apparatus, relates to the field of manufacturing technology of thin film transistor, and can solve the problem that active layer materials of first and second thin film transistors in a complementary thin film transistor of the prior art have influence with each other. The manufacturing method of the present invention comprises steps of: forming a pattern comprising an active layer of a first thin film transistor and a protective layer on a base by a patterning process, and the protective layer is at least located above the active layer of the thin film transistor; and forming a pattern of an active layer of a second thin film transistor on the base subjected to above step by a patterning process. The present invention may be applied to various circuits and systems. | 02-04-2016 |
20160035819 | LOW-TEMPERATURE POLYSILICON MEMBRANE AND PREPARATION METHOD THEREOF, THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S | 02-04-2016 |
20160035901 | FABRICATING METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR AND DISPLAY PANEL - Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon. The fabricating method a thin film transistor comprises following M | 02-04-2016 |
20160035903 | THIN-FILM TRANSISTOR - Thin-film transistor includes column-shaped protrusion portion having a side surface and protruding from a main surface of the substrate, a gate insulating layer including a first layer and a second layer, at least part of the gate insulating layer being in a channel region extending along the side surface, a gate electrode in contact with the gate insulating layer, a source electrode and a drain electrode isolated from one another, at least part of one of the source electrode and the drain electrode overlap the protrusion portion and the other being in a region that does not overlap the protrusion portion or the one electrode, and a semiconductor layer in contact with at least part of the source electrode, at least part of the drain electrode, and at least part of the gate insulating layer in the channel region directly or with a functional layer interposed. | 02-04-2016 |
20160049300 | METHOD AND APPARATUS FOR MANUFACTURING LOW TEMPERATURE POLY-SILICON FILM, AND LOW TEMPERATURE POLY-SILICON FILM - Disclosed are a method and an apparatus for manufacturing low temperature poly-silicon film, and a low temperature poly-silicon film. The method includes: providing a substrate; forming an amorphous silicon film; applying different temperatures to different regions of the amorphous silicon film by using an excimer laser annealing method, to change the amorphous silicon film into a molten state; and recrystallizating the amorphous silicon film in the molten state, a region having a lower temperature serving as a starting point, a region having a higher temperature serving as an end point, to form a low temperature poly-silicon film. The low temperature poly-silicon film manufactured by the above method and apparatus has a greater size of the crystalline grain and a larger electronic mobility than in the existing technology. | 02-18-2016 |
20160056171 | INTEGRATED CIRCUIT DEVICE INCLUDING POLYCRYSTALLINE SEMICONDUCTOR FILM AND METHOD OF MANUFACTURING THE SAME - An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device. | 02-25-2016 |
20160064423 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device ( | 03-03-2016 |
20160079262 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a conductive layer; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a semiconductor body provided in the stacked body and extending in a stacking direction in the stacking body and including a lower end portion provided in the conductive layer; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. As viewed in the stacking direction, a maximum width of the lower end portion is larger than a maximum width of the semiconductor body provided inside a bottom surface of the charge storage film. | 03-17-2016 |
20160079385 | VERTICAL TFT WITH MULTILAYER PASSIVATION - A vertical transistor includes an electrically conductive gate structure having a reentrant profile in contact with a substrate. A conformal gate insulating layer is in contact with the gate structure in the reentrant profile. A conformal semiconductor layer is in contact with the conformal gate insulating layer. A first electrode is in contact with a first portion of the conformal semiconductor layer over the electrically conductive gate structure. A second electrode is in contact with a second portion of the conformal semiconductor layer and separated vertically from the first electrode. The vertical TFT has a multilayer insulating structure that is in contact with at least the conformal semiconductor layer in the reentrant profile. The multilayer insulating structure includes an inorganic dielectric layer and a polymer structure in contact with the conformal semiconductor layer in the reentrant profile. | 03-17-2016 |
20160086972 | MONOLITHIC THREE-DIMENSIONAL NAND STRINGS AND METHODS OF FABRICATION THEREOF - A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers. | 03-24-2016 |
20160093688 | SOURCE-CHANNEL INTERACTION IN 3D CIRCUIT - A multilayer source provides charge carriers to a multitier channel connector. The source includes a metal silicide layer on a substrate and a metal nitride layer between the metal silicide layer and the channel. The metal silicide and the metal nitride are processed without an intervening oxide layer between them. In one embodiment, the source further includes a silicon layer between the metal nitride layer and the channel. The silicon layer can also be processed without an intervening oxide layer. Thus, the source does not have an intervening oxide layer from the substrate to the channel. | 03-31-2016 |
20160099250 | THREE DIMENSIONAL NAND DEVICE WITH SILICON GERMANIUM HETEROSTRUCTURE CHANNEL - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion. | 04-07-2016 |
20160099257 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor includes an active pattern formed on a substrate; a gate pattern formed on the active pattern and comprising a gate electrode and a gate line; a gate insulating layer disposed between the gate pattern and the active pattern; a source electrode that overlaps a first side of the active pattern and contacts a data line; a drain electrode that overlaps a second side of the active pattern and is separated from the source electrode; a channel area formed in an area where the gate line and an active line of the active pattern overlap each other; and a gate line modifying unit formed in the channel area by changing a linear shape of the gate line. | 04-07-2016 |
20160111550 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer. | 04-21-2016 |
20160118391 | DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE - A monolithic three-dimensional memory structure includes a memory stack structure including a memory film and a semiconductor channel. Traps and/or defects within the semiconductor channel and/or at the semiconductor/dielectric material interface and/or inside dielectric materials can be passivated by an anneal in a deuterium-containing gas, which replaces hydrogen atoms within the semiconductor channel or passivate the dangling bonds/traps with deuterium atoms. The anneal may be performed immediately after formation of the semiconductor channel, before or after formation of a dielectric core or a drain region, after replacement of sacrificial material layers with conductive material layers, after dicing of a substrate into semiconductor chips, or at another suitable processing step. | 04-28-2016 |
20160118467 | THIN FILM TRANSISTOR, DISPLAY PANEL AND DISPLAY APPARATUS - Disclosed is a thin film transistor, including a gate electrode, a source electrode and a drain electrode. The source electrode includes a loop structure with an opening, and a width of the opening is less than a maximum width of an inner ring of the loop structure of the source electrode in a direction identical to a direction of the width of the opening. The drain electrode is surrounded by the loop structure, and is not in contact with the source electrode. The drain electrode is distant from the inner ring of the loop structure of the source electrode at a same interval. | 04-28-2016 |
20160118504 | THIN FILM TRANSISTOR - A thin film transistor disposed on a substrate, includes a gate, a gate insulation layer, a first source/drain, a semiconductor layer and a second source/drain. The gate is disposed on the substrate. The gate insulation layer covers the gate and the substrate. The first source/drain is disposed on the gate insulation layer. The semiconductor layer is disposed above the gate, extends from the gate insulation layer to the first source/drain, and includes a first portion disposed on the first source/drain and a second portion connected to the first portion. An electrical conductivity of the first portion is higher than that of the second portion. The second source/drain covers and is in contact with the second portion. A manufacturing method of thin film transistor is further provided. | 04-28-2016 |
20160126344 | TFT SUBSTRATE WITH VARIABLE DIELECTRIC THICKNESS - A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness. | 05-05-2016 |
20160133653 | NARROW BEZEL FLAT PANEL DISPLAY - Provided is a flat panel display. A flat panel display includes: a lower panel defining a display area and a non-display area, a driver element and a line within the non-display area, a planar layer covering the lower panel, a first trench at the planar layer over the driver element and the line, a lower alignment layer on an upper surface of the planar layer and a lower surface of the first trench, the lower alignment layer exposing some upper surface of the planar layer at the first trench, and a sealant at the first trench. | 05-12-2016 |
20160133713 | Floating Gate NVM With Low-Moisture-Content Oxide Cap Layer - A back-end metallization structure for non-volatile memory (NVM) and other semiconductor devices including low-moisture-content oxide cap layers that suppress the creation and migration of mobile hydrogen atoms/ions during back-end processing. The metallization structure includes multiple metallization layers formed over front-end e.g., polysilicon (floating gate) structures and a pre-metal dielectric layer. Each metallization layer includes a patterned metal (e.g., aluminum) structure covered by an interlevel dielectric (ILD) layer (e.g., BPSG, USG or FSG). Each cap layer is formed using a high-density low-moisture content oxide such as silane oxide (i.e., SiO | 05-12-2016 |
20160141530 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD - In an organic TFT ( | 05-19-2016 |
20160148949 | SEMICONDUCTOR STRUCTURES INCLUDING DIELECTRIC MATERIALS HAVING DIFFERING REMOVAL RATES - Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures. | 05-26-2016 |
20160163727 | METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE - Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described. | 06-09-2016 |
20160163728 | UNIFORM THICKNESS BLOCKING DIELECTRIC PORTIONS IN A THREE-DIMENSIONAL MEMORY STRUCTURE - A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions. | 06-09-2016 |
20160164014 | THIN FILM TRANSISTOR - A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, an insulating layer and a gate electrode. The drain electrode is spaced from the source electrode. The semiconductor layer is electrically connected to the source electrode and the drain electrode. The gate electrode is insulated with the source electrode, the drain electrode and the semiconductor layer by the insulating layer. The gate electrode, the source electrode, and the drain electrode comprise a plurality of first carbon nanotubes. The semiconductor layer comprises a plurality of second carbon nanotubes. A distribution density of the plurality of first carbon nanotubes is about 20 times as much as that of the plurality of second carbon nanotubes. A number of the plurality of second carbon nanotubes in 1 square micrometers is smaller than or equal to 1. | 06-09-2016 |
20160172389 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF | 06-16-2016 |
20160181182 | ELECTRONIC DEVICE AND METHODS OF PROVIDING AND USING ELECTRONIC DEVICE | 06-23-2016 |
20160181273 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 06-23-2016 |
20160181437 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE | 06-23-2016 |
20160190231 | SEMICONDUCTOR SWITCH - According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film. | 06-30-2016 |
20160190340 | LATERAL GATE ELECTRODE TFT SWITCH AND LIQUID CRYSTAL DISPLAY DEVICE - A lateral gate electrode TFT switch and a liquid crystal display device are disclosed. The lateral TFT switch has a substrate, a source-drain area, a gate insulation layer and a gate electrode. The source-drain area is disposed on the substrate and has a source electrode, a drain electrode and a semiconductor layer. The semiconductor layer is disposed between the source electrode and the drain electrode. The source electrode and the drain electrode are vertically disposed on the substrate. The gate insulation layer is disposed adjacent to the source-drain area. The gate electrode is disposed adjacent to the gate insulation layer. The gate insulation layer is used to separate the source-drain area from the gate electrode. | 06-30-2016 |
20160197196 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME | 07-07-2016 |
20170236948 | THIN FILM TRANSISTOR, MANUFACTURING PROCESS FOR THIN FILM TRANSISTOR, AND LASER ANNEALING APPARATUS | 08-17-2017 |
20170237003 | SURFACE TREATMENT OF HYDROPHOBIC FERROELECTRIC POLYMERS FOR PRINTING | 08-17-2017 |
20180025983 | DESIGNABLE CHANNEL FINFET FUSE | 01-25-2018 |
20180026213 | Field Effect Transistor and Method for Production Thereof | 01-25-2018 |
20190148371 | Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions | 05-16-2019 |
20190148392 | THREE-DIMENSIONAL MEMORY DEVICE WITH THICKENED WORD LINES IN TERRACE REGION AND METHOD OF MAKING THEREOF | 05-16-2019 |
20190148396 | METHOD OF MANUFACTURING THREE-DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND STRUCTURE MANUFACTURED BY THE SAME | 05-16-2019 |