Entries |
Document | Title | Date |
20080217603 | Hot electron transistor and semiconductor device including the same - A hot electron transistor includes a collector layer, a base layer, an emitter layer, a collector barrier layer formed between the collector layer and the base layer, and an emitter barrier layer formed between the base layer and the emitter layer. An energy barrier between the emitter barrier layer and the emitter layer does not substantially exist and the height of an energy barrier of the collector barrier layer is lower than the height of an energy barrier of the emitter barrier layer. | 09-11-2008 |
20090294759 | Stack structure comprising epitaxial graphene, method of forming the stack structure, and electronic device comprising the stack structure - Provided are a stack structure including an epitaxial graphene, a method of forming the stack structure, and an electronic device including the stack structure. The stack structure includes: a Si substrate; an under layer formed on the Si substrate; and at least one epitaxial graphene layer formed on the under layer. | 12-03-2009 |
20100038629 | Anisotropic Semiconductor Film and Method of Production Thereof - The present invention relates generally to the field of macro- and microelectronics with the potential for large-scale integration, optics, communications, and computer technology and particularly to the materials for these and other related fields. The present invention provides an anisotropic semiconductor film on a substrate, comprising at least one solid layer of material that comprises predominantly planar graphene-like carbon-based structures and possesses anisotropy of conductivity, and wherein the layer thickness is in a range from approximately 5 nm to 1000 nm. | 02-18-2010 |
20100051907 | Devices including graphene layers epitaxially grown on single crystal substrates - An electronic device comprises a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and a at least one epitaxial layer of graphene is disposed on the single crystal region. In a currently preferred embodiment, the single crystal region comprises multilayered hexagonal BN. A method of making such an electronic device comprises the steps of: (a) providing a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and (b) epitaxially forming a at least one graphene layer on that region. In a currently preferred embodiment, step (a) further includes the steps of (a1) providing a single crystal substrate of graphite and (a2) epitaxially forming multilayered single crystal hexagonal BN on the substrate. The hexagonal BN layer has a surface region substantially lattice-matched to graphene, and step (b) includes epitaxially forming at least one graphene layer on the surface region of the hexagonal BN layer. Applications to FETs are described. | 03-04-2010 |
20100200839 | GRAPHENE GROWN SUBSTRATE AND ELECTRONIC/PHOTONIC INTEGRATED CIRCUITS USING SAME - A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less. | 08-12-2010 |
20100200840 | GRAPHENE-BASED TRANSISTOR - A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region. | 08-12-2010 |
20100258786 | SELF-ASSEMBLED ORGANIC MONOLAYERS ON GRAPHENE AND METHODS OF MAKING AND USING - Self-assembled organic monolayers on epitaxial graphene are described. The organic molecules are perylene derivatives including 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) molecules arranged in a herringbone phase and/or molecules are of the following formula: | 10-14-2010 |
20100289005 | AMORPHOUS MULTI-COMPONENT METALLIC THIN FILMS FOR ELECTRONIC DEVICES - An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode. | 11-18-2010 |
20110017979 | HIGH-PERFORMANCE GATE OXIDES SUCH AS FOR GRAPHENE FIELD-EFFECT TRANSISTORS OR CARBON NANOTUBES - An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices. | 01-27-2011 |
20110042650 | SINGLE AND FEW-LAYER GRAPHENE BASED PHOTODETECTING DEVICES - A photodetector which uses single or multi-layer graphene as the photon detecting layer is disclosed. Multiple embodiments are disclosed with different configurations of electrodes. In addition, a photodetector array comprising multiple photodetecting elements is disclosed for applications such as imaging and monitoring. | 02-24-2011 |
20110062421 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer. | 03-17-2011 |
20110062422 | Systems And Methods For Forming Defects On Graphitic Materials And Curing Radiation-Damaged Graphitic Materials - Systems and methods are disclosed herein for forming defects on graphitic materials. The methods for forming defects include applying a radiation reactive material on a graphitic material, irradiating the applied radiation reactive material to produce a reactive species, and permitting the reactive species to react with the graphitic material to form defects. Additionally, disclosed are methods for removing defects on graphitic materials. | 03-17-2011 |
20110089403 | Electronic device using a two-dimensional sheet material, transparent display and methods of fabricating the same - An electronic device, a transparent display and methods for fabricating the same are provided, the electronic device including a first, a second and a third element each formed of a two-dimensional (2D) sheet material. The first, second, and third elements are stacked in a sequential order or in a reverse order. The second element is positioned between the first element and the third element. The second element has an insulator property, the first and third elements have a metal property or a semiconductor property. | 04-21-2011 |
20110089404 | Microfabrication of Carbon-based Devices Such as Gate-Controlled Graphene Devices - A graphene device includes a graphene layer and a back gate electrode connected to apply a global electrical bias to the graphene from a first surface of the graphene. At least two graphene device electrodes are each connected to a corresponding and distinct region of the graphene at a second graphene surface. A dielectric layer blanket-coats the second graphene surface and the device electrodes. At least one top gate electrode is disposed on the dielectric layer and extends over a distinct one of the device electrodes and at least a portion of a corresponding graphene region. Each top gate electrode is connected to apply an electrical charge carrier bias to the graphene region over which that top gate electrode extends to produce a selected charge carrier type in that graphene region. Such a carbon structure can be exposed to a beam of electrons to compensate for extrinsic doping of the carbon. | 04-21-2011 |
20110095268 | TRANSISTOR AND FLAT PANEL DISPLAY INCLUDING THIN FILM TRANSISTOR - A transistor includes at least three terminals comprising a gate electrode, a source electrode and a drain electrode, an insulating layer disposed on a substrate, and a semiconductor layer disposed on the substrate, wherein a current which flows between the source electrode and the drain electrode is controlled by application of a voltage to the gate electrode, where the semiconductor layer includes a graphene layer and at least one of a metal atomic layer and a metal ion layer, and where the metal atomic layer or the metal ion layer is interposed between the graphene layer and the insulating layer. | 04-28-2011 |
20110101309 | GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene. | 05-05-2011 |
20110108806 | Method to Modify the Conductivity of Graphene - A gated electrical device includes a non-conductive substrate and a graphene structure disposed on the non-conductive substrate. A metal gate is disposed directly on a portion of the graphene structure. The metal gate includes a first metal that has a high contact resistance with graphene. Two electrical contacts are each placed on the graphene structure so that the metal gate is disposed between the two electrical contacts. In a method of making a gated electrical device, a graphene structure is placed onto a non-conductive substrate. A metal gate is deposited directly on a portion of the graphene structure. Two electrical contacts are deposited on the graphene structure so that the metal gate is disposed between the two electrical contacts. | 05-12-2011 |
20110114919 | SELF-ALIGNED GRAPHENE TRANSISTOR - A graphene field effect transistor includes a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide; an insulating layer; and a graphene sheet displaced between the seed layer and the insulating layer. | 05-19-2011 |
20110140088 | PHASE COHERENT SOLID STATE ELECTRON GYROSCOPE ARRAY - An apparatus and method is disclosed which may comprise an electron gyroscope, which may comprise an interferometer array which may comprise interferometer rings formed from a sheet of graphene. Each interferometer ring in the interferometer array may have a half-circumference shorter in length than the ballistic length for an electron in graphene. | 06-16-2011 |
20110156007 | COMPLEMENTARY LOGIC GATE DEVICE - Provided is a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits which can effectively solve the problem of the speed performance limit of an ultra-large scale integration and an ultra-low power consumption type logical circuit. The complementary logical gate includes an electron running layer formed by grapheme without using an n-channel FET or a p-channel FET, has the ambipolar characteristic, and uses only two FET having different threshold values, i.e., a first FET and a second FET. The first FET has a gate electrode short-circuited to a gate electrode of the second FET so as to constitute an input terminal. The first FET has a source electrode set to a low potential. The first FET has a drain electrode connected to a source electrode of the second FET so as to constitute an output terminal. The second FET has a drain electrode set to a high potential. | 06-30-2011 |
20110163298 | Graphene and Hexagonal Boron Nitride Devices - Graphene layers, hexagonal boron nitride (hBN) layers, as well as other materials made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, the present invention provides graphene and hBN devices. In one aspect, for example, an electronic device is provided including a graphene layer and a planar hBN layer operably associated with the graphene layer and forming a functional interface therebetween. Numerous functional interfaces are contemplated, depending on the desired functionality of the device. | 07-07-2011 |
20110168981 | NANOTUBE ARRAY BIPOLAR TRANSISTORS - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits. | 07-14-2011 |
20110175060 | GRAPHENE GROWN SUBSTRATE AND ELECTRONIC/PHOTONIC INTEGRATED CIRCUITS USING SAME - A substrate having a graphene film grown thereon according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al | 07-21-2011 |
20110186817 | Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device. | 08-04-2011 |
20110186818 | Doped graphene electronic materials - A graphene substrate is doped with one or more functional groups to form an electronic device. | 08-04-2011 |
20110210314 | Graphene electronic device and method of fabricating the same - A graphene electronic device may include a silicon substrate, connecting lines on the silicon substrate, a first electrode and a second electrode on the silicon substrate, and an interlayer dielectric on the silicon substrate. The interlayer dielectric may be configured to cover the connecting lines and the first and second electrodes and the interlayer dielectric may be further configured to expose at least a portion of the first and second electrodes. The graphene electronic device may further include an insulating layer on the interlayer dielectric and a graphene layer on the insulating layer, the graphene layer having a first end and a second end. The first end of the graphene layer may be connected to the first electrode and the second end of the graphene layer may be connected to the second electrode. | 09-01-2011 |
20110215300 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 09-08-2011 |
20110227044 | TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact. | 09-22-2011 |
20110227045 | Voltage-Controlled Switches - A voltage-controlled switch ( | 09-22-2011 |
20110248243 | Carbon nanotube field effect transistor for printed flexible/rigid electronics - Methods and devices for manufacturing carbon nanotube based field effect transistors are disclosed including providing a substrate; printing a gate electrode layer onto the substrate and sintering and/or UV curing; printing a gate isolation layer onto the gate electrode and air drying and/or UV curing; printing one or more carbon nanotube channel layers onto the gate isolation layer, wherein each carbon nanotube channel layer is air dried prior to subsequent printings; and printing a source and drain electrode layer onto the one or more carbon nanotube channel layers and sintering and/or UV curing. Other embodiments are described and claimed. | 10-13-2011 |
20110278545 | Manufacture of Graphene-Based Apparatus - An apparatus including: a stacked structure including a first substrate having a flat surface; a flat first graphene layer adjacent the flat surface of the first substrate; a flat second graphene layer adjacent the flat first graphene layer; and a second substrate having a flat surface adjacent the flat second graphene layer. An apparatus including: a stacked structure including a substrate having a flat upper surface; a flat lower patterned layer overlying the flat upper surface of the substrate and including at least one patterned electrode; a flat lower graphene layer overlying the flat lower patterned layer; a flat upper graphene layer overlying the flat lower graphene layer; and a flat upper patterned layer overlying the flat upper graphene layer and including at least one patterned electrode. | 11-17-2011 |
20110291075 | FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND BIOSENSOR - Disclosed is a carbon nanotube field effect transistor which stably exhibits excellent electrical conduction properties. Also disclosed are a method for manufacturing the carbon nanotube field effect transistor, and a biosensor comprising the carbon nanotube field effect transistor. First of all, an silicon oxide film is formed on a contact region of a silicon substrate by an LOCOS method. Next, an insulating film, which is thinner than the silicon oxide film on the contact region, is formed on a channel region of the silicon substrate. Then, after arranging a carbon nanotube, which forms a channel, on the silicon substrate, the carbon nanotube is covered with a protective film. Finally, a source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically connected to the carbon nanotube, respectively. A field effect transistor manufactured by these processes stably exhibits excellent electrical conduction properties since the carbon nanotube, which serves as the channel, is not contaminated. | 12-01-2011 |
20110303899 | GRAPHENE DEPOSITION - Embodiments of the invention are directed toward the deposition of Graphene on a semiconductor substrate. In some embodiments, these processes can occur at low temperature levels during a back end of the line process. For example, Graphene can be deposited in a CVD reactor at a processing temperature that is below 600° C. to protect previously deposited layers that may be susceptible to sustained higher temperatures. Graphene deposition can include the deposition of an underlayer (e.g., cobalt) followed by the flow of a carbon precursor (e.g., acetylene) at the processing temperature. Graphene can then be synthesized with during cooling, an RTP cure, and/or a UV cure. | 12-15-2011 |
20110309336 | SEMICONDUCTING GRAPHENE COMPOSITION, AND ELECTRICAL DEVICE INCLUDING THE SAME - A graphene composition including a graphene monolayer and an alkali metal disposed on the graphene monolayer. | 12-22-2011 |
20110315961 | Ultrathin Spacer Formation for Carbon-Based FET - A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET. | 12-29-2011 |
20110315962 | NANOSENSORS - Electrical devices comprised of nanowires are described, along with methods of their manufacture and use. The nanowires can be nanotubes and nanowires. The surface of the nanowires may be selectively functionalized Nanodetector devices are described. | 12-29-2011 |
20120007054 | Self-Aligned Contacts in Carbon Devices - A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity. | 01-12-2012 |
20120012817 | Semiconductor devices and methods of manufacturing an operating same - A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device. | 01-19-2012 |
20120032150 | Semiconductor component, method of producing a semiconductor component, semiconductor device - Semiconductor component comprising: | 02-09-2012 |
20120068159 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer. | 03-22-2012 |
20120068160 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact plug is connected to the graphene film. The adjustment film is formed in a region other than a region connected to the contact plug of a surface of the graphene film to adjust a Dirac point position in a same direction as the region connected to the contact plug with respect to a Fermi level. | 03-22-2012 |
20120068161 | METHOD FOR FORMING GRAPHENE USING LASER BEAM, GRAPHENE SEMICONDUCTOR MANUFACTURED BY THE SAME, AND GRAPHENE TRANSISTOR HAVING GRAPHENE SEMICONDUCTOR - A method for forming graphene includes introducing a substrate and a carbon-containing reactant source into a chamber, and radiating a laser beam onto the substrate to decompose the carbon-containing reactant source and form graphene over the substrate using carbon atoms generated by decomposition of the carbon-containing reactant source. A carbon-containing gas (methane) decomposes upon radiation of a laser beam. The carbon-containing gas has a decomposition rate on the order of femtoseconds and the laser beam has a pulse on the order of nanoseconds or more. The graphene is grown in a single layer along the surface of the substrate. Then, the graphene is selectively patterned using a laser beam to form a desired pattern. | 03-22-2012 |
20120074387 | MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER - The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor. | 03-29-2012 |
20120080661 | GRAPHENE INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench. | 04-05-2012 |
20120080662 | GRAPHENE INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces. | 04-05-2012 |
20120112166 | GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP - A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene. | 05-10-2012 |
20120132893 | Graphene Electronic Devices - A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer. | 05-31-2012 |
20120138901 | Color Selective Photodetector and Methods of Making - A photoelectric device, such as a photodetector, can include a semiconductor nanowire electrostatically associated with a J-aggregate. The J-aggregate can facilitate absorption of a desired wavelength of light, and the semiconductor nanowire can facilitate charge transport. The color of light detected by the device can be chosen by selecting a J-aggregate with a corresponding peak absorption wavelength. | 06-07-2012 |
20120138902 | Edge-Contacted Vertical Carbon Nanotube Transistor - A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench. | 06-07-2012 |
20120138903 | Graphene Substrates And Methods Of Fabricating The Same - The graphene substrate may include a metal oxide film on a substrate, and a graphene layer on the metal oxide film. The concentration of oxygen in the metal oxide film may be gradually reduced from the substrate towards the graphene layer, and the graphene layer may be formed directly on the metal oxide film. | 06-07-2012 |
20120145999 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode. | 06-14-2012 |
20120146000 | Omega Shaped Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region. | 06-14-2012 |
20120146001 | ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET - A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer. | 06-14-2012 |
20120161106 | PHOTODETECTOR USING A GRAPHENE THIN FILM AND NANOPARTICLES, AND METHOD FOR PRODUCING THE SAME - Provided are a photodetector (PD) using a graphene thin film and nanoparticles and a method of fabricating the same. The PD includes a graphene thin film having a sheet shape formed by means of a graphene deposition process using a vapor-phase carbon (C) source and a nanoparticle layer formed on the graphene thin film and patterned to define an electrode region of the graphene thin film, the nanoparticle layer being formed of nanoparticles without a matrix material. The PD has a planar structure using the graphene thin film as a channel and an electrode and using nanoparticles as a photovoltaic material (capable of forming electron-hole pairs due to photoelectron-motive force caused by ultraviolet (UV) light). Since the PD has a very simple structure, the PD may be fabricated at low cost with high productivity. Also, the PD includes the graphene thin film to reduce power consumption. | 06-28-2012 |
20120168721 | GRAPHENE FORMATION ON DIELECTRICS AND ELECTRONIC DEVICES FORMED THEREFROM - Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene. | 07-05-2012 |
20120168722 | Graphene Electronic Device Including A Plurality Of Graphene Channel Layers - Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers. | 07-05-2012 |
20120168723 | ELECTRONIC DEVICES INCLUDING GRAPHENE AND METHODS OF FORMING THE SAME - Methods of forming a graphene layer are provided. The method includes sequentially forming a seed layer and a protection layer on a substrate, patterning the protection layer and the seed layer to form a protection pattern and a seed pattern having a first length in a first direction and a second length in a second direction perpendicular to the first direction, and forming a graphene material on at least one of both sidewalls of the seed pattern. The second length is greater than the first length. Related devices are also provided. | 07-05-2012 |
20120168724 | TRANSFER-FREE BATCH FABRICATION OF SINGLE LAYER GRAPHENE DEVICES - A method of manufacturing one or more graphene devices is disclosed. A thin film growth substrate is formed directly on a device substrate. Graphene is formed on the thin film growth substrate. A transistor is also disclosed, having a device substrate and a source supported by the device substrate. The transistor also has a drain separated from the source and supported by the device substrate. The transistor further has a single layer graphene (SLG) channel grown partially on and coupling the source and the drain. The transistor also has a gate aligned with the SLG channel, and a gate insulator between the gate and the SLG channel. Integrated circuits and other apparati having a device substrate, a thin film growth substrate formed directly on at least a portion of the device substrate, and graphene formed directly on at least a portion of the thin film growth substrate are also disclosed. | 07-05-2012 |
20120175594 | Graphene Devices with Local Dual Gates - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer. | 07-12-2012 |
20120175595 | Graphene Electronic Device And Method Of Fabricating The Same - A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode. | 07-12-2012 |
20120181505 | Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric. | 07-19-2012 |
20120181506 | High-Speed Graphene Transistor and Method of Fabrication by Patternable Hard Mask Materials - Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer. | 07-19-2012 |
20120181507 | SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME - A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons. | 07-19-2012 |
20120181508 | Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits - A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer. | 07-19-2012 |
20120181509 | GRAPHENE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices. | 07-19-2012 |
20120181510 | Graphene Devices and Semiconductor Field Effect Transistors in 3D Hybrid Integrated Circuits - A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator. | 07-19-2012 |
20120187377 | GRAPHENE-BASED DEVICE AND METHODS OF FORMING THE SAME - A graphene-based device can be characterized as including a first electrode comprising graphene, a second electrode comprising graphene, and a potential barrier. The first electrode is physically separated from the second electrode by the potential barrier. The first electrode, second electrode and potential barrier are configured such that the graphene-based device can exhibit non-linear I-V characteristics under application of a voltage bias between the first electrode and the second electrode. | 07-26-2012 |
20120199815 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film ( | 08-09-2012 |
20120211727 | Method of Producing Precision Vertical and Horizontal Layers in a Vertical Semiconductor Structure - The present invention relates to providing layers of different thickness on vertical and horizontal surfaces ( | 08-23-2012 |
20120217480 | METHOD FOR MANUFACTURING GRAPHENE ELECTRONICS - An electrical circuit structure employing graphene as a charge carrier transport layer. The structure includes a plurality of graphene layers. Electrical contact is made with one of the layer of the plurality of graphene layers, so that charge carriers travel only through that one layer. By constructing the active graphene layer within or on a plurality of graphene layers, the active graphene layer maintains the necessary planarity and crystalline integrity to ensure that the high charge carrier mobility properties of the active graphene layer remain intact. | 08-30-2012 |
20120217481 | MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate - Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided. | 08-30-2012 |
20120248414 | Semiconductor Device, Method Of Manufacturing The Same, And Electronic Device Including The Semiconductor Device - An example embodiment relates to a semiconductor device including a semiconductor element. The semiconductor element may include a plurality of unit layers spaced apart from each other in a vertical direction. Each unit layer may include a patterned graphene layer. The patterned graphene layer may be a layer patterned in a nanoscale. The patterned graphene layer may have a nanomesh or nanoribbon structure. The semiconductor device may be a transistor or a diode. An example embodiment relates to a method of making a semiconductor device including a semiconductor element. | 10-04-2012 |
20120248415 | RESONANCE TUNNELING DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes. | 10-04-2012 |
20120248416 | High Performance Field-Effect Transistors - A high performance field-effect transistor includes a substrate, a nanomaterial thin film disposed on the substrate, a source electrode and a drain electrode formed on the nanomaterial thin film, and a channel area defined between the source electrode and the drain electrode. A unitary self-aligned gate electrode extends from the nanomaterial thin film in the channel area between the source electrode and the drain electrode, the gate electrode having an outer dielectric layer and including a foot region and a head region, the foot region in contact with a portion of the nanomaterial thin film in the channel area. A metal layer is disposed over the source electrode, the drain electrode, the head region of the gate electrode, and portions of the nanomaterial thin film proximate the source electrode and the drain electrode in the channel area. | 10-04-2012 |
20120248417 | DOUBLE GATE NANOSTRUCTURE FET - A Field Effect Transistor (FET) semiconductor device comprising at least one nanostructure, comprises at least a uniformly doped beam-shaped nanostructure having two major surfaces, a gate electrode provided at either major surface of the nanostructure, and an insulating layer between each of the major surfaces of the nanostructure and the gate electrodes to form a double gate nanostructure pinch-off FET. It is an advantage of such FET that pinch-off voltage and current of the FET can be independently tuned. | 10-04-2012 |
20120261644 | STRUCTURE AND METHOD OF MAKING GRAPHENE NANORIBBONS - Disclosed is a ribbon of graphene less than 3 nm wide, more preferably less than 1 nm wide. In a more preferred embodiment, there are multiple ribbons of graphene each with a width of one of the following dimensions: the length of 2 phenyl rings fused together, the length of 3 phenyl rings fused together, the length of 4 phenyl rings fused together, and the length of 5 phenyl rings fused together. In another preferred embodiment the edges of the ribbons are parallel to each other. In another preferred embodiment, the ribbons have at least one arm chair edge and may have wider widths. | 10-18-2012 |
20120261645 | Graphene Device Having Physical Gap - Disclosed herein is a graphene device having a structure in which a physical gap is provided so that the off-state current of the graphene device can be significantly reduced without having to form a band gap in graphene, and thus the on/off current ratio of the graphene device can be significantly increased while the high electron mobility of graphene is maintained. | 10-18-2012 |
20120261646 | Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits one. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes. | 10-18-2012 |
20120261647 | METHODS OF FORMING STRUCTURES HAVING NANOTUBES EXTENDING BETWEEN OPPOSING ELECTRODES AND STRUCTURES INCLUDING SAME - A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed. | 10-18-2012 |
20120273762 | ELECTRONIC ARRANGEMENTS FOR PASSIVATED SILICON NANOWIRES - Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches. | 11-01-2012 |
20120280213 | Method of Fabricating Thin Film Transistor and Top-gate Type Thin Film Transistor - A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C. | 11-08-2012 |
20120286242 | NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES - A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion. | 11-15-2012 |
20120286243 | FIELD-EFFECT TRANSISTOR, SINGLE-ELECTRON TRANSISTOR AND SENSOR - A field-effect transistor or a single electron transistor is used as sensors for detecting a detection target such as a biological compound. A substrate has a first side and a second side, the second side being opposed to the first side. A source electrode is disposed on the first side of the substrate and a drain electrode disposed on the first side of the substrate, and a channel forms a current path between the source electrode and the drain electrode. An interaction-sensing gate is disposed on the second side of the substrate, the interaction-sensing gate having a specific substance that is capable of selectively interacting with the detection target. A gate for applying a gate voltage adjusts a characteristic of the transistor as the detection target changes the characteristic of the transistor when interacting with the specific substance. | 11-15-2012 |
20120292596 | Graphene Base Transistor Having Compositionally-Graded Collector Barrier Layer - A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer. | 11-22-2012 |
20120292597 | Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity. | 11-22-2012 |
20120292598 | EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS - A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks. | 11-22-2012 |
20120298965 | MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION - A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure. | 11-29-2012 |
20120305892 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING A DEVICE AND APPARATUS FOR MANUFACTURING A DEVICE - An electronic device comprises an in-plane component formed in an organic semiconductor layer, desirably graphene, on a flexible substrate. The component is formed using imprint lithography to create a trench through the organic semiconductor layer in a roll-to-roll process. The number of process steps required is limited to allow manufacture of the device in a single integrated apparatus. | 12-06-2012 |
20120305893 | TRANSISTOR DEVICE - The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×10 | 12-06-2012 |
20120313079 | GRAPHENE ELECTRONIC DEVICES HAVING MULTI-LAYERED GATE INSULATING LAYER - A graphene electronic device includes a multi-layered gate insulating layer between a graphene channel layer and a gate electrode. The multi-layered gate insulating layer includes an organic insulating layer and an inorganic insulating layer on the organic insulating layer. | 12-13-2012 |
20120319083 | NANOROD SEMICONDUCTOR DEVICE HAVING A CONTACT STRUCTURE, AND METHOD FOR MANUFACTURING SAME - Disclosed is a nanorod semiconductor device having a contact structure, and a method for manufacturing the same. The nanorod semiconductor device having a contact structure according to one embodiment of the present disclosure includes: a transparent wafer; a transparent electrode layer formed on the transparent wafer; a nanorod layer including a plurality of semiconductor nanorods doped with dopants having a first polarity and grown on the transparent electrode layer; and a single crystal semiconductor layer doped with dopants having a second polarity and forming a certain physical contact with the ends of the semiconductor nanorods. | 12-20-2012 |
20120319084 | PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer. | 12-20-2012 |
20120326126 | Graphene or Carbon Nanotube Devices with Localized Bottom Gates and Gate Dielectric - Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device. | 12-27-2012 |
20120326127 | COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURES - A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT. | 12-27-2012 |
20120326128 | GRAPHENE-LAYERED STRUCTURE, METHOD OF PREPARING THE SAME, AND TRANSPARENT ELECTRODE AND TRANSISTOR INCLUDING GRAPHENE-LAYERED STRUCTURE - A method of directly growing graphene of a graphene-layered structure, the method including ion-implanting at least one ion of a nitrogen ion and an oxygen ion on a surface of a silicon carbide (SiC) thin film to form an ion implantation layer in the SiC thin film; and heat treating the SiC thin film with the ion implantation layer formed therein to graphenize a SiC surface layer existing on the ion implantation layer. | 12-27-2012 |
20120326129 | METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES - An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene. | 12-27-2012 |
20130001516 | GRAPHITE AND/OR GRAPHENE SEMICONDUCTOR DEVICES - Various embodiments are provided for graphite and/or graphene based semiconductor devices. In one embodiment, a semiconductor device includes a semiconductor layer and a semimetal stack. In another embodiment, the semiconductor device includes a semiconductor layer and a zero gap semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the semiconductor layer, which forms a Schottky barrier. In another embodiment, a semiconductor device includes first and second semiconductor layers and a semimetal stack. In another embodiment, a semiconductor device includes first and second semiconductor layers and a zero gap semiconductor layer. The first semiconductor layer includes a first semiconducting material and the second semi conductor layer includes a second semiconducting material formed on the first semiconductor layer. The semimetal stack/zero gap semiconductor layer is formed on the second semiconductor layer, which forms a Schottky barrier. | 01-03-2013 |
20130001517 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses. | 01-03-2013 |
20130001518 | FABRICATION OF GRAPHENE NANOELECTRONIC DEVICES ON SOI STRUCTURES - A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an embodiment, the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-on-insulator layer on the buried oxide. A graphene layer is transferred onto the silicon-on-insulator layer. Source and drain regions are formed in the silicon-on-insulator layer, and a gate is formed above the graphene. In one embodiment, the processing includes growing a respective oxide layer on each of first and second silicon sections, and joining these silicon sections together via the oxide layers to form the silicon material. The processing, in an embodiment, further includes removing a portion of the first silicon section, leaving a residual silicon layer on the bonded oxide, and the graphene layer is positioned on this residual silicon layer. | 01-03-2013 |
20130001519 | GRAPHENE DEVICES WITH LOCAL DUAL GATES - An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer. | 01-03-2013 |
20130009133 | A GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE - A transistor structure is provided which includes a graphene layer located on an insulating layer, a first metal portion overlying a portion of the graphene layer, a second metal portion contacting and overhanging the first metal portion, a first electrode contacting a portion of the graphene layer and laterally offset from a first sidewall of the first metal portion by a lateral spacing, and a second electrode contacting another portion of the graphene layer and laterally offset from a second sidewall of the first metal portion by the lateral spacing. | 01-10-2013 |
20130015429 | ALL GRAPHENE FLASH MEMORY DEVICEAANM Hong; Augustin J.AACI Los AngelesAAST CAAACO USAAGP Hong; Augustin J. Los Angeles CA USAANM Kim; Ji-YoungAACI Los AngelesAAST CAAACO USAAGP Kim; Ji-Young Los Angeles CA USAANM Wang; Kang-LungAACI Santa MonicaAAST CAAACO USAAGP Wang; Kang-Lung Santa Monica CA US - A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers. | 01-17-2013 |
20130037781 | FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A field-effect transistor includes a semiconductor layer containing carbon nanomaterials; a first electrode and a second electrode formed in contact with the semiconductor layer; a third electrode for controlling current flowing between the first electrode and the second electrode; and an insulating layer formed between the semiconductor layer and the third electrode. The insulating layer contains an aromatic polyamide comprising a substituent containing 1 to 20 carbon atoms. | 02-14-2013 |
20130048949 | Carbonaceous Nanomaterial-Based Thin-Film Transistors - Disclosed are thin film transistor devices incorporating a thin film semiconductor derived from carbonaceous nanomaterials and a dielectric layer composed of an organic-inorganic hybrid self-assembled multilayer. | 02-28-2013 |
20130048950 | ON-DEMAND NANOELECTRONICS PLATFORM - A reconfigurable device includes a first insulating layer, a second insulating layer, and a nanoscale quasi one- or zero-dimensional electron gas region disposed at an interface between the first and second insulating layers. The device is reconfigurable by applying an external electrical field to the electron gas, thereby changing the conductivity of the electron gas region. A method for forming and erasing nanoscale-conducting structures employs tools, such as the tip of a conducting atomic force microscope (AFM), to form local electric fields. The method allows both isolated and continuous conducting features to be formed with a length well below 5 nm. | 02-28-2013 |
20130048951 | GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER - According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer. | 02-28-2013 |
20130048952 | HOLE DOPING OF GRAPHENE - An article includes a layer of graphene having a first work function; and a metal oxide film disposed on the layer of graphene, the metal oxide film having a second work function greater than the first work function. Electrons are transferred from the layer of graphene to the metal oxide film, forming a hole accumulation layer in the layer of graphene. | 02-28-2013 |
20130062594 | METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE - A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate. | 03-14-2013 |
20130069041 | METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME - A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer. | 03-21-2013 |
20130075701 | PROGRAMMABLE ARRAY OF SILICON NANOWIRE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed. | 03-28-2013 |
20130075702 | Tunable Hot-Electron Transfer Within a Nanostructure - Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element. | 03-28-2013 |
20130075703 | PEPTIDE NANOSTRUCTURES ENCAPSULATING A FOREIGN MATERIAL AND METHOD OF MANUFACTURING SAME - A composition comprising a material at least partially enclosed by a tubular, spherical or planar nanostructure composed of a plurality of peptides, wherein each of the plurality of peptides includes no more than 4 amino acids and whereas at least one of the 4 amino acids is an aromatic amino acid. | 03-28-2013 |
20130082242 | TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided. | 04-04-2013 |
20130082243 | TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided. | 04-04-2013 |
20130092902 | NANOWIRE TUNNELING FIELD EFFECT TRANSISTOR WITH VERTICAL STRUCTURE AND A MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly. | 04-18-2013 |
20130105765 | Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same | 05-02-2013 |
20130119348 | Radio Frequency Devices Based on Carbon Nanomaterials - RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive. | 05-16-2013 |
20130119349 | GRAPHENE TRANSISTOR HAVING AIR GAP, HYBRID TRANSISTOR HAVING THE SAME, AND METHODS OF FABRICATING THE SAME - A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode. | 05-16-2013 |
20130119350 | SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME - A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons. | 05-16-2013 |
20130134391 | Reducing Contact Resistance for Field-Effect Transistor Devices - A method and an apparatus for doping a graphene and nanotube thin-film transistor field-effect transistor device to decrease contact resistance with a metal electrode. The method includes selectively applying a dopant to a metal contact region of a graphene and nanotube field-effect transistor device to decrease the contact resistance of the field-effect transistor device. | 05-30-2013 |
20130134392 | Doping Carbon Nanotubes and Graphene for Improving Electronic Mobility - A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device. | 05-30-2013 |
20130134393 | Nanotube Field Effect Devices and Methods of Making Same - Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. An electromechanically-deflectable, nanotube switching element is formed over the field effect device. Terminals and corresponding interconnect are provided to correspond to each of the source, drain and gate such that the nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal, and such that the others of said source, drain and gate are directly connected to their corresponding terminals. | 05-30-2013 |
20130134394 | Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes. | 05-30-2013 |
20130140526 | HEXAGONAL BORON NITRIDE SHEET, METHOD OF PREPARING THE HEXAGONAL BORON NITRIDE SHEET, AND ELECTRONIC DEVICE INCLUDING THE HEXAGONAL BORON NITRIDE SHEET - A hexagonal boron nitride sheet having: a two-dimensional planar structure with a sp | 06-06-2013 |
20130146847 | GRAPHENE FIELD EFFECT TRANSISTOR - Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material. | 06-13-2013 |
20130161587 | GRAPHENE DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer. | 06-27-2013 |
20130161588 | Implant Free Quantum Well Transistor, Method for Making Such an Implant Free Quantum Well Transistor and Use of Such an Implant Free Quantum Well Transistor - An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region. | 06-27-2013 |
20130168640 | INVERTER DEVICE, NAND DEVICE, NOR DEVICE, AND LOGIC DEVICE INCLUDING THE SAME - An inverter device including a tunable diode device and a diode device that includes a control terminal connected to an input terminal of the inverter device, an anode terminal connected to a high-level voltage terminal, and a cathode terminal connected to an output terminal of the inverter device, wherein the diode device is configured to turn on or off according to a voltage applied to the control terminal. | 07-04-2013 |
20130175502 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region. | 07-11-2013 |
20130175503 | Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process - A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires. | 07-11-2013 |
20130175504 | OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS - An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer. | 07-11-2013 |
20130175505 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode. | 07-11-2013 |
20130175506 | THREE-DIMENSIONAL GRAPHENE SWITCHING DEVICE - A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate. | 07-11-2013 |
20130181189 | Logic Elements Comprising Carbon Nanotube Field Effect Transistor (CNTFET) Devices and Methods of Making Same - Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs. | 07-18-2013 |
20130193410 | NANO-DEVICES FORMED WITH SUSPENDED GRAPHENE MEMBRANE - Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices. | 08-01-2013 |
20130193411 | GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a graphene device may include forming a device portion including a graphene layer on the first substrate; attaching a second substrate on the device portion of the first substrate; and removing the first substrate. The removing of the first substrate may include etching a sacrificial layer between the first substrate and the graphene layer. After removing the first substrate, a third substrate may be attached on the device portion. After attaching the third substrate, the second substrate may be removed. | 08-01-2013 |
20130193412 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer. | 08-01-2013 |
20130214252 | CONTROLLED SYNTHESIS OF MONOLITHICALLY-INTEGRATED GRAPHENE STRUCTURE - In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene. | 08-22-2013 |
20130214253 | MANUFACTURING METHOD OF GRAPHENE SUBSTRATE AND GRAPHENE SUBSTRATE - The invention provides a manufacturing method of a graphene-on-insulator substrate which is mass productive, of high quality, and yet is directly usable for manufacture of semiconductor devices at a low manufacturing cost. According to the manufacturing method of a graphene substrate of the invention, a metal layer and a carbide layer are heated with the metal layer in contact with the carbide layer so that carbon in the carbide layer is dissolved into the metal layer, and then the metal layer and the carbide layer are cooled so that the carbon in the metal layer is segregated as graphene on the surface of the carbide layer. | 08-22-2013 |
20130221329 | Graphene Device - An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc. | 08-29-2013 |
20130240839 | Graphene Channel-Based Devices and Methods for Fabrication Thereof - Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel. | 09-19-2013 |
20130248823 | SEMICONDUCTOR DEVICE INCLUDING GRAPHENE LAYER AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts. | 09-26-2013 |
20130248824 | GRAHENE FIELD EFFECT TRANSISTOR - Graphene FETs exhibit low power consumption and high switching rates taking advantage of the excellent mobility in graphene deposited on a rocksalt oxide (111) by chemical vapor deposition, plasma vapor deposition or molecular beam epitaxy. A source, drain and electrical contacts are formed on the graphene layer. These devices exhibit band gap phenomena on the order of greater than about 0.5 eV, easily high enough to serve as high speed low power logic devices. Integration of this construction technology, based on the successful deposition of few layer graphene on the rocksalt oxide (111) with SI CMOS is straightforward. | 09-26-2013 |
20130270521 | GRAPHENE TRANSISTOR GATED BY CHARGES THROUGH A NANOPORE FOR BIO-MOLECULAR SENSING AND DNA SEQUENCING - A technique for a nanodevice is provided. A reservoir is separated into two parts by a membrane. A nanopore is formed through the membrane, and the nanopore connects the two parts of the reservoir. The nanopore and the two parts of the reservoir are filled with ionic buffer. The membrane includes a graphene layer and insulating layers. The graphene layer is wired to first and second metal pads to form a graphene transistor in which transistor current flowing through the graphene transistor is modulated by charges passing through the nanopore. | 10-17-2013 |
20130270522 | RESONANCE TUNNELING DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are a resonance tunneling device and a method of manufacturing the resonance tunneling device. The resonance tunneling device includes a substrate, a plurality of electrodes disposed on the substrate, and a nanoparticle layer disposed between the electrodes, and doped with an impurity. The nanoparticle layer uses the impurity to exhibit resonance tunneling where a current peak occurs at a target bias voltage applied between the electrodes. | 10-17-2013 |
20130277644 | GRAPHENE SWITCHING DEVICE INCLUDING TUNABLE BARRIER - A graphene switching device includes a first electrode and an insulating layer in first and second regions of the semiconductor substrate, respectively, a plurality of metal particles on a surface of the semiconductor substrate between the first and second regions, a graphene layer on the plurality of metal particles and extending on the insulating layer, a second electrode on the graphene layer in the second region and configured to face the insulating layer, a gate insulating layer configured to cover the graphene layer, and a gate electrode on the gate insulating layer. The semiconductor substrate forms an energy barrier between the graphene layer and the first electrode. | 10-24-2013 |
20130285018 | PHOTODETECTOR USING GRAPHENE AND METHOD OF MANUFACTURING THE SAME - A photodetector using graphene includes: a gate electrode; a graphene channel layer which is opposite to and spaced apart from the gate electrode and does not have π-binding; a first electrode which contacts a first side of the graphene channel layer; and a second electrode which contacts a side of the graphene channel layer, where the first and second sides are opposite to each other, and where the graphene channel layer includes a first graphene layer and a first nanoparticle disposed on the first graphene layer. The first graphene layer may include a single graphene layer, or the first graphene layer may include a plurality of single graphene layers, which is sequentially stacked and does not have π-binding. | 10-31-2013 |
20130285019 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region. | 10-31-2013 |
20130285020 | Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated With a Replacement Gate Process - A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires. | 10-31-2013 |
20130299782 | GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES - Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface. | 11-14-2013 |
20130306937 | 3D NANO-ELECTRO-MECHANICAL MULTIPLE-STATE CARBON NANOTUBE DEVICE STRUCTURES AND METHODS OF FABRICATION - A 3D M-CNT structure with at least one tri-state CNT NEM switch comprising at least an electrode as a source, an electrode as a gate and an electrode as a drain, a conductive carbon nanotube which is able to take three positions depending on a voltage application to said electrodes. | 11-21-2013 |
20130313522 | GRAPHENE-BASED SEMICONDUCTOR DEVICE - A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer. | 11-28-2013 |
20130313523 | GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a method of fabricating a graphene electronic device and the graphene electronic device fabricated thereby. The method may include forming a first electrode and a second electrode spaced apart from each other, on a substrate, forming supporting patterns on the first electrode and the second electrode, coating the supporting patterns with graphene-oxide-containing solution to form composite patterns, and separating the supporting patterns from the composite patterns. | 11-28-2013 |
20130313524 | AMBIPOLAR SILICON NANOWIRE FIELD EFFECT TRANSISTOR - This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts. | 11-28-2013 |
20130313525 | Nanowire-based Transistor, Method for Fabricating the Transistor, Semiconductor Component Incorporating the Transistor, Computer Program and Storage Medium Associated with the Fabrication Method - The transistor ( | 11-28-2013 |
20130320303 | Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes - Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric. | 12-05-2013 |
20130328017 | SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS - A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer. | 12-12-2013 |
20130334498 | TRANSPORT CONDUITS FOR CONTACTS TO GRAPHENE - An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart relative to one another on the substrate. The graphene layer comprises at least a first portion and a second portion, the first portion being in contact with the first source/drain region and the second portion being in contact with the second source/drain region. One or more cuts are formed in at least one of the first and second portions of the graphene layer. The apparatus allows for lowered contact resistance in graphene/metal contacts. | 12-19-2013 |
20130334499 | METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE - A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate. | 12-19-2013 |
20130341596 | NANOWIRE FET AND FINFET - A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region. | 12-26-2013 |
20140001441 | INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES | 01-02-2014 |
20140014904 | Replacement Contacts for All-Around Contacts - In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device. | 01-16-2014 |
20140014905 | FIELD EFFECT TRANSISTOR USING GRAPHENE - According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode. | 01-16-2014 |
20140021446 | TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene. | 01-23-2014 |
20140027715 | P-TYPE GRAPHENE BASE TRANSISTOR - A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer. | 01-30-2014 |
20140034909 | THIN-FILM BALLISTIC SEMICONDUCTOR WITH ASYMMETRIC CONDUCTANCE - A thermoelectric structure comprises a thin thermoelectric film extending in a plane between parallel first and second shorting bars. A plurality of curved ballistic scattering guides are formed in a magnetic field region of the thin thermoelectric film subjected to a local, substantially uniform, nonzero magnetic field normal to the plane of the thin thermoelectric film. | 02-06-2014 |
20140042393 | Graphene and Nanotube/Nanowire Transistor with a Self-Aligned Gate Structure on Transparent Substrates and Method of Making Same - Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes. | 02-13-2014 |
20140048774 | GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES - Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed. | 02-20-2014 |
20140054550 | METHOD FOR N-DOPING GRAPHENE - The present disclosure provides an n-doping method of graphene, including supplying a reaction gas containing a carbon source and heat to a substrate and reacting to grow graphene on the substrate; and n-doping the graphene by a doping solution containing an n-type dopant or a vapor containing an n-type dopant, an n-doped graphene produced by the method, and a device including the n-doped graphene. | 02-27-2014 |
20140061590 | GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME - The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from each other, forming a graphene layer having a portion defined as an active area between the first and second metal pads on the insulating material layer, forming third and fourth metal pads on the graphene layer spaced apart from each other with the active area therebetween, the third and fourth metal pads extending above the first metal pad and the second metal pad, respectively, forming a first protection layer to cover all the first and second metal pads, the graphene layer, and the third and fourth metal pads, and etching an entire surface of the first protection layer until only a residual layer made of a material for forming the first protection layer remains on the active area. | 03-06-2014 |
20140070169 | Separated Carbon Nanotube-Based Active Matrix Organic Light-Emitting Diode Displays - A separated carbon nanotube-based active matrix organic light-emitting diode (AMOLED) device including a substrate and transistors. Each transistor includes an individual back gate patterned on the substrate and a gate dielectric layer disposed over the substrate. An active channel including a network of separated semiconducting nanotubes is disposed over a functionalized surface of the gate dielectric layer. A source contact and a drain contact are formed on two ends of the active channel, with the network of separated nanotubes between the source contact and the drain contact. An organic light-emitting diode (OLED) display device is coupled to the drain of one of the transistors. A system includes a display control circuit having a substrate, with scan lines, data lines, and AMOLED devices formed on the substrate, with each AMOLED device coupled to one of the scan lines and one of the data lines. | 03-13-2014 |
20140070170 | FIELD EFFECT TRANSISTOR FOR CHEMICAL SENSING USING GRAPHENE, CHEMICAL SENSOR USING THE TRANSISTOR AND METHOD FOR PRODUCING THE TRANSISTOR - A field effect transistor ( | 03-13-2014 |
20140077160 | TFT ARRAY SUBSTRATE AND A METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - Embodiments of the present invention provide a thin film transistor (TFT) array substrate and a method for manufacturing the same and a display device. The TFT array substrate improves a structure of a TFT array substrate and has a small thickness, and process flow is simplified. The method for manufacturing a thin film transistor (TFT) array substrate comprises: obtaining a gate line and a gate electrode through a first patterning process on a glass substrate; forming a gate insulating layer on the gate line and the gate electrode; forming a graphene layer on the gate insulating layer, and obtaining a semiconductor active layer over the gate electrode by a second patterning process and a hydrogenation treatment; obtaining a data line, a source electrode, a drain electrode and a pixel electrode which are located on the same layer by a third patterning process; and forming a protection layer on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode. | 03-20-2014 |
20140077161 | HIGH PERFORMANCE GRAPHENE TRANSISTORS AND FABRICATION PROCESSES THEREOF - A graphene transistor includes: (1) a substrate; (2) a source electrode disposed on the substrate; (3) a drain electrode disposed on the substrate; (4) a graphene channel disposed on the substrate and extending between the source electrode and the drain electrode; and (5) a top gate disposed on the graphene channel and including a nanostructure. | 03-20-2014 |
20140077162 | DOPED GRAPHENE ELECTRONIC MATERIALS - A graphene substrate is doped with one or more functional groups to form an electronic device. | 03-20-2014 |
20140084249 | STACKED NANOWIRE FIELD EFFECT TRANSISTOR - A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate. | 03-27-2014 |
20140084250 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer. | 03-27-2014 |
20140091280 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed. | 04-03-2014 |
20140097404 | MEMORY DEVICES INCLUDING GRAPHENE SWITCHING DEVICES - A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element. | 04-10-2014 |
20140103296 | GRAPHENE NANORIBBON SENSOR - Provided is a graphene nanoribbon sensor. The sensor includes a substrate, a graphene layer formed on the substrate in a first direction, and an upper dielectric layer on the graphene layer. Here, the graphene layer may have a plurality of electrode regions respectively separated in the first direction and a channel between the plurality of electrode regions. | 04-17-2014 |
20140103297 | ORGANIC MATERIAL-BASED GRAPHITIC MATERIAL - Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template. | 04-17-2014 |
20140103298 | GRAPHENE-BASED FILMS IN SENSOR APPLICATIONS - An environmental sensor comprises a graphene thin-film as an environmentally responsive material. Such graphene films exhibit negative temperature coefficients (NTC), resulting in rapid decreases in electrical resistance as temperature increases, as well as a much faster response time than any other NTC material reported in the literature. The graphene film is also mechanically stable under bending, and, therefore, can be adapted for use in a mechanical sensor or pressure sensor, because the electrical resistance of the graphene film changes upon deflection and/or changes in pressure. The electrical resistance of the graphene film also increases in response to increases in environmental humidity. The electrical resistance changes of the graphene film can also be used as a sensing mechanism for changes in chemical and biological parameters in the environment of the sensor. | 04-17-2014 |
20140103299 | NANOTUBE ARRAY ELECTRONIC AND OPTO-ELECTRONIC DEVICES - Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits. | 04-17-2014 |
20140110670 | DOPED GRAPHENE STRUCTURE COMPRISING HYDROPHOBIC ORGANIC MATERIAL, METHOD FOR PREPARING THE SAME, AND TRANSPARENT ELECTRODE, DISPLAY DEVICE AND SOLAR CELL COMPRISING THE ELECTRODE - A hydrophobic organic layer may be formed on a surface of a graphene doped with a dopant to improve stability of the doped graphene with respect to moisture and temperature. Thus, the transparent electrode having the doped graphene containing the hydrophobic organic layer may be usefully applied in solar cells or display devices. | 04-24-2014 |
20140110671 | LIGHT SOURCE MODULE AND ILLUMINATION DEVICE INCLUDING A THERMOELECTRIC DEVICE - A light source module includes at least one light emitting device and a thermoelectric device coupled to the at least one light emitting device. The thermoelectric devices includes a plurality of conductive layers, made of a resin material containing a thermoelectric conversion material, and a plurality of insulating layers laminated to the conductive layers. The thermoelectric device generates electricity by using heat from the light emitting device. | 04-24-2014 |
20140117312 | CARBON NANOTUBE DEVICES WITH UNZIPPED LOW-RESISTANCE CONTACTS - A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region. | 05-01-2014 |
20140117313 | GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER - According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode. | 05-01-2014 |
20140124737 | CARBON NANOTUBE NETWORK THIN-FILM TRANSISTORS ON FLEXIBLE/STRETCHABLE SUBSTRATES - This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network. | 05-08-2014 |
20140124738 | HIGH TEMPERATURE SUPERFLUIDITY SYSTEM - A small gap semiconductor system comprises: two parallel semiconductor sheets formed of atomically thin small gap semiconductor, one sheet containing electrons and the other containing holes; a dielectric insulating barrier arranged parallel to and separating the two semiconductor sheets; independent electrical contacts to each of the semiconductor sheets; two dielectric layers above and below the two semiconductor sheets respectively; and two conducting gates sandwiching the two semiconductor sheets and separated from the respective semiconductor sheets by the respective dielectric layers. | 05-08-2014 |
20140131662 | Graphene Formation on Dielectrics and Electronic Devices Formed Therefrom - Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene. | 05-15-2014 |
20140138623 | TRANSISTORS FROM VERTICAL STACKING OF CARBON NANOTUBE THIN FILMS - A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region. | 05-22-2014 |
20140138624 | VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR - A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet. | 05-22-2014 |
20140138625 | TRANSISTORS FROM VERTICAL STACKING OF CARBON NANOTUBE THIN FILMS - A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region. | 05-22-2014 |
20140138626 | VERTICAL STACKING OF GRAPHENE IN A FIELD-EFFECT TRANSISTOR - A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet. | 05-22-2014 |
20140145148 | FIELD EFFECT TRANSISTOR USING GRAPHENE, PHOSPHORUS-DOPED GRAPHENE, AND METHODS OF PRODUCING THE SAME - A field effect transistor using a channel layer including a phosphorus-doped graphene and a method of fabricating the same are provided. Further, a phosphorus-doped graphene and a method of producing the same are provided. The field effect transistor includes: a source electrode and a drain electrode formed on a substrate; and a channel layer comprising a phosphorus-doped graphene, the channel layer electrically connected to the source electrode and the drain electrode. | 05-29-2014 |
20140151640 | SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR - A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate. | 06-05-2014 |
20140151641 | 3D RFICS WITH ULTRA-THIN SEMICONDUCTOR MATERIALS - Three-dimensional integrated circuits and method for fabricating the same include forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions. | 06-05-2014 |
20140151642 | 3D RFICS WITH ULTRA-THIN SEMICONDUCTOR MATERIALS - Three-dimensional integrated circuits include an active layer having one or more active components formed with carbon-based channel material; a passive layer monolithically formed with the active layer, having one or more sub-layers and each sub-layer having one or more passive components, where the passive components have monolithically formed vertical interconnects to components on other layers; and a surface layer monolithically formed with the passive layer, including one or more surface components connected to one or more of the passive components through monolithically formed vias. | 06-05-2014 |
20140151643 | SELF-ALIGNED DOUBLE-GATE GRAPHENE TRANSISTOR - A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate. | 06-05-2014 |
20140158987 | METHODS FOR INTEGRATING AND FORMING OPTICALLY TRANSPARENT DEVICES ON SURFACES - An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches. | 06-12-2014 |
20140158988 | GRAPHENE TRANSISTOR - Disclosed is a graphene transistor. The graphene transistor includes a source electrode, a drain electrode, a graphene layer, an insulating layer, a gate electrode and at least one doping layer. The graphene layer is disposed between the source electrode and the drain electrode. The gate electrode is separated from the graphene layer, the source electrode and the drain electrode by the insulating layer. The doping layer is disposed on the graphene layer or beneath the graphene layer for providing dopants for the graphene layer. The doping layer includes nonstoichiometric compounds. The graphene transistor of the present invention has a superior air stability and is not easily affected by environment. | 06-12-2014 |
20140158989 | ELECTRONIC DEVICE INCLUDING GRAPHENE - According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10 | 06-12-2014 |
20140166982 | ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE - A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed. | 06-19-2014 |
20140166983 | ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE - A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed. | 06-19-2014 |
20140183453 | FIELD EFFECT TRANSISTOR HAVING DOUBLE TRANSITION METAL DICHALCOGENIDE CHANNELS - A field effect transistor (FET) includes first and second channels stacked on a substrate, the first and second channels formed of a transition metal dichalcogenide, a source electrode and a drain electrode contacting both the first channel and the second channel, each of the source electrode and the drain electrode having one end between the first channel and the second channel, and a first gate electrode corresponding to at least one of the first channel and the second channel. | 07-03-2014 |
20140191197 | AMORPHOUS MULTI-COMPONENT METALLIC THIN FILMS FOR ELECTRONIC DEVICES - An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode. | 07-10-2014 |
20140191198 | GRAPHENE ELECTRONIC DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene electronic device includes: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer. | 07-10-2014 |
20140191199 | NANOSCALE QCA-BASED LOGIC GATES IN GRAPHENE TECHNOLOGY - QCA assemblies, in which basic cells are formed on the basis of graphene in order to provide a coupling field distribution in the form of an electrostatic field, a magnetic field, and the like which allows a unique association between field distribution and logic state. | 07-10-2014 |
20140197377 | CMOS NANOWIRE STRUCTURE - Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire. | 07-17-2014 |
20140209863 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type which is a reverse conductive type of the first conductive type, the first conductive type first diffusion layer and the second conductive type diffusion layer being spaced apart and provided in a semiconductor layer, a pocket region of the second conductive type which is provided on a surface portion of the semiconductor layer adjacently to the first diffusion layer, and a first extension region of the first conductive type which is provided in the semiconductor layer to cover at least a portion of the pocket region. A second diffusion layer side end portion of the first extension region is positioned closer to a second diffusion layer side than a second diffusion layer side end portion of the pocket region. | 07-31-2014 |
20140209864 | Nanowire Capacitor for Bidirectional Operation - A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device. | 07-31-2014 |
20140209865 | CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS - Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor. | 07-31-2014 |
20140217364 | Diode Structure and Method for Wire-Last Nanomesh Technologies - In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack. | 08-07-2014 |
20140231751 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire. | 08-21-2014 |
20140231752 | GRAPHENE DEVICE AND ELECTRONIC APPARATUS - A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor. | 08-21-2014 |
20140239256 | METHOD OF MANUFACTURING GRAPHENE LAMINATED STRUCTURE, GRAPHENE LAMINATED STRUCTURE, AND ELECTRONIC DEVICE INCLUDING THE GRAPHENE LAMINATED STRUCTURE - A method of manufacturing a graphene laminated structure includes plasma-treating a surface of a hexagonal boron nitride sheet using a fluorine-based gas plasma, depositing the hexagonal boron nitride sheet on a graphene sheet, and forming an insulating layer on a surface of the surface-treated hexagonal boron nitride sheet. | 08-28-2014 |
20140239257 | GRAPHENE HETEROSTRUCTURE FIELD EFFECT TRANSISTORS - A field effect transistor includes a substrate, a first graphene (Gr) layer on the substrate, a second graphene (Gr) layer on the substrate, a fluorographene (GrF) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts. | 08-28-2014 |
20140246651 | GROWN NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallised semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 09-04-2014 |
20140264280 | NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS - A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented. | 09-18-2014 |
20140264281 | Channel-Last Methods for Making FETS - Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts. | 09-18-2014 |
20140264282 | HETEROGENEOUS LAYERED STRUCTURE, METHOD OF PREPARING THE HETEROGENEOUS LAYERED STRUCTURE, AND ELECTRONIC DEVICE INCLUDING THE HETEROGENEOUS LAYERED STRUCTURE - A method of manufacturing a heterogeneous layered structure includes growing a hexagonal boron nitride sheet directly on a metal substrate in a chamber, increasing a temperature of the chamber to about 300° C. to about 1500° C., and forming a graphene sheet on the hexagonal boron nitride sheet by supplying a carbon source into the chamber while thermally treating the hexagonal boron nitride sheet at the increased temperature. | 09-18-2014 |
20140284553 | CNT-BASED ELECTRONIC AND PHOTONIC DEVICES - The carbon nanotube-based electronic and photonic devices are disclosed. The devices are united by the same technology as well as similar elements for their fabrication. The devices consist of the vertically grown semiconductor nanotube having two Schottky barriers at the nanotube ends and one Schottky barrier at the middle of the nanotube. Depending on the Schottky barrier heights and bias arrangements, the disclosed devices can operate either as transistors, CNT MESFET and CNT Hot Electron Transistor, or as a CNT Photon Emitter. | 09-25-2014 |
20140299839 | ELECTRICAL DEVICES WITH GRAPHENE ON BORON NITRIDE - Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (GFETs) including boron nitride. | 10-09-2014 |
20140299840 | GRAPHENE LAMINATE WITH BAND GAP - A graphene laminate includes a first piezoelectric material layer having a negatively-charged surface and a positively-charged surface, a first graphene layer under the first piezoelectric material layer, the first graphene layer contacting the positively-charged surface of the first piezoelectric material layer, a second graphene layer underlying the first graphene layer, and a second piezoelectric material layer under the second graphene layer, the second piezoelectric material layer having a negatively-charged surface and a positively-charged surface, the negatively-charged surface contacting the second graphene layer. | 10-09-2014 |
20140299841 | GRAPHENE BASED FIELD EFFECT TRANSISTOR - A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance. | 10-09-2014 |
20140306184 | TWO-DIMENSIONAL MATERIAL CONTAINING ELECTRONIC COMPONENTS - In various embodiments, an electronic component is provided. The electronic component may include a dielectric structure; and a two-dimensional material containing structure over the dielectric structure. The dielectric structure is doped with dopants to change the electric characteristic of the two-dimensional material containing structure. | 10-16-2014 |
20140306185 | THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME - A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The insulating layer has a first surface and a second surface opposite to the first surface. The gate electrode is located on the first surface of the insulating layer. The source electrode, the drain electrode, and the semiconductor layer are located on the second surface of the insulating layer. The gate electrode, the source electrode, and the drain electrode include a first carbon nanotube layer. The semiconductor layer includes a second carbon nanotube layer. A first film resistor of the first carbon nanotube layer is smaller than or equal to 10 kΩ per square. A second film resistor of the second carbon nanotube layer is greater than or equal to 100 kΩ per square. | 10-16-2014 |
20140312305 | PLASMONIC GRAPHENE DEVICES - An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array. | 10-23-2014 |
20140312306 | PLASMONIC GRAPHENE DEVICES - An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array. | 10-23-2014 |
20140312307 | PLASMONIC GRAPHENE DEVICES - An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array. | 10-23-2014 |
20140312308 | PLASMONIC GRAPHENE DEVICES - An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array. | 10-23-2014 |
20140312309 | PLASMONIC GRAPHENE DEVICES - An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array. | 10-23-2014 |
20140312310 | Semiconductor Power Device - A vertical semiconductor power field effect transistor device includes a SiC semiconductor body, at least part of the SiC semiconductor body constituting a drift zone, a first contact at a first side of the SiC semiconductor body, the first contact being a contact to one of a source and drain of the field effect transistor device, a second contact at a second side of the SiC semiconductor body, the first side being opposite the second side, the second contact being a contact to the other one of the source and drain, and a current path between the first contact and the second contact and which includes at least one graphene layer. A lateral channel region at the first side includes the at least one graphene layer. | 10-23-2014 |
20140326954 | INTEGRATED NANOWIRE/NANOSHEET NANOGAP AND NANOPORE FOR DNA AND RNA SEQUENCING - A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current. | 11-06-2014 |
20140326955 | PLANAR TRANSISTORS WITH NANOWIRES COINTEGRATED ON A SOI UTBOX SUBSTRATE - Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor. | 11-06-2014 |
20140332757 | GRAPHENE PHOTODETECTOR - A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device. | 11-13-2014 |
20140339506 | FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE - A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate. | 11-20-2014 |
20140339507 | STACKED SEMICONDUCTOR NANOWIRES WITH TUNNEL SPACERS - A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material. | 11-20-2014 |
20140346442 | MATERIALS AND METHODS FOR THE PREPARATION OF NANOCOMPOSITES - Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices. | 11-27-2014 |
20140346443 | PLASMONIC GRAPHENE DEVICES - An integrated graphene-based structure comprises an N-dimensional array of elements formed on a surface of a substrate. The N-dimensional array of elements includes a plurality of rows. Each respective row in the plurality of rows comprises a corresponding plurality of elements formed along a first dimension. Each element in the corresponding plurality of elements comprising at least one graphene stack and separated from an adjacent element along the first dimension by a first average spatial separation thereby resulting in a first periodicity in lateral spacing along the first dimension. Each respective row in the plurality of rows is separated from an adjacent row along a second dimension by a second average spatial separation, thereby resulting in a second periodicity in lateral spacing along the second dimension. The N-dimensional array exhibits a set of characteristic electromagnetic interference properties in response to electromagnetic radiation incident on the N-dimensional array. | 11-27-2014 |
20140353589 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140353590 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140353591 | TRANSISTOR USING SINGLE CRYSTAL SILICON NANOWIRE AND METHOD FOR MANUFACTURING SAME - A transistor using a single crystal silicon nanowire and a method for fabricating the transistor is disclosed. The transistor using a single crystal silicon nanowire comprises a substrate and a single crystal silicon nanowire formed on the substrate. Here, the single crystal silicon nanowire comprises a source region and a drain region formed longitudinally with the single crystal silicon nanowire and separate from each other, and a channel region located between the source region and the drain region, wherein the perpendicular thickness of the channel region to the longitudinal direction is thinner than the thickness of the source region and the drain region. | 12-04-2014 |
20140353592 | THIN FILM TRANSISTOR USING A CARBON NANOTUBE AS A CHANNEL AND A DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other. | 12-04-2014 |
20140367642 | Process for Preparing Graphene on a SiC Substrate Based on Metal Film-Assisted Annealing - Provided is a process for preparing graphene on a SiC substrate, based on metal film-assisted annealing, comprising the following steps: subjecting a SiC substrate to a standard cleaning process; placing the cleaned SiC substrate into a quartz tube and heating the quartz tube up to a temperature of 750 to 1150° C.; introducing CCl | 12-18-2014 |
20140374702 | CARBON NANOSTRUCTURE DEVICE FABRICATION UTILIZING PROTECT LAYERS - Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing. | 12-25-2014 |
20150021553 | JUNCTIONLESS ACCUMULATION-MODE DEVICE ISOLATED FROM SEMICONDUCTIVE SUBSTRATE BY REVERSE-BIAS JUNCTION - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 01-22-2015 |
20150021554 | DIRECT FORMATION OF GRAPHENE ON SEMICONDUCTOR SUBSTRATES - The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate. | 01-22-2015 |
20150048312 | SOLUTION-ASSISTED CARBON NANOTUBE PLACEMENT WITH GRAPHENE ELECTRODES - A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween. | 02-19-2015 |
20150053927 | STRETCHABLE TRANSISTORS WITH BUCKLED CARBON NANOTUBE FILMS AS CONDUCTING CHANNELS - Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains. | 02-26-2015 |
20150053928 | SILICON AND SILICON GERMANIUM NANOWIRE FORMATION - Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. | 02-26-2015 |
20150053929 | VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY - A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process. | 02-26-2015 |
20150053930 | ATOMIC LAYER DEPOSITION OF SELECTED MOLECULAR CLUSTERS - Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation. | 02-26-2015 |
20150060768 | METHOD TO IMPROVE PERFORMANCE CHARACTERISTICS OF TRANSISTORS COMPRISING GRAPHENE AND OTHER TWO-DIMENSIONAL MATERIALS - The electrical properties of graphene and molybdenum sulfide semiconductor devices are improved by incorporating a fluoropolymer capping layer that is in contact with the graphene or molybdenum sulfide layer. | 03-05-2015 |
20150060769 | INFRARED DETECTOR - An infrared detector includes a detecting element, a first electrode and a second electrode. The detecting element includes an absorbing part and a non-absorbing part. A first end is located in the absorbing part. A second end is located in the non-absorbing part. An angle between the absorbing part and the non-absorbing part is less than 90 degrees. A first electrode is electrically connected with the first end. A second electrode is electrically connected with the second end. | 03-05-2015 |
20150060770 | Light Emitting Diode (LED) Using Carbon Materials - Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material. | 03-05-2015 |
20150069329 | NANOPORE DEVICE INCLUDING GRAPHENE NANOPORE AND METHOD OF MANUFACTURING THE SAME - Provided are a nanopore device with resolution improved by graphene nanopores, and a method of manufacturing the same. The nanopore device includes: a first insulating layer; a graphene layer disposed on the first insulating layer and having a nanopore formed at a center portion of the graphene layer; and first and second electrode layers disposed respectively at both sides of the nanopore on a top surface of the graphene layer, wherein a center region of the first insulating layer is removed such that the center portion of the graphene layer is exposed to the outside. | 03-12-2015 |
20150069330 | NANOWIRE FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME - Provided are a nanowire field-effect transistor and a method for manufacturing the same. The nanowire field-effect transistor can enable a source region to be positioned, with respect to an asymmetrical nanowire channel, adjacent to a region in which the diameter of the nanowire channel is large, can enable a drain region to be positioned adjacent to a region in which the diameter of the nanowire channel is small, can enable an ON current to be increased in a state in which a threshold voltage level is kept the same, and can enable the current drivability of a gate electrode to be improved. | 03-12-2015 |
20150076450 | NANOWIRE DEVICE HAVING GRAPHENE TOP AND BOTTOM ELECTRODES AND METHOD OF MAKING SUCH A DEVICE - A composition of matter comprising a plurality of nanowires on a substrate, said nanowires having been grown epitaxially on said substrate in the presence of a metal catalyst such that a catalyst deposit is located at the top of at least some of said nanowires, wherein said nanowires comprise at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group IV element; and wherein a graphitic layer is in contact with at least some of the catalyst deposits on top of said nanowires. | 03-19-2015 |
20150084001 | GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION - A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench. | 03-26-2015 |
20150084002 | METHODS FOR INTEGRATING AND FORMING OPTICALLY TRANSPARENT DEVICES ON SURFACES - An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches. | 03-26-2015 |
20150090959 | RECONFIGURABLE TUNNEL FIELD-EFFECT TRANSISTORS - A tunnel field-effect transistor (TFET) device includes first and second semiconductor contact regions separated by a semiconductor channel region; a channel gate overlying the channel region; and first and second doping gates overlying the first and second contact regions respectively; wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region. | 04-02-2015 |
20150102288 | ULTRALOW POWER CARBON NANOTUBE LOGIC CIRCUITS AND METHOD OF MAKING SAME - In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage V | 04-16-2015 |
20150108432 | HIGH ION AND LOW SUB-THRESHOLD SWING TUNNELING TRANSISTOR - Devices and manufacturing methods thereof are presented. The device includes a substrate and a fin-type transistor disposed on the substrate. The transistor includes a fin structure that protrudes from the substrate to serve as a source of the transistor. The fin structure is doped with dopants of a first polarity. The transistor also includes a gate layer formed over and around a first end of the fin structure to serve as a gate of the transistor. A drain layer is disposed over the fin structure and adjacent to the gate layer to serve as a drain of the transistor. The drain layer is doped with dopants of a second polarity opposite the first polarity. | 04-23-2015 |
20150123078 | GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer. | 05-07-2015 |
20150123079 | NANOSTRUCTURE AND OPTICAL DEVICE HAVING NANOSTRUCTURE - Provided are nanostructures and optical devices having the nanostructures. The nanostructure may include a carbon nanomaterial layer, a nanopattern formed on the carbon nanomaterial layer, and a metal layer formed on a surface of the nanopattern. The nanostructure may be formed in a ring shape, and the metal layer may include a plurality of metal layers formed of different metals. | 05-07-2015 |
20150123080 | ELECTRONIC DEVICE, STACKED STRUCTURE, AND MANUFACTURING METHOD OF THE SAME - A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr | 05-07-2015 |
20150129839 | FLEXIBLE GRAPHENE SWITCHING DEVICE - Provided is a graphene switching device including: a graphene layer formed on a substrate; a plurality of semiconductor nanowires on the substrate; a first electrode connected to a second end of the graphene layer; a second electrode on the substrate to face the first electrode so as to be connected to the plurality of semiconductor nanowires; a gate insulating layer on the substrate to cover the graphene layer; and a gate electrode on the gate insulating layer. The gate electrode and the plurality of semiconductor nanowires face each other with the graphene layer therebetween. At least one of the plurality of semiconductor nanowires is connected to at least one of the second electrode, the graphene layer, and the other of the plurality of semiconductor nanowires. | 05-14-2015 |
20150137075 | INVERTER INCLUDING TWO-DIMENSIONAL MATERIAL, METHOD OF MANUFACTURING THE SAME AND LOGIC DEVICE INCLUDING INVERTER - Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first transistor and a second transistor that are connected to each other, and the first and second transistor layers may include 2D materials. The first transistor may include a first graphene layer and a first 2D semiconductor layer contacting the first graphene layer, and the second transistor may include a second graphene layer and a second 2D semiconductor layer contacting the second graphene layer. The first 2D semiconductor layer may be a p-type semiconductor, and the second 2D semiconductor layer may be an n-type semiconductor. The first 2D semiconductor layer may be arranged at a lateral side of the second 2D semiconductor layer. | 05-21-2015 |
20150137076 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film ( | 05-21-2015 |
20150137077 | GRAPHENE ELECTRONIC DEVICE - A graphene electronic device includes a substrate, a first electrode and a second electrode provided on the substrate and spaced apart from each other, and graphene channels connecting the first electrode with the second electrode. Each of the graphene channels is separated from the substrate to have a cylindrical structure. | 05-21-2015 |
20150137078 | GRAPHENE SENSOR - A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel. | 05-21-2015 |
20150144883 | FORMING RECESSED STRUCTURE WITH LIQUID-DEPOSITED SOLUTION - A damascene approach is used to form a recessed structure in a substrate for receiving liquid-deposited solution, such as a carbon nanotube (CNT) solution. The liquid-deposited solution is built-up in the recessed structure, simplifying the coating process and providing a more uniform thickness of the liquid-deposited layer. | 05-28-2015 |
20150144884 | GRAPHENE FILM, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A reliable graphene film that provides complete semiconductive properties without mixing of metallic properties, redacts an off current, achieves a high current on/off ratio of 10 | 05-28-2015 |
20150144885 | GRAPHENE STRUCTURE AND METHOD OF MANUFACTURING THE GRAPHENE STRUCTURE, AND GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE GRAPHENE DEVICE - A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer. | 05-28-2015 |
20150144886 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 05-28-2015 |
20150295072 | Methods to Improve the Performance of Compound Semiconductor Devices and Field Effect Transistors - Three methods will be described which may be used to improve the performance of compound semiconductor devices and Field Effect Transistors. In the first method, implementation of more than one sheet of 2DEG or high-density electrons in compound semiconductor devices will be described which may be used to improve the performance of compound semiconductor diodes, resistors and transistors. In the second method, implementation of at least one discontinuity in sheet or sheets of 2DEG or high-density electrons will be discussed which can be used to improve the performance of compound semiconductor diodes, resistors and transistors. In the third method, a way to form an electrical connection between an electrode and a sheet of 2DEG or high density electrons will be presented which may be implemented in compound semiconductor devices to reduce the contact resistance between an electrode and a sheet of 2DEG or high-density electrons. | 10-15-2015 |
20150303059 | Homoepitaxial Tunnel Barriers with Functionalized Graphene-on-Graphene and Methods of Making - This disclosure describes a method of making a tunnel barrier-based electronic device, in which the tunnel barrier and transport channel are made of the same material—graphene. A homoepitaxial tunnel barrier/transport device is created using a monolayer chemically modified graphene sheet as a tunnel barrier on another monolayer graphene sheet. This device displays enhanced spintronic properties over heteroepitaxial devices and is the first to use graphene as both the tunnel barrier and channel. | 10-22-2015 |
20150303264 | METHOD FOR COUPLING A GRAPHENE LAYER AND A SUBSTRATE AND DEVICE COMPRISING THE GRAPHENE/SUBSTRATE STRUCTURE OBTAINED - The present disclosure regards a method for coupling a graphene layer to a substrate having at least one hydrophilic surface, the method comprising the steps of providing the substrate having at least one hydrophilic surface, depositing on the hydrophilic surface a layer of a solvent selected in the group constituted by acetone, ethyl lactate, isopropyl alcohol, methylethyl ketone and mixtures thereof and depositing on the solvent layer a graphene layer. It moreover regards an electronic device comprising the graphene/substrate structure obtained. | 10-22-2015 |
20150303299 | 3D UTB TRANSISTOR USING 2D MATERIAL CHANNELS - A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode. | 10-22-2015 |
20150318356 | METHOD AND ARRANGEMENT FOR REDUCING CONTACT RESISTANCE OF TWO-DIMENSIONAL CRYSTAL MATERIAL - A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing. | 11-05-2015 |
20150333196 | OPTOELECTRONIC DEVICE INCLUDING FERROELECTRIC MATERIAL - Example embodiments relate to optoelectronic devices. An optoelectronic device may include a photoactive layer between first and second electrodes, and a ferroelectric layer corresponding to at least one of the first and second electrodes. At least one of the first and second electrodes may include graphene. The photoactive layer may include a two-dimensional (2D) semiconductor. The optoelectronic device may further include a third electrode, and in this case, the ferroelectric layer may be between the second electrode and the third electrode. The second electrode, the ferroelectric layer, and the third electrode may constitute a nanogenerator. | 11-19-2015 |
20150340436 | THREE-DIMENSIONAL TEXTURING OF TWO-DIMENSIONAL MATERIALS - A method of creating crumples in a monolayer entails contacting a monolayer comprising a two-dimensional material with a thermally contractible polymer, and heating the thermally contractible polymer to contract the polymer and induce buckling of the monolayer, where a plurality of crumples are formed in the monolayer due to the buckling. A device having a crumpled microstructure includes a monolayer comprising a two-dimensional material and including a plurality of crumples. | 11-26-2015 |
20150357189 | METHODS FOR INTEGRATING LEAD AND GRAPHENE GROWTH AND DEVICES FORMED THEREFROM - Methods for forming integrated graphite-based structures with interconnections between leads and graphene layers are provided. A substrate is patterned to form a plurality of elements on the substrate. A trench separates a first element from an adjacent element in the plurality of elements. A lead is deposited on a side wall of the first element, and a layer from the top of the first element is removed to expose a portion of the lead. Both the deposition of the lead and removal of a layer from the top of the first element are conducted before generation of graphene layers on the top of the first element and the bottom of the trench. Thus, an integrated graphite-based structure having spatially isolated but electrically connected graphene layers is formed. | 12-10-2015 |
20150357485 | PHOTODETECTOR - Provided is a photodetector including a graphene p-n homogeneous vertical-junction diode by evaluating photodetection characteristics of the manufactured graphene p-n vertical junction according to the amount of doping. The photodetector comprises a substrate and graphene having a p-n homogeneous vertical junction as a photodetection layer formed on the substrate, wherein the photodetection layer has a detectability of 10E11 (Jones) or higher within the range of 350 nm to 1100 nm, and first and second electrodes are formed on the photodetection layer. | 12-10-2015 |
20150364472 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device, a method for manufacturing the same, and an electronic device including the same are provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel layer and a first ion gel. The second transistor includes a second channel layer and a second ion gel. The first channel layer and the second channel layer may include, for example, graphene. The first ion gel and the second ion gel include different ionic liquids. The first ion gel and the second ion gel include different cations and/or different anions. One of the first transistor and the second transistor is a p-type transistor, and the other one is an n-type transistor. The combination of the first transistor and the second transistor constitutes an inverter. | 12-17-2015 |
20150364542 | Integrated Circuits with Si and Non-Si Nanosheet FET Co-Integration with Low Band-to-Band Tunneling and Methods of Fabricating the Same - An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs. | 12-17-2015 |
20150364589 | GRAPHENE-METAL BONDING STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE GRAPHENE-METAL BONDING STRUCTURE - Provided are a graphene-metal bonding structure, a method of manufacturing the graphene-metal bonding structure, and a semiconductor device including the graphene-metal bonding structure. According to example embodiments, a graphene-metal bonding structure includes: a graphene layer; a metal layer on the graphene layer; and an intermediate material layer between the graphene layer and the metal layer. The intermediate material layer forms an edge-contact with the metal layer from boundary portions of a material contained in the intermediate material layer that contact the metal layer. | 12-17-2015 |
20150364592 | Thin-Sheet FinFET Device - A thin-sheet non-planar circuit device such as a FinFET and a method for forming the device is disclosed. In some exemplary embodiments, the device includes a substrate having a top surface and a feature disposed on the substrate that extends above the top surface. A material layer disposed on the feature. The material layer includes a plurality of source/drain regions and a channel region disposed between the source/drain regions. A gate stack is disposed on the channel region of the material layer. In some such embodiments, the feature includes a plurality of side surfaces, and the material layer is disposed on each of the side surface surfaces. In some such embodiments, the feature also includes a top surface and the material layer is further disposed on the top surface. In some embodiments, the top surface of the feature is free of the material layer. | 12-17-2015 |
20150364691 | INFRARED DETECTOR WITH SWNT-BASED DOUBLE-CANTILEVER AND MANUFACTURE THEREOF - A double-cantilever infrared detector based on single walled carbon nanotube and the manufacture method thereof are provided. The detector comprises: a substrate having a detection window extending through the substrate from the top surface to the bottom surface; two heterogeneous cantilevers, wherein each cantilever is located on the substrate and has a fixed end connected to the substrate and a free end suspended above the detection window; a single walled carbon nanotube film bridged between the two free ends of the two heterogeneous composite cantilevers, wherein the heterogeneous cantilevers include a first material layer and a second material layer located thereon, and the first material layer and the second material layer have different thermal expansion coefficients. | 12-17-2015 |
20150372111 | METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES - A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers. | 12-24-2015 |
20150372163 | NANOSTRUCTURE AND OPTICAL DEVICE INCLUDING THE NANOSTRUCTURE - Provided are a nanostructure and an optical device including the nanostructure. The nanostructure is formed on a two-dimensional material layer such as graphene and includes nanopatterns having different shapes. The nanopattern may include a first nanopattern and a second nanopattern and may be spherical; cube-shaped; or poly-pyramid-shaped, including a triangular pyramid shape; or polygonal pillar-shaped. | 12-24-2015 |
20160005894 | METHOD OF MANUFACTURING A MONOLAYER GRAPHENE PHOTODETECTOR AND MONOLAYER GRAPHENE PHOTODETECTOR - In various embodiments of the present disclosure, there is provided a method of manufacturing a monolayer graphene photodetector, the method including forming a graphene quantum dot array in a graphene monolayer, and forming an electron trapping center in the graphene quantum dot array. Accordingly, a monolayer graphene photodetector is also provided. | 01-07-2016 |
20160005974 | ELECTRONIC DEVICE USING ORGANIC THIN FILM, AND ELECTRONIC APPARATUS CONTAINING THE SAME - The present invention provides a high-performance, highly homogeneous, highly stable electronic device by forming an extremely uniform interface between an insulator and an organic semiconductor, as well as an electronic apparatus using the same. The present invention relates to an electronic device which contains, as a component, an organic thin film in which a geometric two-dimensional arrangement is formed regularly by interdigitating skeletal structures of a positive three-pronged shape of triptycene and by adding a first molecule extending out of one plane of a two-dimensional molecular structure of the triptycene skeletal structure. The invention also relates to an electronic apparatus and the like which contains the electronic device in the interior of the electronic apparatus. | 01-07-2016 |
20160013277 | SEMICONDUCTOR STRUCTURE WITH TEMPLATE FOR TRANSITION METAL DICHALCOGENIDES CHANNEL MATERIAL GROWTH | 01-14-2016 |
20160027928 | CONNECTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A connecting structure includes: a Si substrate; a nanocarbon material formed above the Si substrate; and an electrode electrically connected to the nanocarbon material, wherein a molecular material having a doping function is inserted between the Si substrate and the nanocarbon material. With this configuration, a highly-reliable connecting structure and a method for manufacturing the same are obtained which realize, even though using the nanocarbon material, a sufficiently low contact resistance between the nanocarbon material and the electrode. | 01-28-2016 |
20160033800 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present invention provides a thin film transistor, an array substrate and a display device, relating to the field of display technology, for solving the problem that a source/drain electrode metals and a gate metal may be short-circuited in the manufacturing process of an existing bottom-gate thin film transistor. The thin film transistor of the present invention comprises: a gate formed on a substrate, the gate being connected with a gate line; and a semiconductor layer formed on the gate and the gate line, at least a part of the semiconductor layer extends in the direction parallel to the substrate to exceed the edge of the gate. The array substrate of the present invention comprises the thin film transistor, and the display device comprises the array substrate. The present invention may improve the yield of the bottom-gate thin film transistor. | 02-04-2016 |
20160043235 | SEMICONDUCTOR DEVICE AND METHOD OF FORMATION - A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided. | 02-11-2016 |
20160049475 | GRAPHENE LAYER TRANSFER - A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene. | 02-18-2016 |
20160056236 | SILICON AND SILICON GERMANIUM NANOWIRE FORMATION - Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. | 02-25-2016 |
20160056240 | GRAPHENE FILM, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A GNR is a ribbon-shaped graphene film which includes: five or more (for example, five, seven, or nine) six-membered rings of carbon atoms which are bonded and arranged in line in a short side direction; and a complete armchair type edge structure along a long side direction. By such a constitution, without using a transfer method, there are materialized a highly reliable graphene film which has an armchair type edge structure with a uniform width at a desired value and which enables an electric current on-off ratio of 10 | 02-25-2016 |
20160056384 | HYBRID CARBON-METAL INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed. | 02-25-2016 |
20160071982 | SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL - A field effect transistor (FET) with a graphene layer as a channel layer is disclosed. The FET provides two gate electrodes, one of which receives the gate bias, while, the other receives a reference bias. An intermediate electrode made of ohmic metal to the graphene layer is provided between the two gate electrodes. The second gate electrode receiving the reference bias suppresses the hole injection into the channel beneath the first gate electrode. | 03-10-2016 |
20160079357 | ORIENTED BOTTOM-UP GROWTH OF ARMCHAIR GRAPHENE NANORIBBONS ON GERMANIUM - Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are formed using a scalable, bottom-up, chemical vapor deposition (CVD) technique in which the (001) facet of the germanium is used to orient the graphene nanoribbon crystals along the [110] directions of the germanium. | 03-17-2016 |
20160079422 | NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF - A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire. | 03-17-2016 |
20160087042 | FIN-TYPE GRAPHENE DEVICE - Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to the substrate, a gate insulating layer that covers one side surface of the graphene channel layer, a gate electrode on the gate insulating layer, and a source electrode and a drain electrode that are formed separately from each other on other side surface of the graphene channel layer. | 03-24-2016 |
20160087212 | GRAPHENE NANORIBBONS AS SEMICONDUCTORS FOR ORGANIC THIN FILM TRANSISTORS - Disclosed herein are graphene nanoribbons, controllable and reproducible methods of synthesizing graphene nanoribbons, and uses thereof. Transistors containing graphene nanoribbons are also disclosed. | 03-24-2016 |
20160093551 | INTEGRATION OF HEAT SPREADER FOR BEOL THERMAL MANAGEMENT - A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters. | 03-31-2016 |
20160093552 | INTEGRATION OF BACKSIDE HEAT SPREADER FOR THERMAL MANAGEMENT - A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters. | 03-31-2016 |
20160093745 | SEMICONDUCTOR DEVICE AND CHANNEL STRUCTURE THEREOF - A semiconductor device having a composite structure is disclosed, which includes a channel structure having an inner core strut that extends substantially along a channel direction of the semiconductor device and an outer sleeve layer disposed on the inner core strut. The inner core strut mechanically supports the sleeve member across a channel length of the semiconductor device. | 03-31-2016 |
20160093746 | COHERENT SPIN FIELD EFFECT TRANSISTOR - A voltage switchable coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A chrome oxide layer is formed on the cobalt by MBE at room at UHV at room temperature. There was thin cobalt oxide interface between the chrome oxide and the cobalt. Other magnetic materials may be employed. A few ML field of graphene is deposited on the chrome oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology. | 03-31-2016 |
20160093819 | FRINGING FIELD ASSISTED DIELECTROPHORESIS ASSEMBLY OF CARBON NANOTUBES - A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device. | 03-31-2016 |
20160104765 | SEMICONDUCTOR DEVICES WITH HORIZONTAL GATE ALL AROUND STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm | 04-14-2016 |
20160104778 | GRAPHENE BASE TRANSISTOR AND METHOD FOR MAKING THE SAME - A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other. | 04-14-2016 |
20160104790 | SILICENE MATERIAL LAYER AND ELECTRONIC DEVICE HAVING THE SAME - Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a 2-dimensional honeycomb structure formed as one of a monolayer and a double layer. The silicene material layer includes a doping region doped with at least one material from the group of Group 1, Group 2, Group 16 and Group 17 and at least one of a p-type dopant or an n-type dopant. | 04-14-2016 |
20160104799 | DUAL-STRAINED NANOWIRE AND FINFET DEVICES WITH DIELECTRIC ISOLATION - A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions. | 04-14-2016 |
20160111633 | Method and Device for Huge Magnetoresistance in Graphene-Based Magnetic Tunnel Junctions with Segmented Potentials - A graphene-based magnetic tunnel junction is disclosed. The magnetic tunnel junction can enhance the tunnel magnetoresistance ratio and a device including the magnetic tunnel junction. The magnetic tunnel junction includes: a pinned layer; a free layer; and a graphene with segmented potentials configured between the pinned layer and the free layer. The magnetic tunnel junction may be a series or parallel connection of the above-mentioned basic form. The device including a magnetic tunnel junction may be a magnetic random access memory bit cell, a magnetic tunnel junction transistor device, a magnetic field sensor, etc. | 04-21-2016 |
20160111643 | TOPOLOGICAL INSULATOR FORMED NEW SURFACE ELECTRONIC STATE AND THE PREPARATION METHOD THEREOF - The disclosure describes a topological insulator having a new surface electronic state and a preparation method thereof, and more particularly, to a topological insulator having a new surface electronic state, the topological insulator including a unimolecular metal layer formed on a 3D topological insulator, and a method of preparing a topological insulator having a new surface electronic state, the method including: heating and cooling at least one selected from the group consisting of tellurium (Te) and selenium (Se), and bismuth (Bi) to prepare an alloy; and forming a unimolecular metal layer on the alloy. | 04-21-2016 |
20160116431 | MANUFACTURING METHOD OF A GRAPHENE-BASED ELECTROCHEMICAL SENSOR, AND ELECTROCHEMICAL SENSOR - A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure. | 04-28-2016 |
20160126293 | ACTIVE MATRIX LIGHT EMITTING DIODES DISPLAY MODULE WITH CARBON NANOTUBES CONTROL CIRCUITS AND METHODS OF FABRICATION - An active matrix light emitting diodes display module integrated with single-walled carbon nanotubes control circuits includes a light emitting diode pixel having a crystalline semiconductor light emitting diode, single-walled carbon nanotubes switching transistors and a charge storage capacitor | 05-05-2016 |
20160126317 | GRAPHENE LAYER, METHOD OF FORMING THE SAME, DEVICE INCLUDING GRAPHENE LAYER AND METHOD OF MANUFACTURING THE DEVICE - A graphene layer, a method of forming the graphene layer, a device including the graphene layer, and a method of manufacturing the device are provided. The method of forming the graphene layer may include forming a first graphene at a first temperature using a first source gas and forming a second graphene at a second temperature using a second source gas. One of the first and second graphenes may be a P-type graphene, and the other one of the first and second graphenes may be an N-type graphene. The first graphene and the second graphene together form a P—N junction. | 05-05-2016 |
20160126482 | Assembly of Vertically Aligned Nanotube Arrays Containing Particles and Application Thereof - A nanotube assembly including a nanotube layer, a first layer and a second layer. The nanotube layer comprises a vertically aligned nanotube array. The nanotube array includes a plurality of nanotubes. The first layer of a first conductive material is disposed on one surface of the nanotube layer. The second layer of a second conductive material is disposed on an opposite surface of the nanotube layer. The nanotube of the nanotube layer includes a first end against the first layer and a second end against the second layer. The resistance from the first end to the first layer is lower than a resistance from the second end to the second layer. One or more nano-particles are placed within the nanotube. At least one of the nano-particles is electrically charged, and can move along the nanotube under influence of an electric field. | 05-05-2016 |
20160133700 | NANOWIRE AND PLANAR TRANSISTORS CO-INTEGRATED ON UTBOX SOI SUBSTRATE - Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor. | 05-12-2016 |
20160141174 | MOLYBDENUM DISULFIDE FILM FORMATION AND TRANSFER TO A SUBSTRATE - A method is provided for forming an unsupported MoS | 05-19-2016 |
20160141336 | Field Effect Transistor Constructions And Memory Arrays - In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers. | 05-19-2016 |
20160141501 | SELECTIVE PLACEMENT OF CARBON NANOTUBES VIA COULOMBIC ATTRACTION OF OPPOSITELY CHARGED CARBON NANOTUBES AND SELF-ASSEMBLED MONOLAYERS - A method of forming a structure having selectively placed carbon nanotubes, a method of making charged carbon nanotubes, a bi-functional precursor, and a structure having a high density carbon nanotube layer with minimal bundling. Carbon nanotubes are selectively placed on a substrate having two regions. The first region has an isoelectric point exceeding the second region's isoelectric point. The substrate is immersed in a solution of a bi-functional precursor having anchoring and charged ends. The anchoring end bonds to the first region to form a self-assembled monolayer having a charged end. The substrate with charged monolayer is immersed in a solution of carbon nanotubes having an opposite charge to form a carbon nanotube layer on the self-assembled monolayer. The charged carbon nanotubes are made by functionalization or coating with an ionic surfactant. | 05-19-2016 |
20160155839 | NANOGAPS ON ATOMICALLY THIN MATERIALS AS NON-VOLATILE READ/WRITABLE MEMORY DEVICES | 06-02-2016 |
20160155971 | INTEGRATED MULTI-TERMINAL DEVICES CONSISTING OF CARBON NANOTUBE, FEW-LAYER GRAPHENE NANOGAPS AND FEW-LAYER GRAPHENE NANORIBBONS HAVING CRYSTALLOGRAPHICALLY CONTROLLED INTERFACES | 06-02-2016 |
20160163753 | NANOWIRE PHOTO-DETECTOR GROWN ON A BACK-SIDE ILLUMINATED IMAGE SENSOR - An embodiment relates to a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. | 06-09-2016 |
20160178569 | Chemically-Sensitive Field Effect Transistor | 06-23-2016 |
20160181539 | Systems and Process For Forming Carbon Nanotube Sensors | 06-23-2016 |
20160190210 | COMPLEMENTARY CARBON NANOTUBE NEURON DEVICE - A method for forming a semiconductor device includes providing a substrate structure, which includes a carbon nanotube supported by two support structures on a substrate. The carbon nanotube includes a first portion and a second portion having different conductivity types. A multi-layer film structure is formed surrounding the carbon nanotube, the multi-layer film structure including a conductive material layer sandwiched between two dielectric layers. A plurality of first electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the first portion, and a plurality of second electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the second portion. A third electrode is formed to contact one end of the carbon nanotube, and a fourth electrode is formed to contact the other end of the carbon nanotube. A fifth electrode is formed and coupled to a center portion of the carbon nanotube. | 06-30-2016 |
20160190244 | ELECTRONICS DEVICE HAVING TWO-DIMENSIONAL (2D) MATERIAL LAYER AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE BY INKJET PRINTING - An electronic device includes first and second electrodes that are spaced apart from each other and a 2D material layer. The 2D material layer connects the first and second electrodes. The 2D material layer includes a plurality of 2D nanomaterials. At least some of the 2D nanomaterials overlap one another. | 06-30-2016 |
20160190336 | COMPLEMENTARY HIGH MOBILITY NANOWIRE NEURON DEVICE - A method for forming a semiconductor device includes providing a substrate structure, which includes a nanowire structure supported by two isolation regions on a substrate. The nanowire structure includes a first nanowire and a second nanowire having different high mobility semiconductor materials and conductivity types. A multi-layer film structure is formed surrounding the nanowire structure and includes a conductive material layer sandwiched between two dielectric layers. A plurality of first electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the first nanowire, and a plurality of second electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the second nanowire. A third electrode is formed to contact one end of the nanowire structure, and a fourth electrode is formed to contact the other end of the nanowire structure. A fifth electrode is formed and coupled to a center portion of the nanowire structure. | 06-30-2016 |
20160190343 | A FET DEVICE HAVING A VERTICAL CHANNEL IN A 2D MATERIAL LAYER - Semiconductor devices and methods of forming the same are provided. A source/drain electrode stack is formed over a substrate, wherein the source/drain electrode stack comprises a first source/drain electrode and a second source/drain electrode. A source/channel/drain layer is formed on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material. A gate stack is formed on the source/channel/drain layer. | 06-30-2016 |
20160190490 | N-TYPE THIN FILM TRANSISTOR - An thin film transistor includes an insulating substrate, an MgO layer, a semiconductor carbon nanotube layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is sandwiched between the MgO layer and the functional dielectric layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer. The gate electrode is sandwiched between the insulating substrate and the MgO layer. | 06-30-2016 |
20160190492 | N-TYPE THIN FILM TRANSISTOR - An N-type semiconductor layer includes an insulating substrate, an MgO layer, a semiconductor carbon nanotube layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is sandwiched between the MgO layer and the functional dielectric layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer. The gate electrode is on the functional dielectric layer and insulated from the semiconductor carbon nanotube layer. | 06-30-2016 |
20160190493 | N-TYPE THIN FILM TRANSISTOR - An N-type thin film transistor includes an insulating substrate, a semiconductor carbon nanotube layer, an MgO layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is located on the insulating substrate. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode. The MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covers the MgO layer. The gate electrode is located on the functional dielectric layer. | 06-30-2016 |
20160190494 | CARBON NANOTUBE NEURON DEVICE AND METHOD FOR MAKING THE SAME - A carbon nanotube neuron device and a method of making the same are provided. The carbon nanotube neuron device includes a substrate, an insulating layer formed on the substrate, and a carbon nanotube formed above the insulating layer. The carbon nanotube includes a source region, a drain region, and a channel region between the source region and the drain region. The carbon nanotube neuron device further includes a laminate structure surrounding the channel region. The laminate structure includes a first dielectric layer, a conductive layer, and a second dielectric layer. The carbon nanotube neuron device further includes a source electrode and a drain electrode disposed above the insulating layer and surrounding the source region and the drain region, respectively, and a plurality of gate electrodes spaced apart from each other and disposed above the insulating layer. Each gate electrode surrounds the laminate structure that surrounds the channel region. | 06-30-2016 |
20160190495 | N-TYPE THIN FILM TRANSISTOR - An N-type thin film transistor includes an insulating substrate, a gate electrode, an insulating layer, a semiconductor carbon nanotube layer, an MgO layer, a functional dielectric layer, a source electrode, and a drain electrode. The gate electrode is located on a surface of the insulating substrate. The insulating layer is located on the gate electrode. The semiconductor carbon nanotube layer is located on the insulating layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode. The MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covers the MgO layer. | 06-30-2016 |
20160197148 | ELECTRICAL DEVICES WITH GRAPHENE ON BORON NITRIDE | 07-07-2016 |
20160197274 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY DEVICE | 07-07-2016 |
20160204204 | STACKED GRAPHENE FIELD-EFFECT TRANSISTOR | 07-14-2016 |
20160204351 | LIGHT EMITTING DIODE | 07-14-2016 |
20160254355 | ELECTRONIC DEVICE | 09-01-2016 |
20160254468 | ALIGNED CARBON NANOTUBES FOR USE IN HIGH PERFORMANCE FIELD EFFECT TRANSISTORS | 09-01-2016 |
20160379901 | Semiconductor Devices Comprising 2D-Materials and Methods of Manufacture Thereof - A method for manufacturing a semiconductor device comprising two-dimensional (2D) materials may include: epitaxially forming a first two-dimensional (2D) material layer over a substrate; calculating a mean thickness of the first 2D material layer; comparing the mean thickness of the first 2D material layer with a reference parameter; determining that the mean thickness of the first 2D material layer is not substantially equal to the reference parameter; and after the determining, epitaxially forming a second 2D material layer over the first 2D material layer. | 12-29-2016 |
20160380054 | NANOWIRE SEMICONDUCTOR DEVICE INCLUDING LATERAL-ETCH BARRIER REGION - A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material. | 12-29-2016 |
20170237008 | RF-TRANSISTORS WITH SELF-ALIGNED POINT CONTACTS | 08-17-2017 |
20180026214 | CARBON NANOTUBE THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF | 01-25-2018 |
20190148534 | TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING TUNNELING FIELD-EFFECT TRANSISTOR | 05-16-2019 |