VIA Technologies, Inc. Patent applications |
Patent application number | Title | Published |
20150339232 | APPARATUS AND METHOD FOR REPAIRING CACHE ARRAYS IN A MULTI-CORE MICROPROCESSOR - An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configuration data sets. One of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store the decompressed configuration data sets for one or more cache memories in the stores. Each of the plurality of cores includes reset logic and sleep logic. The reset logic is configured to employ the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic is configured to determine that power is restored following a power gating event, and is configured to subsequently access the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event. | 11-26-2015 |
20150339231 | MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL MECHANISM - An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches. | 11-26-2015 |
20150338905 | MULTI-CORE DATA ARRAY POWER GATING RESTORAL MECHANISM - An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event. | 11-26-2015 |
20150338904 | MULTI-CORE APPARATUS AND METHOD FOR RESTORING DATA ARRAYS FOLLOWING A POWER GATING EVENT - An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event. | 11-26-2015 |
20150254093 | SYSTEM AND METHOD FOR ASSIGNING VIRTUAL FUNCTIONS AND MANAGEMENT HOST THEREOF - A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function. | 09-10-2015 |
20150227424 | DATA STORAGE DEVICE AND DATA CHECKING AND CORRECTION FOR VOLATILE MEMORY - Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction. | 08-13-2015 |
20150212947 | DYNAMIC CACHE ENLARGING BY COUNTING EVICTIONS - A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions. | 07-30-2015 |
20150207497 | LOW-OFFSET BANDGAP CIRCUIT AND OFFSET-CANCELLING CIRCUIT THEREIN - A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current. | 07-23-2015 |
20150200791 | DIFFERENTIAL SIGNAL TRANSMITTERS - A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state. | 07-16-2015 |
20150160705 | INTERMEDIATE ELECTRONIC DEVICE, METHOD FOR OPERATING THE INTERMEDIATE ELECTRONIC DEVICE AND ELECTRONIC SYSTEM - An intermediate electronic device, arranged to be coupled to a host system and an electronic device. The intermediate electronic device includes: a controller, enabled by an enable signal to process the data transmission between the host system and the electronic device; and a power transmission unit disposed between the host system and the electronic device. The power transmission units detect whether the power transmission unit is coupled to the host system or an external power source. When the power transmission unit detects that the power transmission unit is coupled to the host system, but not coupled to the external power source, the power transmission unit informs the host system to raise the voltage output to the intermediate electronic device to supply power to the electronic device, and outputs the enable signal. | 06-11-2015 |
20150134978 | SECURE BIOS TAMPER PROTECTION MECHANISM - An apparatus including a ROM, a selector, and a detector. The ROM has a partitions, each stored as plaintext, and a encrypted digests, each comprising an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more partitions responsive to an interrupt. The detector generates the interrupt at a combination of intervals and event occurrences, and accesses the one or more partitions and corresponding one or more encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate corresponding one or more second digests corresponding to the one or more partitions and corresponding one or more decrypted digests corresponding to the one or more encrypted digests using the same algorithms and key that were employed to generate the first message digest and encrypted digests, and compares the one or more second digests with the one or more decrypted digests, and precludes the operation if the one or more second digests and the one or more decrypted digests are not pair wise equal. | 05-14-2015 |
20150134977 | PARTITION-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION - An apparatus including a ROM, a selector, and a detector. The ROM has partitions and encrypted digests. Each of the partitions is stored as plaintext, and each of the encrypted digests includes an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more of the partitions responsive to an interrupt. The detector accesses the one or more of the partitions and corresponding one or more of the encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate one or more of second digests corresponding to the one or more of the partitions and one or more of decrypted digests corresponding to the one or more of encrypted digests using the same algorithms and key that were employed to generate the first digest and the encrypted digests, and compares the one or more of the second digests with the one or more of the decrypted digests, and precludes operation of the microprocessor if the one or more of the second digests and the one or more of the decrypted digests are not pair wise equal. | 05-14-2015 |
20150134976 | EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION - An apparatus including a ROM, an event detector, and a tamper detector. The ROM has BIOS contents stored as plaintext, and an encrypted digest. The encrypted digest is an encrypted version of a first digest corresponding to the BIOS contents. The event detector generates an interrupt that interrupts operation of the system upon occurrence of an event. The tamper detector is operatively coupled to the ROM and accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs a microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second digest and the decrypted digest are not equal. | 05-14-2015 |
20150134974 | APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM - An apparatus including a BIOS read only memory (ROM) and a tamper detector. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest comprising an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is coupled to the BIOS ROM, and accesses the BIOS contents and the encrypted message digest upon reset of a microprocessor, and directs the microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the same algorithms and key that were employed to generate the first message digest and the encrypted message digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. | 05-14-2015 |
20150123690 | PROBE CARD - A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board. | 05-07-2015 |
20150113253 | SELECTIVELY COMPRESSED MICROCODE - A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word. | 04-23-2015 |
20150113250 | MICROPROCESSOR WITH COMPRESSED AND UNCOMPRESSED MICROCODE MEMORIES - A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed. | 04-23-2015 |
20150089204 | DYNAMICALLY RECONFIGURABLE MICROPROCESSOR - A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint. | 03-26-2015 |
20150089142 | MICROPROCESSOR WITH INTEGRATED NOP SLIDE DETECTOR - A microprocessor includes an instruction cache and a hardware state machine configured to detect a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero. The microprocessor is configured to suspend fetching and executing instructions from the instruction cache in response to detecting the continuous sequence of N NOP instructions. | 03-26-2015 |
20150067666 | PROPAGATION OF MICROCODE PATCHES TO MULTIPLE CORES IN MULTICORE MICROPROCESSOR - A microprocessor includes a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and comprises hardware to patch the microcode. A first core of the plurality of processing cores is configured to encounter an instruction that instructs the first core to apply a microcode patch. The first core of the plurality of processing cores is further configured to, in response to encountering the instruction, inform each core of the other of the plurality of processing cores of the microcode patch and apply the microcode patch to the hardware of the first core. Each core of the plurality of processing cores other than the first core is configured to apply the microcode patch to the hardware of the core, in response to being informed by the first core. | 03-05-2015 |
20150067369 | MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred. | 03-05-2015 |
20150067368 | CORE SYNCHRONIZATION MECHANISM IN A MULTI-DIE MULTI-CORE MICROPROCESSOR - A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores. | 03-05-2015 |
20150067367 | METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS - An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency. | 03-05-2015 |
20150067306 | INTER-CORE COMMUNICATION VIA UNCORE RAM - A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores. | 03-05-2015 |
20150067263 | SERVICE PROCESSOR PATCH MECHANISM - A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores. | 03-05-2015 |
20150067250 | MULTI-CORE HARDWARE SEMAPHORE - A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource. | 03-05-2015 |
20150067219 | DYNAMIC DESIGNATION OF THE BOOTSTRAP PROCESSOR IN A MULTI-CORE MICROPROCESSOR - A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor. | 03-05-2015 |
20150067214 | SINGLE-CORE WAKEUP MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep. | 03-05-2015 |
20150061119 | CIRCUIT SUBSTRATE, SEMICONDUTOR PACKAGE STRUCTURE AND PROCESS FOR FABRICATING A CIRCUIT SUBSTRATE - A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided. | 03-05-2015 |
20150058695 | CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements. | 02-26-2015 |
20150058610 | CORE-SPECIFIC FUSE MECHANISM FOR A MULTI-CORE DIE - An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores. | 02-26-2015 |
20150058609 | APPARATUS AND METHOD FOR STORAGE AND DECOMPRESSION OF CONFIGURATION DATA - An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
20150058598 | APPARATUS AND METHOD FOR CONFIGURABLE REDUNDANT FUSE BANKS - An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register. | 02-26-2015 |
20150058564 | APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION - An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
20150055429 | APPARATUS AND METHOD FOR COMPRESSION AND DECOMPRESSION OF MICROPROCESSOR CONFIGURATION DATA - An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core. | 02-26-2015 |
20150055428 | MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA - An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory. | 02-26-2015 |
20150055427 | MULTI-CORE MICROPROCESSOR CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM - An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores. | 02-26-2015 |
20150055395 | EXTENDED FUSE REPROGRAMMABILITY MECHANISM - An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. | 02-26-2015 |
20150054543 | APPARATUS AND METHOD FOR RAPID FUSE BANK ACCESS IN A MULTI-CORE PROCESSOR - An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data. | 02-26-2015 |
20150049839 | Common Mode Modulation with Current Compensation - The present disclosure provides systems and methods for compensating channel modulation effects. Some embodiments comprise a differential switching circuit, a common mode modulation circuit, and a current compensation circuit. The current compensation circuit compensates for channel modulation effects. | 02-19-2015 |
20150042666 | IMAGE TRANSMISSION APPARATUS AND IMAGE PROCESSING METHOD THEREOF - An image transmission apparatus for providing a low voltage differential signaling (LVDS) data stream to a display panel is provided. The image transmission apparatus includes a transmitter and a graphic processing unit (GPU). The transmitter obtains an extended display identification data (EDID) according to an inter integrated circuit signal from the display panel. The GPU provides configuration data according to the EDID, and provides a display port (DP) data stream according to an image data. The transmitter obtains a transfer parameter according to the configuration data, and converts the DP data stream into the LVDS data stream according to the transfer parameter. | 02-12-2015 |
20150019222 | METHOD FOR USING VOICEPRINT IDENTIFICATION TO OPERATE VOICE RECOGNITION AND ELECTRONIC DEVICE THEREOF - A method for using voiceprint identification to operate voice recognition and electronic device thereof are provided. The method includes the following steps: receiving a specific voice fragment; cutting the received specific voice fragment into a plurality of specific sub-voice clips; performing a voiceprint identification flow to the specific sub-voice clips, respectively; determining whether each of the specific sub-voice clips is an appropriate sub-voice clip according to a result of the voiceprint identification flow; and capturing the appropriate sub-voice clips and operating a voice recognition thereto. | 01-15-2015 |
20150012549 | SORTING METHOD OF DATA DOCUMENTS AND DISPLAY METHOD FOR SORTING LANDMARK DATA - A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving corresponding keyword rankings of the plurality of keywords by a search engine; searching corresponding keyword categories of the plurality of keywords; and generating a sort algorithm based on the plurality of keywords, the keyword ranking and the keyword category of each of the plurality of keywords, and a current ranking of each of the plurality of data documents, wherein the sort algorithm is used to calculate a predicting ranking of another data document and to sort the another data document. | 01-08-2015 |
20150012543 | REGION LABELING METHOD AND DEVICE OF DATA DOCUMENTS - A region labeling method of data documents and a device thereof are provided. The region labeling method includes: obtaining a tree structure, which has a plurality of nodes including a plurality of administrative division names and iconic names with a hierarchical relationship therebetween; receiving the data document and retrieving at least one keyword from the data document; comparing the at least one keyword with the nodes to find a first node matching the at least one keyword; and labeling the first node and at least one father node of the first node to the data document. | 01-08-2015 |
20140361828 | DIGITAL POWER GATING WITH PROGRAMMABLE CONTROL PARAMETER - An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter. | 12-11-2014 |
20140361823 | DIGITAL POWER GATING WITH GLOBAL VOLTAGE SHIFT - A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus. | 12-11-2014 |
20140361820 | DIGITAL POWER GATING WITH CONTROLLED RESUME - An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock. | 12-11-2014 |
20140351561 | MICROPROCESSOR THAT FUSES IF-THEN INSTRUCTIONS - A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block. | 11-27-2014 |
20140320188 | SCANNABLE FAST DYNAMIC REGISTER - A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration. | 10-30-2014 |
20140320164 | FAST DYNAMIC REGISTER WITH TRANSPARENT LATCH - A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency. | 10-30-2014 |
20140317331 | EXTERNAL ELECTRONIC DEVICE AND INTERFACE CONTROLLER AND EXTERNAL ELECTRONIC DEVICE CONTROL METHOD - An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host. | 10-23-2014 |
20140310004 | VOICE CONTROL METHOD, MOBILE TERMINAL DEVICE, AND VOICE CONTROL SYSTEM - A voice control method, a mobile terminal device, and a voice control system are provided. The voice control method includes the following steps. An application provides at least one operating parameter for a speech software development module. The speech software development module receives a voice signal and parses the voice signal, and thus a voice recognition result is obtained. The speech software development module determines whether the voice recognition result matches the operating parameters. When the voice recognition result matches the operating parameters, the speech software development module provides an operating signal for the application. | 10-16-2014 |
20140309996 | VOICE CONTROL METHOD AND MOBILE TERMINAL APPARATUS - A voice control method and a mobile terminal apparatus are provided. The mobile terminal apparatus includes a voice receiving module, a voice outputting module, a voice wake-up module and a language recognition module. When the voice wake-up module determined that a first voice signal matches to identification information, the voice receiving module is turned on. When the voice receiving module receives a second voice signal after the first voice signal, the language recognition module parses the second voice signal and obtains a voice recognition result. When the voice recognition result includes an executing request, the language recognition module executes a responding operation, and the voice receiving module is turned off from receiving a third voice signal. When the voice recognition result does not include the executing request, the language recognition module executes a speech conversation mode. | 10-16-2014 |
20140307376 | TRANSMITTAL SYSTEM AND CONNECTION DEVICE - A transmittal system including an extension device, a connection device, and an impedance device is disclosed. The extension device includes a first connection port and is coupled to a peripheral device. The connection device includes a second connection port and a third connection port. The second connection port is coupled to the first connection port. The third connection port is coupled to an electronic device. The impedance device connects at least one of the first, the second and the third connection ports to ground. | 10-16-2014 |
20140306736 | STATE MACHINE CIRCUIT AND STATE ADJUSTING METHOD - A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit for outputting the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit for outputting the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal. | 10-16-2014 |
20140298060 | ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM - A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized. | 10-02-2014 |
20140298053 | UNIVERSAL SERIAL BUS HUB AND CONTROL METHOD THEREOF - A universal serial bus and a control method thereof are provided. Different voltages are respectively provided to circuit groups when a universal serial bus hub is in a suspend state and a normal working state, so as to reduce leakage current. | 10-02-2014 |
20140297993 | UNCORE MICROCODE ROM - A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions. | 10-02-2014 |
20140293547 | CIRCUIT SUBSTRATE, SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING THE SAME - A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here. | 10-02-2014 |
20140289479 | BOUNDING BOX PREFETCHER - A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters. | 09-25-2014 |
20140258641 | COMMUNICATING PREFETCHERS IN A MICROPROCESSOR - A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern. | 09-11-2014 |
20140223157 | COMPUTER SYSTEM HAVING VOICE-CONTROL FUNCTION AND VOICE-CONTROL METHOD - The invention discloses a computer system having voice-control function. The computer system includes a voice-recognition module, a shared memory, a microcontroller, a power-management module and a central processing unit. The voice-recognition module receives an external voice signal via a microphone and determines whether the external voice signal corresponds to an operation instruction. The shared memory is used for storing shared state information. The microcontroller is used for setting the shared state information according to the operation instruction when the external voice signal corresponds to the operation instruction. The power-management module generates a power-management signal according to the shared state information in the shared memory. When the power-management module transmits the power-management signal, the central processing unit executes a processing operation corresponding to the operation instruction according to the shared state information in the shared memory. | 08-07-2014 |
20140223079 | NON-VOLATILE MEMORY APPARATUS AND OPERATING METHOD THEREOF - A non-volatile memory (NVM) apparatus and an operation method thereof are provided. A mapping table in a main memory is divided into a plurality of sub-mapping tables according to logical address groups. When an access command of a host is processed by the NVM apparatus, at least one corresponding sub-mapping table is selected from the sub-mapping tables according to a logical address of the access command. If the at least one corresponding sub-mapping table is required to be rebuilt, then the at least one corresponding sub-mapping table is rebuilt, and the logical address of the access command is converter for accessing the NVM apparatus according to the at least one corresponding sub-mapping table which has been rebuilt. | 08-07-2014 |
20140223041 | INTEGRATED CIRCUIT USING I2C BUS AND CONTROL METHOD THEREOF - An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (I | 08-07-2014 |
20140210044 | SEMICONDUCTOR DEVICE HAVING INDUCTOR - A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines. | 07-31-2014 |
20140208149 | APPARATUS AND METHOD FOR DYNAMICALLY ALIGNED SOURCE SYNCHRONOUS RECEIVER - An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals. | 07-24-2014 |
20140208148 | AUTOMATIC SOURCE SYNCHRONOUS BUS SIGNAL ALIGNMENT COMPENSATION MECHANISM - An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus. | 07-24-2014 |
20140208147 | APPARATUS AND METHOD FOR LOCALLY OPTIMIZING SOURCE SYNCHRONOUS DATA STROBES - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a bit lag control element and a synchronous lag receiver. The bit lag control element is configured to measure a propagation time beginning with assertion of a strobe and ending with assertion of a first one of a plurality of radially distributed strobes corresponding to the strobe, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive the first one of the plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. | 07-24-2014 |
20140207735 | APPARATUS AND METHOD FOR DYNAMIC ALIGNMENT OF SOURCE SYNCHRONOUS BUS SIGNALS - An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. | 07-24-2014 |
20140204691 | SOURCE SYNCHRONOUS BUS SIGNAL ALIGNMENT COMPENSATION MECHANISM - An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus. | 07-24-2014 |
20140203865 | OUTPUT BUFFERS - An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage. | 07-24-2014 |
20140195840 | METHOD FOR POWER MANAGEMENT AND AN ELECTRONIC SYSTEM USING THE SAME - A power-management method is provided, and the power-management method includes setting a central processing unit in a first low-power state when receiving a second low-power state request requiring the central processing unit to enter the second low-power state, obtaining first idle periods of the peripheral modules respectively to determine a second idle period according to the first idle periods of the peripheral modules, determining whether the peripheral modules have not sent a data-access request during the second idle period, setting the central processing unit in the second low-power state when the peripheral modules have not sent the data-access request during the second idle period, wherein each first idle period is an interval period between two data transmissions of each peripheral module. | 07-10-2014 |
20140195823 | MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN ENCRYPTED AND UNENCRYPTED PROGRAMS - A microprocessor includes an architected register having a bit. The microprocessor sets the bit. The microprocessor also includes a fetch unit that fetches encrypted instructions from an instruction cache and decrypts them prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the value of the bit to a stack in memory and then clears the bit, in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them, after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set. | 07-10-2014 |
20140195822 | MICROPROCESSOR THAT SECURELY DECRYPTS AND EXECUTES ENCRYPTED INSTRUCTIONS - A microprocessor is provided with a method for decrypting encrypted instruction data into plain text instruction data and securely executing the same. The microprocessor includes a master key register file comprising a plurality of master keys. Selection logic circuitry in the microprocessor selects a combination of at least two of the plurality of master keys. Key expansion circuitry in the microprocessor performs mathematical operations on the selected master keys to generate a decryption key having a long effective key length. Instruction decryption circuitry performs an efficient mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data. | 07-10-2014 |
20140195821 | METHOD FOR ENCRYPTING A PROGRAM FOR SUBSEQUENT EXECUTION BY A MICROPROCESSOR CONFIGURED TO DECRYPT AND EXECUTE THE ENCRYPTED PROGRAM - A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information. | 07-10-2014 |
20140195820 | APPARATUS FOR GENERATING A DECRYPTION KEY FOR USE TO DECRYPT A BLOCK OF ENCRYPTED INSTRUCTION DATA BEING FETCHED FROM AN INSTRUCTION CACHE IN A MICROPROCESSOR - An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key. | 07-10-2014 |
20140188835 | SEARCH METHOD, SEARCH SYSTEM, AND NATURAL LANGUAGE COMPREHENSION SYSTEM - A search method, a search system, and a natural language comprehension system are provided. The search system includes a structured database and a search engine. The structured database stores a plurality of records, each of which has a title field and a content field. The title field includes at least one sub-field, and each sub-field includes an indication field and a value field. The indication field stores indication data, the value field stores value data, and the content field stores detailed content data. The search engine conducts a full-text search to the records in the structured database according to a keyword derived from a user's request formation, and a search result is transmitted to a knowledge comprehension assistance module, so as to recognize the user's intention. After the user's intention is recognized, information associated with the recognized user's intention is transmitted back to the user. | 07-03-2014 |
20140188478 | NATURAL LANGUAGE DIALOGUE METHOD AND NATURAL LANGUAGE DIALOGUE SYSTEM - A natural language dialogue method and a natural language dialogue system are provided. In the method, a first speech input is received and parsed to generate at least one keyword included in the first speech input, so that a candidate list including at least one report answer is obtained. According to a properties database, one report answer is selected from the candidate list, and a first speech response is output according to the report answer. Other speech inputs are received, and a user's preference data is captured from the speech inputs. The user's preference data is stored in the properties database. | 07-03-2014 |
20140188477 | METHOD FOR CORRECTING A SPEECH RESPONSE AND NATURAL LANGUAGE DIALOGUE SYSTEM - A natural language dialogue system and a method capable of correcting a speech response are provided. The method includes following steps. A first speech input is received. At least one keyword included in the first speech input is parsed to obtain a candidate list having at least one report answers. One of the report answers is selected from the candidate list as a first report answer, and a first speech response is output according to the first report answer. A second speech input is received and parsed to determine whether the first report answer is correct. If the first report answer is incorrect, another report answer other than the first report answer is selected from the candidate list as a second report answer. According to the second report answer, a second speech response is output. | 07-03-2014 |
20140173301 | POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR - A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications. | 06-19-2014 |
20140167714 | SOFT-START CIRCUITS AND POWER SUPPLIERS USING THE SAME - A soft-start circuit is provided. The soft-start circuit generates an output voltage at an output terminal. The soft-start includes a transistor, a capacitor, and a current source. The transistor has a first terminal receiving an input voltage, a second terminal coupled to the output terminal, and a control terminal. The capacitor is coupled between the second terminal and the control terminal of the transistor. The current source is coupled between the control terminal of the transistor and a ground terminal. The capacitor and the current source modulate the output voltage by modulating a driving voltage at the control terminal to perform a soft-start operation of the output voltage. | 06-19-2014 |
20140164816 | DISTRIBUTED MANAGEMENT OF A SHARED CLOCK SOURCE TO A MULTI-CORE MICROPROCESSOR - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores. | 06-12-2014 |
20140149122 | VOICE CONTROL DEVICE AND VOICE CONTROL METHOD - A voice control device and a corresponding voice control method are provided. The voice control device includes a sound receiver, a sound converter, a voice identifier, and a central processing unit (CPU). The sound receiver receives a first sound signal. The sound converter converts the first sound signal from analog signal to digital signal. The voice identifier identifies a first voice signal from the first sound signal, performs a first comparison on the first voice signal and a second voice signal, and generates a wake-up signal according to the first comparison. When receiving the wake-up signal, the CPU enters a working state from a sleeping state, performs a second comparison on the first voice signal and the second voice signal, and takes over the voice input from the sound receiver and the sound converter according to the second comparison. | 05-29-2014 |
20140132213 | BATTERY MANAGEMENT SYSTEM AND ELECTRIC VEHICLE - A battery management system for use in an electric vehicle is provided. The battery management system has: a battery module, configured to provide power to drive the electric vehicle; and a charging module, configured to detect a type of a USB device coupled to the battery management system, and charge the USB device by using power from the battery module according to the type of the USB device. | 05-15-2014 |
20140129818 | ELECTRONIC DEVICE AND BOOTING METHOD - The present invention provides an electronic device including a write-once-then-read-only register, a chipset, a read-only memory, a flash memory and a central processor. The write-once-then-read-only register is arranged to store a determination value. The chipset is arranged to produce a CPU reset signal. The read-only memory is implemented in the chipset, and has a first memory block which corresponds to a predetermined address and is used to store a first instruction. The flash memory is coupled to the chipset, and has a second memory block which corresponds to the predetermined address and is used to store a second instruction. The central processor is arranged to determine the location of the predetermined address according to the CPU reset signal and the determination value. | 05-08-2014 |
20140115531 | METHOD AND APPARATUS FOR RENDERING OVERLAPPED OBJECTS - A method and apparatus for rendering overlapped objects are provided. In the method, multiple objects are sorted according to rendering properties thereof and placed into a source chain. As for a target object in the source chain, an object first overlapped with the target object is successively searched. If no overlapped object is found, the target object is moved to a target chain. Otherwise, a blending object is generated by blending an overlapping area of the target object and overlapped object according to an alpha-blending property thereof and the blending object and all non-overlapping areas of the target object and overlapped object are inserted respectively as a new object into the source chain. The above steps are repeated until all objects in the source chain are moved to the target chain. Finally, the objects in the target chain are rendered on an electronic device. | 04-24-2014 |
20140115314 | ELECTRONIC DEVICE AND SECURE BOOT METHOD - An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor. | 04-24-2014 |
20140115284 | PROGRESS RECORDING METHOD AND RECOVERING METHOD FOR ENCODING OPERATION ON STORAGE DEVICE - A progress recording method and a corresponding recovering method adapted to an encoding operation performed on a storage area of a storage device are provided. The progress recording method includes the following steps. A variable set is initialized and stored. The encoding operation includes a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set. The flag variables are used for recording execution progresses of the sub-operations. When each of the sub-operations is executed, the corresponding flag variable in the variable set is updated according to the execution progress of the sub-operation. | 04-24-2014 |
20140097703 | POWER SUPPLY SYSTEM AND POWER CONTROL CIRCUIT THEREOF - A power supply system for supplying power to a chipset of an electronic device is provided. The power supply system includes a voltage converter, converting a supply voltage of a power supply into a predetermined voltage and supplying the predetermined voltage to the chipset, and a power control circuit connected between the voltage converter and the power supply. The power control circuit further includes a switch and a switch controller. The switch has a first terminal connected to the power supply, a second terminal connected to the voltage converter and a control terminal The switch controller, connected to the control terminal of the switch and the chipset, controls the switch to couple the power supply to the voltage converter according to the turning-on of the power supply system. | 04-10-2014 |
20140094300 | DISPLAY SYSTEM AND DISPLAY METHOD FOR VIDEO WALL - A display system and a display method for video walls are provided. The display system includes at least one server and a plurality of player devices. Each server renders an image and transmits the image to a network. The player devices are coupled to the at least one server through the network. Each player device receives the image or a part of the image rendered by one of the at least one server, and determines a synchronization time together with at least one of the other player devices. Each player device uses a display of a video wall to simultaneously display the image or the part of the image at the synchronization time. | 04-03-2014 |
20140086297 | TRANSMISSION CIRCUIT FOR I/O INTERFACE AND SIGNAL TRANSMISSION METHOD THEREOF - A transmission circuit including an equalizer circuit, a slicer circuit, a signal detection circuit, and a control circuit is provided. The equalizer circuit performs an equalizing operation on an input signal according to preset states to output an equalizing signal corresponding to each preset state. The slicer circuit performs a slicing operation on the equalizing signal to output a slicing signal. The signal detection circuit detects and compares the equalizing signal and the slicing signal and accordingly adjusts the equalizer circuit to one of the preset states. The control circuit receives the slicing signal corresponding to each preset state, compares the slicing signal corresponding to each preset state with a plurality of signal patterns to generate a comparison result, and selects one of the preset states according to the comparison result, such that the control circuit let the equalizer circuit perform the equalizing operation according to the selected preset state. | 03-27-2014 |
20140084427 | MULTI-CORE DIES PRODUCED BY RETICLE SET MODIFICATION - A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus. | 03-27-2014 |
20140077357 | CIRCUIT SUBSTRATE AND PROCESS FOR FABRICATING THE SAME - A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided. | 03-20-2014 |
20140059358 | REVOKEABLE MSR PASSWORD PROTECTION - A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key. | 02-27-2014 |
20140059267 | USB TRANSACTION TRANSLATOR AND USB TRANSACTION TRANSLATION METHOD - A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. | 02-27-2014 |
20140047142 | DATA TRANSMISSION SYSTEM AND METHOD THEREOF - A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device. | 02-13-2014 |
20140025726 | HARDWARE RESOURCE ACCESSING SYSTEMS AND METHODS FOR ACCESSING HARDWARE RESOURCES IN BROWSER-BASED OPERATING SYSTEMS AND MACHINE-READABLE STORAGE MEDIUM THEREOF - Methods for accessing hardware resources in an electronic device with a browser-based operating system (OS) which includes a user interface running in a browser are provided. A local server is first provided on the electronic device, wherein the local server has a corresponding URL and a dedicated network port. Then, upon receiving a service request from the client-side web application, the local server analyzes a service type of the service request and performs an operation to at least one of the hardware resources corresponding to the service type, wherein the service request is generated and directed to the local server according to the URL and the dedicated network port of the local server by the client-side web application on the electronic device. | 01-23-2014 |
20140013089 | CONDITIONAL LOAD INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR - A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction. | 01-09-2014 |
20140013058 | PREFETCHING OF NEXT PHYSICALLY SEQUENTIAL CACHE LINE AFTER CACHE LINE THAT INCLUDES LOADED PAGE TABLE ENTRY - A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line. | 01-09-2014 |
20140006718 | DATA PREFETCHER WITH COMPLEX STRIDE PREDICTOR | 01-02-2014 |
20140000953 | CIRCUIT SUBSTRATE | 01-02-2014 |
20130335167 | DE-NOISE CIRCUIT AND DE-NOISE METHOD FOR DIFFERENTIAL SIGNALS AND CHIP FOR RECEIVING DIFFERENTIAL SIGNALS - A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value. | 12-19-2013 |
20130332496 | SATURATION DETECTOR - A hardware integer saturation detector that detects both whether packing a 32-bit integer value causes saturation and whether packing each of first and second 16-bit integer values causes saturation, where the first 16-bit integer value is the upper 16 bits of the 32-bit integer value and the second 16-bit integer value is the lower 16 bits of the 32-bit integer value. The detector includes hardware signal logic, configured to generate four signals with information about the integer values. The hardware integer detector also includes saturation logic, configured to gate the four signals to generate a saturation signal. Each bit of the saturation signal indicates whether packing the 32-bit integer value or whether packing one of the first and second 16-bit integer values will cause saturation respectively. | 12-12-2013 |
20130321437 | GRAPHICS PROCESSING UNIT AND MANAGEMENT METHOD THEREOF - A graphics processing unit (GPU) and a management method of the GPU are provided. The GPU includes at least one graphics engine and an engine manager. The graphics engine performs a video decoding function or a graphics rendering function according to a graphics command from a driver software. The engine manager records a workload index of each graphics engine. The engine manager also adjusts the work ability of one of or more of the at least one graphics engine according to an adjustment command from the driver software. The driver software provides the adjustment command according to the workload index. | 12-05-2013 |
20130318530 | DEADLOCK/LIVELOCK RESOLUTION USING SERVICE PROCESSOR - A microprocessor includes a main processor and a service processor. The service processor is configured to detect and break a deadlock/livelock condition in the main processor. The service processor detects the deadlock/livelock condition by detecting the main processor has not retired an instruction or completed a processor bus transaction for a predetermined number of clock cycles. In response to detecting the deadlock/livelock condition in the main processor, the service processor causes arbitration requests to a cache memory to be captured in a buffer, analyzes the captured requests to detect a pattern that may indicate a bug causing the condition and performs actions associated with the pattern to break the deadlock/livelock. The actions include suppression of arbitration requests to the cache, suppression of comparisons cache request addresses and killing requests to access the cache. | 11-28-2013 |
20130311755 | RUNNING STATE POWER SAVING VIA REDUCED INSTRUCTIONS PER CLOCK OPERATION - A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states. | 11-21-2013 |
20130305014 | MICROPROCESSOR THAT ENABLES ARM ISA PROGRAM TO ACCESS 64-BIT GENERAL PURPOSE REGISTERS WRITTEN BY X86 ISA PROGRAM - A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures. | 11-14-2013 |
20130305013 | MICROPROCESSOR THAT MAKES 64-BIT GENERAL PURPOSE REGISTERS AVAILABLE IN MSR ADDRESS SPACE WHILE OPERATING IN NON-64-BIT MODE - A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers. In response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers. The microprocessor does so even when operating in non-64-modes. | 11-14-2013 |
20130304961 | HUB CONTROL CHIP - A HUB control chip implemented in a specific package is provided. The HUB control chip includes a plurality of transmission modules and a plurality of pins. The plurality of the pins include: a plurality of data pin groups coupled to one of the plurality of transmission modules respectively. Each of the plurality of data pin groups includes: a first sub-group, receiving and transmitting a first pair of differential signals conforming to the USB 2.0 standard; a second sub-group, receiving a second pair of differential signals conforming to the USB 3.0 standard; and a third sub-group, transmitting a third pair of differential signals conforming to the USB 3.0 standard. The number of the plurality of the pins is less than or equal to 52. | 11-14-2013 |
20130297951 | OPERATION SYSTEM AND CONTROL METHOD THEREOF - An operation system including a chipset and a detection unit is disclosed. The chipset includes a first circuit group receiving a plurality of operation voltages. The detection unit generates a control signal to control the first circuit group to stop accessing a memory device when an external power is abnormal. A level of the control signal switches before variation in a level of a first operation voltage among the operation voltages. The variation is induced when the external power is abnormal. | 11-07-2013 |
20130268575 | CLOUD-COMPUTING GRAPHIC SERVER - The invention provides a cloud-computing graphic server. In one embodiment, the cloud-computing graphic server is coupled to a client host via a network, and includes a plurality of back-end graphic servers and at least one front-end graphic server. The graphic server is coupled to the back-end graphic servers via a high-speed network, receives a request from the client host via the network, determines a plurality of application programs required by the request, and selects a plurality of used back-end graphic servers respectively corresponding to the application programs from the back-end graphic servers. The used back-end graphic servers execute the application programs according to instructions from the front-end graphic server to generate a plurality of graphic surfaces, and the front-end graphic server blends the graphic surfaces to obtain a windows surface datastream and sends the windows surface datastream back to the client host for display via the network. | 10-10-2013 |
20130259444 | METHOD OF MANAGING MULTIPLE WIRELESS VIDEO TRAFFIC AND ELECTRONIC DEVICE THEREOF - A method and a playback control device are provided. The method, performed by the playback control device, includes: receiving a first request to playback a first data of a first wireless multimedia data type having a first priority; and playing back the first data if no other data of a wireless multimedia data type having a priority higher than the first priority is received. | 10-03-2013 |
20130230132 | RECEIVER AND SIGNAL TESTING METHOD THEREOF - A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same. | 09-05-2013 |
20130226997 | Networked Applications with Client-Caching of Executable Modules - Disclosed are various embodiments for providing networked applications that are segmented into multiple client-cached executable modules. Multiple networked applications are provided by an application server, and a module cache is maintained in a client. The client obtains a user invocation of a particular functionality associated with a networked application. One of the modules associated with the particular functionality is obtained by the client from the application server over a network in response to determining that the module is not already in the module cache. The module is executed by the client to provide the particular functionality. A data cache may be implemented that includes data blocks that have been used, are being used, or are predicted to be used by the networked application. | 08-29-2013 |
20130222020 | FREQUENCY-CONTROL CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops. | 08-29-2013 |
20130213692 | FABRICATING METHOD OF CIRCUIT BOARD AND CIRCUIT BOARD - A method of fabricating a circuit board includes the following steps. A first and a second patterned conductive layer are plated on the first and the second surface of a core substrate, respectively. A first and a second extending pad are individually plated on a first and a second pad of the first and the second patterned conductive layer, respectively. A first and a second thermal-curing type dielectric layer are individually formed on the first and the second surface to cover the first and the second patterned conductive layer and the first and the second extending pad, respectively. A portion of the first and the second thermal-curing type dielectric layer respectively covering the top of the first and the second extending pad are removed. A protective film covers the second extending pad. The extending pad is removed by an etching process. | 08-22-2013 |
20130191653 | USB HUB FOR SUPPLYING POWER AND METHOD THEREOF - A USB hub and a method thereof. The USB hub supplies power to a USB device, is connected between the USB device and a USB host under a working power state, and comprises an upstream port, a downstream port, a power port, and a controller. The upstream port is coupled to the USB host. The downstream port is coupled to the USB device. The power port is coupled to a power source. The controller is coupled to the upstream port, the downstream port, and the power port, and determines whether the USB host has left the working power state, and determines whether the USB device is electrically chargeable, when the USB host has left the working power state. The downstream port provides power to the USB device from the power source when the USB device is electrically chargeable. | 07-25-2013 |
20130187657 | DISCHARGE CURVE CALIBRATION SYSTEM AND CALIBRATION METHOD FOR INITIAL DISCHARGING CURVE OF BATTERY - An embodiment of the invention provides a calibration method for an initial discharging curve of a battery. The method includes: acquiring an initial discharging curve of a battery; measuring a first open circuit voltage at a first time point and a second open circuit voltage at a second time point; according to the initial discharging curve, acquiring a first discharge capacity corresponding to the first open circuit voltage and a second discharge capacity corresponding to the second open circuit voltage according to the initial discharging curve; calculating an ideal discharge capacity according to the first discharge capacity and the second discharge capacity; measuring an real discharge capacity between the first time point and the second time point; determining a total discharge capacity difference according to the ideal discharge capacity and the real discharge capacity to calibrate the initial discharging curve to generate a current discharging curve. | 07-25-2013 |
20130187609 | RECHARGEABLE BATTERY MODULE AND BATTERY CHARGING METHOD - An embodiment of the invention provides a rechargeable battery module including a battery bank having serial connected battery units, a charging transistor providing a charging current to the battery bank, a balancing circuit for detecting and balancing voltage values of battery units and battery bank and a control chip. When a first voltage value of a first battery unit reaches a charge-off voltage, the control chip estimates a first unbalanced voltage difference between the first voltage and the minimal voltage among battery units. The control chip disables the charging transistor and estimates a second unbalanced voltage difference between voltages of the first battery unit and the battery unit having a minimal voltage. The control chip enables the balancing circuit to balance the first battery unit. When the voltage of the first battery is dropped by a calibration target, the charging transistor is enabled. | 07-25-2013 |
20130187608 | RECHARGEABLE BATTERY MODULE AND BATTERY CHARGING METHOD - A rechargeable battery module including a plurality of battery cells connected in series, a charging transistor, a balancing circuit and a control chip. The charging transistor is operative to convey a charging current to charge the battery cells. Based on voltage levels of the battery cells, the control chip disables the charging transistor and controls the balancing circuit to perform a first stage battery balance process. After finishing the first stage battery balance process, the control chip enables the charging transistor to charge the battery cells again. After being switched to a constant voltage charging mode, the control chip controls the balancing circuit based on the voltage levels of the battery cells to perform a second stage battery balance process. | 07-25-2013 |
20130179748 | SYSTEMS AND METHODS FOR ERROR CHECKING AND CORRECTING FOR MEMORY MODULE - Methods for error checking and correcting (ECC) in a memory module including at least one memory unit are provided. The method includes the steps of: receiving input data from the memory unit; performing, by a first ECC module, a first ECC operation to the input data and generating a decoding result which indicates whether decoding was successful; and determining whether to activate a second ECC module to perform a second ECC operation to the input data according to the decoding result, wherein the first and second ECC modules respectively utilize a first method and a second method, wherein the first method applies a ECC with a first fault tolerant quantity for error correction and the second method applies a ECC with a second fault tolerant quantity for error correction, and the second fault tolerant quantity is larger than the first fault tolerant quantity. | 07-11-2013 |
20130179710 | MULTI-CORE PROCESSOR SYSTEM, DYNAMIC POWER MANAGEMENT METHOD THEREOF AND CONTROL APPARATUS THEREOF - A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off. | 07-11-2013 |
20130179604 | DATA TRANSMISSION METHODS AND HUB DEVICES UTILIZING THE SAME - A hub device includes an upstream port, multiple downstream ports, a first and a second sub-hub module, a data-format detector, a transaction translator, and a controller. The upstream port is coupled to a host device supporting a first and/or a second data format. Each downstream port is coupled to one of a plurality of slave devices supporting a first and/or a second data format. The first sub-hub module supports transmission of data in the first data format. The second sub-hub module supports transmission of data in the second data format. The data-format detector detects the data format supported by the host device and the slave devices. The transaction translator transforms the data format between the first data format and the second data format. The controller determines whether to control the transaction translator to perform data-format transformation. | 07-11-2013 |
20130175681 | CHIP PACKAGE STRUCTURE - A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier. | 07-11-2013 |
20130162635 | Image Codec Engine - A method implemented in a graphics engine for decoding image blocks to derive an original image is provided. The method comprises receiving at least one encoded image data block at a block decoder, the at least one encoded image data block comprising a plurality of codewords and a bitmap. The method further comprises determining a block type based on the plurality of codewords and selecting a decoder unit among a plurality of decoder units in accordance with the block type. | 06-27-2013 |
20130151881 | BRIDGING DEVICE AND POWER SAVING METHOD THEREOF - A bridging device and a power saving method thereof are disclosed. When a bridging chip of the bridging device receives a power saving command transferred from a host and thereby enters a power saving state, a voltage converter of the bridging device is disabled accordingly and a selection circuit selects to couple a bus voltage to the bridging chip to power the bridging chip. The bus voltage is transferred from the host through a power pin of a connector of the bridging device. The connector is coupled to the host. | 06-13-2013 |
20130151749 | APPARATUS FOR COUPLING TO A USB DEVICE AND A HOST AND METHOD THEREOF - An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result. | 06-13-2013 |
20130151731 | USB CHARGING MODULE - An apparatus is provided for charging a Universal Serial Bus (USB) device according to an optimal charging mode. The apparatus includes a charging module that is configured to obtain a descriptor from the USB device upon detection of the USB device on a USB bus. The charging module includes one or more descriptor entries disposed in a memory and a controller. The one or more descriptor entries include descriptor data, for matching the descriptor to a specific descriptor entry, and charging data, that specifies the optimal charging mode for the USB device. The controller is coupled to the memory, and is configured to match the descriptor to the specific descriptor entry, and is configured to initiate the optimal charging mode on the USB bus according to the charging data. | 06-13-2013 |
20130148258 | CAPACITOR STRUCTURE - A capacitor structure including a dielectric material layer and at least two metal layers is provided. The metal layers are disposed at intervals in the dielectric material layer. Each of the metal layers includes a zigzaging electrode, a first finger-shaped electrode and a second finger-shaped electrode. The zigzaging electrode forms a plurality of first concave parts disposed at one side of the zigzaging electrode and a plurality of second concave parts disposed at the other side of the zigzaging electrode. The first finger-shaped electrode includes a plurality of first extension parts. The first extension parts are respectively disposed in the first concave parts. The second finger-shaped electrode includes a plurality of second extension parts. The second extension parts are respectively disposed in the second concave parts. The zigzaging electrode in each of the metal layers is electrically coupled to the first and second finger-shaped electrodes of adjacent metal layers. | 06-13-2013 |
20130132746 | BRIDGING DEVICE AND POWER SAVING METHOD THEREOF - A bridging device and a power saving method thereof are disclosed. The disclosed bridging device includes a connector, a connection detector and a bridging chip. The connector is operative to connect to a host and includes a power pin and a command pin. The connection detector is coupled to the power pin to determine whether the connector is floating, and, outputs a linked signal when the connection is non-floating. The bridging chip is coupled to the command pin and the connection detector. When the bridging chip receives a power saving command transferred from the host via the command pin and the linked signal transferred from the connection detector, the bridging chip executes a power saving operation. | 05-23-2013 |
20130129283 | ACTIVE OPTICAL CABLE AND ELECTRONIC DEVICE USING THE SAME - An active optical cable has a connector containing an electrical-to-optical and optical-to-electrical (EO/OE) conversion processing chip. The EO/OE conversion processing chip has a TXin+ pin and a TXin− pin to be coupled to a TX+ terminal and a TX− terminal of an USB connector of an apparatus. The pair of pins TXin+ and TXin−, for a differential transmission signal, are provided base on a common mode impedance structure, to charge capacitors carried by the TX+ and TX− terminals and, according to the charging status of the capacitors, it is determined whether the active optical cable is connected to the apparatus. | 05-23-2013 |
20130119938 | CIRCUIT AND SYSTEM AND METHOD FOR CONTROLLING BATTERY - A battery control circuit for balancing a battery includes a voltage detector, a controller, a balancing device, and a switch. The voltage detector is configured to detect a voltage difference of the battery so as to generate a detecting signal. The controller is configured to generate a control signal according to the detecting signal. The switch is coupled between the battery and the balancing device, and is opened or closed according to the control signal, wherein if the voltage difference is greater than a threshold value, the switch is closed and the balancing device draws a load current from the battery, and if the voltage difference is smaller than or equal to the threshold value, the switch is opened and the balancing device is not capable of drawing any current. | 05-16-2013 |
20130114173 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region. | 05-09-2013 |
20130113728 | SINGLE-POINT-MULTI-FINGER GESTURES FOR TOUCH PANEL - A controlling device applied to a touch panel. The controlling device includes a sampling module, a determining module and a reporting module. The sampling module samples electrical signals of the touch panel, and generates at least one trigger signal corresponding to the at least one touch event when at least one touch event occurs on the touch panel. The determining module determines whether the at least one touch event is a single-point-multi-finger gesture according to a position of the at least one trigger signal and sampled physical quantity. The reporting module reports the at least one touch event when the determining module determines that the at least one touch event corresponding to the at least one trigger signal is the single-point-multi-finger gesture. | 05-09-2013 |
20130103872 | COMPUTER APPARATUS AND METHOD FOR DISTRIBUTING INTERRUPT TASKS THEREOF - A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to each of the CPUs. The chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs. If a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type, so as to perform a corresponding interrupt task. | 04-25-2013 |
20130099840 | DUTY ADJUSTMENT CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal. | 04-25-2013 |
20130086292 | Systems and Methods for Hot-Plug Detection Recovery - One embodiment is a method for establishing a link between a source device and a sink device. The method comprises enabling a hot plug detect (HPD) handler in the source device, utilizing the HPD handler to receive an HPD interrupt upon the sink device being coupled to the source device, applying one or more predetermined parameters corresponding to the HPD interrupt to establish the link between the source device and the sink device, and adjusting the one or more predetermined parameters if the link between the source device and the sink device is not established. | 04-04-2013 |
20130085763 | CODEC DEVICES AND OPERATING AND DRIVING METHOD THEREOF - The present application discloses coding and decoding (CODEC) devices and operating and driving methods thereof. The CODEC device includes a first interface compatible with High Definition Audio (HDA) specification, a second interface compatible with Musical Instrument Digital Interface (MIDI) specification, and a converter. The converter is configured to convert a first MIDI command received from the first interface and output a corresponding first converted MIDI command via the second interface, and to convert a second MIDI command received from the second interface and output a corresponding second converted MIDI command via the first interface. | 04-04-2013 |
20130076404 | LOW VOLTAGE DIFFERENTIAL SIGNAL DRIVING CIRCUIT AND ELECTRONIC DEVICE COMPATIBLE WITH WIRED TRANSMISSION - A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal. | 03-28-2013 |
20130067455 | MEMORY ONLINE UPDATE SYSTEM AND METHOD - An online upgrade system/method for a memory. The system includes a host and an electronic device. An application is executed by the host and contains parameter records for different memory model types. The electronic device includes a memory and a device controller. The application distinguishes the model type of the memory equipped in the electronic device, and according to the model type of the memory, the application provides the device controller with the parameter record corresponding thereto and thereby the application upgrades the contents of the memory through the device controller. | 03-14-2013 |
20130067202 | CONDITIONAL NON-BRANCH INSTRUCTION PREDICTION - A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions. | 03-14-2013 |
20130067199 | CONTROL REGISTER MAPPING IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE PROCESSOR - A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR. | 03-14-2013 |
20130064322 | FREQUENCY-CONTROL CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit is arranged to charge/discharge a voltage-control node according to a comparison result signal. The voltage-controlled delay line is arranged to generate a control signal according to the comparison result signal and a control voltage of the voltage-control node to control the output signal. A frequency of the control signal is modulated by the voltage-controlled delay line according to the control voltage of the voltage-control node. The comparison result signal is generated according to a difference between a reference voltage and a voltage level of the output signal. | 03-14-2013 |
20130059453 | INTEGRATED CIRCUITS - An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for coupling to a first pair of differential pins of the USB receptacle, a second group for coupling to a second pair of differential pins of the USB receptacle, a third group for coupling to a third pair of differential pins to the USB receptacle, a ground pin, a first and second power pins. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the USB 2.0 or USB 3.0 signals. | 03-07-2013 |
20130050201 | METHOD OF IMAGE DEPTH ESTIMATION AND APPARATUS THEREOF - A method and an apparatus of image depth estimation are provided. The method includes the following steps. First, a hue value of each pixel in an image is calculated by comparing all color components of each pixel in the image. The hue value of each pixel in the image is associated with a corresponding value, wherein the corresponding value is a first numerical value or a second numerical value. Then, according to the corresponding value of each pixel in the image, a depth value of each pixel in the image is calculated, in which the depth value is used to convert the image into a three-dimensional (3D) image to be displayed on a 3D display apparatus. | 02-28-2013 |
20130050158 | GRAPHICS CARD, MULTI-SCREEN DISPLAY SYSTEM AND SYNCHRONOUS DISPLAY METHOD - A graphics card, a multi-screen display system and a synchronous display method are disclosed. The disclosed method includes the following steps. Firstly, first clock signals are provided in parallel in response to a first clock signal transferred from a motherboard. A second clock signal is generated according to one of the first clock signals that are provided in parallel, wherein the oscillation frequency of the first clock signals is larger than the oscillating frequency of the second clock signal. Then, a set of display clocks are generated based on the second clock signal. The set of display clocks control the display of a set of screens, for synchronous multi-screen display. | 02-28-2013 |
20130025926 | CIRCUIT SUBSTRATE - A circuit substrate having a base layer, a patterned conductive layer, a dielectric layer and a conductive block is provided. The patterned conductive layer is disposed on the base layer and having an inner pad. The dielectric layer is disposed on the base layer and covering the patterned conductive layer. The conductive block penetrates the dielectric layer, the conductive block being substantially coplanar with the dielectric layer and connecting the inner pad. | 01-31-2013 |
20130013819 | TRANSMISSION SYSTEM AND METHOD THEREOF - A transmission system receiving a first token packet and a second token packet is disclosed. The transmission system is coupled to a first peripheral device and a second peripheral device. The transmission system includes an upstream port to receive the first and the second token packets. A first transmission path occurs between the upstream port and the first peripheral device. A second transmission path occurs between the upstream port and the second peripheral device. The transmission system analyzes the first and the second token packets. The first token packet includes information corresponding to the first peripheral device. When the second token packet includes information corresponding to the first peripheral device, the transmission system disables the second transmission path. | 01-10-2013 |
20130012067 | LEAD ARRANGEMENT, ELECTRIC CONNECTOR AND ELECTRIC ASSEMBLY - A lead arrangement is suitable for an electric connector. The lead arrangement includes a first lead lane that includes a pair of first differential signal leads, a pair of second differential signal leads and a first ground lead between the two pairs of differential signal leads. Each of the first differential signal leads, the second differential signal leads and the ground lead has a surface mounting segment adapted for being soldered onto a surface pad of a circuit board. The pair of first differential signal leads is a pair of transmitting differential signal leads T | 01-10-2013 |
20130002688 | METHOD FOR CONTROLLING MULTIPLE DISPLAYS AND SYSTEM THEREOF - A method and system for controlling multiple displays is provided. The disclosed method is used to control a plurality of graphics processing units (GPUs), wherein every GPU controls one or more displays. The method includes the following steps: providing a graphical interface the same to a graphical program library of an operating system to replace the graphical program library to receive a drawing command from an application program; determining a display set of the GPUs according to a display region of the application program, wherein a frame displayed by the display controlled by each GPU is intersected to the display region; and delivering coordinate-transformed drawing commands to the GPUs in the display set according to the display intersection region, wherein each GPU in the display set only draws the content of the corresponding display intersection region. | 01-03-2013 |
20120331330 | PROGRAMMABLE MECHANISM FOR OPTIMIZING A SYNCHRONOUS DATA BUS - An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount. | 12-27-2012 |
20120331329 | OPTIMIZED SYNCHRONOUS DATA RECEPTION MECHANISM - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals. | 12-27-2012 |
20120331328 | APPARATUS AND METHOD FOR DELAYED SYNCHRONOUS DATA RECEPTION - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a delay-locked loop (DLL). The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group. The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal. | 12-27-2012 |
20120331327 | OPTIMIZED SYNCHRONOUS STROBE TRANSMISSION MECHANISM - An apparatus that compensates for misalignment on a synchronous data bus, including a resistor network, a transmitting device, and a receiving device. The resistor network indicates an amount to advance a synchronous data strobe associated with a data group. The transmitting device has a core clocks generator and a synchronous strobe driver. The core clocks generator advances a data strobe clock by the amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe is advanced also by the amount. The receiving device has a composite delay element and delay-locked loops (DLLs). The composite delay element equalizes delay paths within the receiving device, where the delay paths correspond to the synchronous data strobe that is received from the transmitting device. | 12-27-2012 |
20120331326 | APPARATUS AND METHOD FOR ADVANCED SYNCHRONOUS STROBE TRANSMISSION - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount. | 12-27-2012 |
20120331325 | PROGRAMMABLE MECHANISM FOR DELAYED SYNCHRONOUS DATA RECEPTION - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal. | 12-27-2012 |
20120331324 | PROGRAMMABLE MECHANISM FOR SYNCHRONOUS STROBE ADVANCE - An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount. | 12-27-2012 |
20120331179 | NETWORK-TO-NETWORK BRIDGE - A network-to-network bridge is provided. In one embodiment, the network-to-network bridge is coupled between a main system and a subsystem system. The main system includes a slot to couple with the subsystem, wherein the slot complies with the PCIe standard. The network-to-network bridge includes a transport layer and an internet layer but lacks of a network access layer allocated between the first main system and subsystem so as to transfer data by following the PCIe standard therebetween. The network-to-network bridge transfers data between the main system and the subsystem by accessing and employing their MAC addresses, and the network-to-network bridge can be allocated in the mainboard of the main system or the subsystem. | 12-27-2012 |
20120307988 | COMPUTER SYSTEM AND PROCESSOR HAVING INTEGRATED PHONE FUNCTIONALITY - A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated. | 12-06-2012 |
20120303978 | COMPUTER INTEGRAL DEVICE SYSTEM AND METHOD THEREOF - A computer integral device includes a detection unit for detecting whether an external electronic device is in a determined position, wherein the external electronic device has been turned on; and a computer host, coupled to the detection unit. When the external electronic device is detected to be in the determined position, a power enable signal is sent to the computer host so as to activate the computer host to execute a computer turn on process. After the computer turn on process is executed by the computer host, the external electronic device may display image data received via a wireless communication link established between the computer host and the external electronic device. | 11-29-2012 |
20120301027 | IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD - An image processing apparatus and a method thereof are provided. A plurality of target blur radii are obtained by calculating blur radiuses corresponding to the out of focus transform function between a deblurred datum color channel image and the other color channel images. A plurality of deblurred color channel images are obtained by respectively performing deblurring operations on the original channel images according to the target blur radii that are corresponding to the original channel images. The deblurred datum color channel image and the deblurred color channel images are combined to obtain a blur calibrated image. Accordingly, the image out of focus problem induced by dispersion can be solved. | 11-29-2012 |
20120301016 | IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD - An image processing system and an image processing method are provided. The image processing method includes following steps. Transformation matrixes between color channel images are obtained according to feature points in the color channel images. A transformation matrix having the minimum distortion is selected to determine a shift datum color channel image. The other color channel images are transformed according to the transformation matrixes corresponding to the shift datum color channel image. The shift datum color channel image and the transformed color channel images are combined to obtain a shift calibrated image. Thereby, the dispersion problem is resolved. | 11-29-2012 |
20120299910 | Z-CULLING METHOD, THREE-DIMENSIONAL GRAPHICS PROCESSING METHOD AND APPARATUS THREROF - A Z culling method, a three-dimensional graphics processing method using Z-culling, and an apparatus thereof are provided. The Z-culling method includes the following steps. A Z cache memory is provided to buffer a cover mask and a dynamic maximum depth value corresponding to each tile. A draw mask, a draw maximum depth value, and a draw minimum depth value calculated according to the tile and a drawn part are obtained. Moreover, whether the drawn part is completely included in a known part of the cover mask is judged, and coordinated with a comparison of the draw minimum depth value and the dynamic maximum depth value, so as to determine whether to discard the drawn part and whether to update the cover mask and the dynamic maximum depth value in the Z cache memory. Accordingly, the bandwidth taken up in the system memory is reduced efficiently. | 11-29-2012 |
20120299192 | PAD STRUCTURE, CIRCUIT CARRIER AND INTEGRATED CIRCUIT CHIP - A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad. | 11-29-2012 |
20120297222 | BRIDGES AND OPERATION METHODS THEREFOR - A bridge is provided. The bridge is coupled between a host and a peripheral apparatus and includes a connector, a power circuit, and a bridge circuit. The connector connects the host and comprises a power pin. The power circuit converts a supplying power to a driving voltage when the power circuit is enabled. The bridge circuit is powered by the driving voltage and performs a data transmission procedure between the host and the peripheral apparatus. An enabling terminal of the power circuit is coupled to the power pin to receive an enabling signal transmitted by the host through the power pin. The power circuit is enabled to provide the driving voltage when the enabling signal is provided with a first potential. The power circuit is disabled to stop providing the driving voltage when the enabling signal is provided with a second potential. | 11-22-2012 |
20120293512 | THREE-DIMENSIONAL GRAPHICS CLIPPING METHOD, THREE-DIMENSIONAL GRAPHICS DISPLAYING METHOD, AND GRAPHICS PROCESSING APPARATUS USING THE SAME - A three-dimensional (3D) graphics clipping method, a 3D graphics displaying method, and a 3D graphics processing apparatus using the same are provided. The 3D graphics clipping method includes following steps. A plurality of vertexes of a triangle is obtained, wherein a 3D object is constructed by using a plane of the triangle. Whether a view point is located between a first near clipping plane and a far clipping plane is determined. A second near clipping plane is set according to the determination result, and a view field is set between the second near clipping plane and the far clipping plane. A near clipping procedure is executed on the triangle according to the second near clipping plane. In the 3D graphics clipping method, a correct view field is determined in advance so that a graphics processing procedure is efficiently sped up and the accuracy of the near clipping procedure is increased. | 11-22-2012 |
20120287132 | METHOD FOR RECONSTRUCTING GEOMETRY MAPPING - A method for reconstructing geometry mapping of a rasterized area is provided. The method includes: finding a testing pixel within the rasterized area; finding an occluding point corresponding to the testing pixel in a geometry shadow map of the rasterized area; determining weight values of the occluding point according to the (x, y) coordinate values of the testing pixel and vertices of a triangle occluding the testing pixel in the rasterized area; determining depth value of the occluding point according to the weight value and z coordinate of the vertices of the occluding triangle; and comparing the depth value of the occluding point with the depth value of the testing pixel so as to determine whether the testing pixel is drawn in light or in shadow. | 11-15-2012 |
20120272004 | EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS - A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache. | 10-25-2012 |
20120272003 | EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS - A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request. | 10-25-2012 |
20120268458 | CACHE LINE ALLOCATION METHOD AND SYSTEM - A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is less than or equal to a threshold; and locking a second number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is large than the threshold; wherein the first number is greater than the second number. | 10-25-2012 |
20120267155 | CIRCUIT SUBSTRATE - A circuit substrate includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block. | 10-25-2012 |
20120260075 | CONDITIONAL ALU INSTRUCTION PRE-SHIFT-GENERATED CARRY FLAG PROPAGATION BETWEEN MICROINSTRUCTIONS IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR - A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags. | 10-11-2012 |
20120260074 | EFFICIENT CONDITIONAL ALU INSTRUCTION IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR - A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition. | 10-11-2012 |
20120260073 | EMULATION OF EXECUTION MODE BANKED REGISTERS - A microprocessor includes processor modes comprising a user mode and a plurality of exception modes. An execution unit performs arithmetic operations on operands specified by program instructions. A first set of storage elements holds a first subset of the operands and provides them to the execution unit coupled thereto. A second set of storage elements associated with each of the modes hold a second subset of the operands and are incapable of directly providing the second operand subset to the execution unit. To enter a new mode from a current mode, logic saves the first operand subset held in the first set of storage elements to the second set of storage elements associated with the current mode and restores to the first set of storage elements the second operand subset held in the second set of storage elements associated with the new mode. | 10-11-2012 |
20120260071 | CONDITIONAL ALU INSTRUCTION CONDITION SATISFACTION PROPAGATION BETWEEN MICROINSTRUCTIONS IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR - An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register. | 10-11-2012 |
20120260068 | APPARATUS AND METHOD FOR HANDLING OF MODIFIED IMMEDIATE CONSTANT DURING INSTRUCTION TRANSLATION - An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant. | 10-11-2012 |
20120260067 | MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE - A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator. | 10-11-2012 |
20120260066 | HETEROGENEOUS ISA MICROPROCESSOR THAT PRESERVES NON-ISA-SPECIFIC CONFIGURATION STATE WHEN RESET TO DIFFERENT ISA - A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA. | 10-11-2012 |
20120260065 | MULTI-CORE MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE - A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core. | 10-11-2012 |
20120260064 | HETEROGENEOUS ISA MICROPROCESSOR WITH SHARED HARDWARE ISA REGISTERS - A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state. | 10-11-2012 |
20120260042 | LOAD MULTIPLE AND STORE MULTIPLE INSTRUCTIONS IN A MICROPROCESSOR THAT EMULATES BANKED REGISTERS - A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage. | 10-11-2012 |
20120250859 | DATA ENCRYPTION METHOD AND SYSTEM AND DATA DECRYPTION METHOD - An embodiment of the invention provides a data encryption method for an electrical device. The method comprises: generating an identification code corresponding to the electrical device; generating a temporary key according to the identification code; encrypting first data to generate a first secret key according to the temporary key and a first encryption mechanism; and encrypting the first secret key by a second encryption mechanism to generate an encrypted key. | 10-04-2012 |
20120243184 | DIFFERENTIAL SIGNAL PAIR TRANSMISSION STRUCTURE, WIRING BOARD AND ELECTRONIC MODULE - A differential signal pair transmission structure adapted to a wiring board and including a first signal path and a second signal path is provided. The first signal path includes a first upper trace, a first lower trace and a first conductive through via. The second signal path includes a second upper trace, a second lower trace and a second conductive through via. A portion of the first signal path and a portion of the second signal path overlaps in the normal projection onto the upper or lower surface of the wiring board. Normal projections of the first and the second signal path projecting onto the upper surface of the wiring board are substantially symmetric with respect to a line which is perpendicular to a segment connecting normal projections of axes of the first and the second through via onto the upper surface and passes through the midpoint of the segment. | 09-27-2012 |
20120242577 | METHOD FOR POSITIONING A CURSOR ON A SCREEN - The invention provides a method for positioning a cursor on a screen. In one embodiment, a system comprises the screen and a keyboard. First, a selected region is initialized to be a whole region of the screen. The selected region is then divided into a plurality of sub-regions, wherein each of the sub-regions respectively corresponds to one of a plurality of predetermined keys of the keyboard. Whether the predetermined keys have been pressed is then detected. When one of the predetermined keys has been pressed, the selected region is then set to be the sub-region corresponding to the pressed predetermined key. The position of the cursor is then moved to a center point of the selected region. The dividing step, the detecting step, the setting step, and the moving step are then repeated until the area of the selected region is less than an area threshold. | 09-27-2012 |
20120239847 | MULTI-CORE MICROPROCESSOR INTERNAL BYPASS BUS - Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals. | 09-20-2012 |
20120234631 | SIMPLE NODE TRANSPORTATION SYSTEM AND CONTROL METHOD THEREOF - A method of a simple node transportation system is disclosed. The transportation system comprises a vehicle travels on a route and a traditional control module of the vehicle. The route comprises a plurality of nodes which the vehicle may stop by. The method comprises the following steps: detecting that at least one user moving into a target area of one of the nodes; detecting a gesture of the user; outputting a corresponding control command to the traditional control module in response to the gesture; and displaying the corresponding control command. | 09-20-2012 |
20120233445 | Multi-Thread Processors and Methods for Instruction Execution and Synchronization Therein and Computer Program Products Thereof - Methods for instruction execution and synchronization in a multi-thread processor are provided, wherein in the multi-thread processor, multiple threads are running and each of the threads can simultaneously execute a same instruction sequence. A source code or an object code is received and then compiled to generate the instruction sequence. Instructions for all of function calls within the instruction sequence are sorted according to a calling order. Each thread is provided a counter value pointing to one of the instructions in the instruction sequence. A main counter value is determined according to the counter values of the threads such that all of the threads simultaneously execute an instruction of the instruction sequence that the main counter value points to. | 09-13-2012 |
20120226925 | METHOD FOR SWITCHING OPERATING SYSTEM AND ELECTRONIC APPARATUS USING THE SAME - A method for switching an operating system (OS) and an electronic apparatus are provided. While switching to a first OS, a system firmware stored in a memory unit declares that a first segment of a system memory is in a usable state and a second segment of the system memory is in a reserved state by using a first resource description table, so that the first OS is in a working state in the first segment and a second OS is in a power-saving state in the second segment. While switching to the second OS, the system firmware declares that the second segment is in the usable state and the first segment is in the reserved state by using a second resource description table, so that the second OS is in the working state and the first OS is in the power-saving state. | 09-06-2012 |
20120217999 | Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter - A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential output terminal and a negative differential output terminal and a transition accelerator. A differential output signal is provided by the positive and negative differential output terminals. When the differential output signal transits from low to high, the transition accelerator couples the positive differential output terminal to a high voltage source and couples the negative differential output terminal to a low voltage source. When the differential output signal transits from high to low, the transition accelerator couples the positive differential output terminal to the low voltage source and couples the positive output terminal to the high voltage source. | 08-30-2012 |
20120210146 | ADAPTIVE USB CHARGING METHOD AND SYSTEM - An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode. | 08-16-2012 |
20120198176 | PREFETCHING OF NEXT PHYSICALLY SEQUENTIAL CACHE LINE AFTER CACHE LINE THAT INCLUDES LOADED PAGE TABLE ENTRY - A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line. | 08-02-2012 |
20120191961 | Computer System and Operating System Switching Method Thereof - An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state. | 07-26-2012 |
20120185681 | TRACER CONFIGURATION AND ENABLEMENT BY RESET MICROCODE - A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor. | 07-19-2012 |
20120173893 | Processing Device and Operation System Utilizing the Same - A processing device coupled to a host device via a connection device and including a connection port, a control unit and a switching unit is disclosed. The connection port connects to the connection device. The control unit controls a switching signal according to the kind of the connection device when the connection port is coupled between the connection port and the host device. The switching unit transmits an external power to the control unit according to the switching signal. When the switching unit transmits the external power to the control unit, the control unit operates according to the external power provided by an external device. When the switching unit does not transmit the external power to the control unit, the control unit operates according to a host power provided by the host device. | 07-05-2012 |
20120173597 | LEADING SIGN DIGIT PREDICTOR FOR FLOATING POINT NEAR SUBTRACTOR - An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend. | 07-05-2012 |
20120169395 | LEVEL SHIFTER - A level shifter, converting an input signal into an output signal for level shifting, including a leakage blocking circuit having cascaded P-channel transistors and one N-channel transistor. The P-channel transistor at a beginning stage provides a gate for receiving the input signal and a source coupled to a gate of the P-channel transistor at a secondary stage. At intermediate stages, each P-channel transistor provides a source coupled to a gate of the subsequently cascaded P-channel transistor. At a final stage, the P-channel transistor provides a source coupled to a voltage source and a drain coupled to an output terminal of the leakage blocking circuit for the outputting of the output signal. The N-channel transistor has a gate which is coupled to receive the input signal as well, a source coupled to a common voltage, and a drain coupled to the output terminal of the leakage blocking circuit. | 07-05-2012 |
20120166845 | POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR - A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications. | 06-28-2012 |
20120166837 | DECENTRALIZED POWER MANAGEMENT DISTRIBUTED AMONG MULTIPLE PROCESSOR CORES - A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic. | 06-28-2012 |
20120166832 | DISTRIBUTED MANAGEMENT OF A SHARED POWER SOURCE TO A MULTI-CORE MICROPROCESSOR - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores. | 06-28-2012 |
20120166764 | DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR - Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire. | 06-28-2012 |