SUN MICROSYSTEMS, INC. Patent applications |
Patent application number | Title | Published |
20120230695 | WAVELENGTH-DIVISION MULTIPLEXING FOR USE IN MULTI-CHIP SYSTEMS - Embodiments of a system that includes an array of chip modules (CMs) is described. In this system, a given CM in the array includes a semiconductor die that is configured to communicate data signals with one or more adjacent CMs through electromagnetic proximity communication using proximity connectors. Note that the proximity connectors are proximate to a surface of the semiconductor die. Moreover, the given CM is configured to communicate optical signals with other CMs through an optical signal path using optical communication, and the optical signals are encoded using wavelength-division multiplexing (WDM). | 09-13-2012 |
20120229941 | SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE - A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap. | 09-13-2012 |
20120144073 | METHOD AND APPARATUS FOR TRANSFERRING DIGITAL CONTENT - A method for transferring digital content, involving defining a first region of space associated with a first device and a second region of space associated with a second device, wherein the first device includes digital content to be transferred to the second device, performing a first action within the first region, obtaining the digital content to be transferred from the first device in response to performing the first action to obtain captured digital content, performing a second action within the second region, and transferring the captured digital content to the second device in response to performing the second action. | 06-07-2012 |
20110281395 | SELF-ASSEMBLY OF MICRO-STRUCTURES - Embodiments of a method for assembling a multi-chip module (MCM) are described. During this method, a fluid that includes coupling elements is applied to a surface of a base plate in the MCM. Then, at least some of the coupling elements are positioned into negative features on the surface of the base plate using fluidic assembly. Note that a given coupling element selects a given negative feature using chemical-based selection and/or geometry-based selection. Next, the fluid and excess coupling elements (which reside in regions outside of the negative features on the surface) are removed. | 11-17-2011 |
20110258415 | APPARATUS AND METHOD FOR HANDLING DEPENDENCY CONDITIONS - Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency. Embodiments including a compiler that inserts instructions in a generated instruction stream to eliminate dependency conditions are also contemplated. | 10-20-2011 |
20110191787 | SYSTEM AND METHOD FOR PROVIDING SENSOR DATA FROM EMBEDDED DEVICE TO SOFTWARE DEVELOPMENT ENVIRONMENT - A system and method for providing device data for use in developing application software for a microprocessor-based embedded device having at least one physical sensor using a software development environment include an agent executing on the target embedded device and a connectivity module executing within the software development environment to communicate sensor data from the embedded device to the software development environment. In one embodiment, the target device is a mobile phone that provides sensor data from an integrated physical sensor to a development computer executing mobile phone software within the development environment using the same API's within the development environment as used on the embedded device. | 08-04-2011 |
20110191518 | VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions. | 08-04-2011 |
20110191508 | Low-Contention Update Buffer Queuing For Large Systems - A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue. | 08-04-2011 |
20110191506 | VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is stored in at least one buffer, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions, by speculatively moving the packets forward even while DMA engines perform their processing to facilitate their transfer. | 08-04-2011 |
20110191393 | MARKING ALGORITHM FOR LOW-BANDWITH MEMORY - A method for garbage collection, involving identifying a first object referenced by a second object, determining whether the address of the first object is lower than a pointer position, in response to determining that the address of the first object is lower than the pointer position, adding an identifier for the first object to a mark stack, determining whether a number of identifiers in the mark stack has reached a flush threshold, in response to determining that the number of identifiers in the mark stack has reached the flush threshold, setting a set of marks included in a mark bitmap to grey, setting a region field of a rescan map to indicate that a region of the mark bitmap includes any of the set of marks, and performing a rescan of the region based on the region field. | 08-04-2011 |
20110185347 | METHOD AND SYSTEM FOR EXECUTION PROFILING USING LOOP COUNT VARIANCE - A method for executing a computer program involving obtaining a statement of the source code, where the statement comprises a method call, and where the source code is composed in a statically-typed programming language. The method also involves, upon entry into a loop included in the computer program: incrementing an entry counter by one; and, for each iteration of the loop, incrementing an iteration counter by one, incrementing a local counter by one to obtain an incremented value of the local counter, incrementing a summation variable by the incremented value of the local counter, and executing the iteration of the loop. | 07-28-2011 |
20110185344 | CHARACTERIZING ARTIFICIALITY IN OBJECT CODE - One embodiment of the present invention provides a system that characterizes content in object code. During operation, the system receives the source code of a program. The system also receives one or more pieces of object code of the program, or creates one or more pieces of object code from the source code. Next, the system identifies a construct in the object code. The system then determines whether the construct is physically present in the source code. If the construct is not physically present, the system determines whether the construct is logically present in the source code, wherein a construct is logically present if it is required by the programming language. If so, the system sets a construct flag to indicate that the construct is “synthesized.” However, if not, the system sets the construct flag to indicate that the construct is “synthetic.” Finally, the construct flag is made available to a reflective API. | 07-28-2011 |
20110185195 | ENERGY EFFICIENT MANAGEMENT OF DATALINKS - A system including a first physical network interface card (NIC) include a number of rings, where at least one of the rings is an active ring. The system further includes a host, operatively connected to the first NIC, and including Media Access Control (MAC) layer. The MAC layer is configured to obtain a power management policy, obtain a load associated with the active ring, determine, using the power management policy and the load, that the state associated with at least one of the rings must be changed, and change, in response to the determining, the state of at least one of the of rings. | 07-28-2011 |
20110185150 | Low-Overhead Misalignment and Reformatting Support for SIMD - Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization of the data set and loading the bit mask into an application specific register (ASR). Subsequently, the data may be reorganized inline according to the ASR as the data is loaded into the SIMD functional unit such that the SIMD functional unit may operate on the data set. The results of the SIMD operation may be written to a results register. | 07-28-2011 |
20110185144 | Low-Contention Update Buffer Queuing for Small Systems - A method for queuing update buffers to enhance garbage collection. The method includes running an application thread and providing, for the application thread, a data structure including current and finished update buffer slots. The method includes providing an update buffer for the application thread and storing a pointer to the update buffer in the current update buffer slot. The method includes storing null in the finished update buffer slot and, with the application thread, writing to the update buffer. The thread may write a pointer to the filled update buffer in the finished update buffer slot after the buffer is filled. The method includes using a garbage collector thread to inspect the finished update buffer slot and claim filled buffers and change the pointer to null. The thread then obtains an empty update buffer and updates the current update buffer slot to point to the new buffer. | 07-28-2011 |
20110185129 | SECONDARY JAVA HEAPS IN SHARED MEMORY - A computing system includes a first virtual machine associated with a memory region readable by the first virtual machine, and a first private memory region. A data object is created by the first virtual machine in the sharable memory region, readable and writeable by the first virtual machine and a second virtual machine. A mapping is established between the first virtual machine and a particular area of the shareable memory region. The computing system includes the second virtual machine associated with a second private memory region, and a reference to the particular area of the shareable memory region. The mapping enables both the first virtual machine and second virtual machine to read and write second data in the shareable memory region without creating a copy of the second data in the first and second private memory regions. | 07-28-2011 |
20110184996 | METHOD AND SYSTEM FOR SHADOW MIGRATION - A method for migrating files involves receiving, from a client, a file system (FS) operation request for a target FS, making a first determination that migration for a source FS is not complete, making a second determination that the FS operation request specifies a directory and that a directory level attribute for the directory on the target FS specifies that the directory is un-migrated. In response to the first and second determination, creating, using the meta-data for content in the directory, a directory entry for a file in the directory on the target FS, where the directory entry for the file is associated with a file level attribute that specifies the file is un-migrated, and servicing, after the creating, the first FS operation request using target FS. | 07-28-2011 |
20110184907 | METHOD AND SYSTEM FOR GUARANTEED TRAVERSAL DURING SHADOW MIGRATION - A method for migrating files including receiving, from a client, a file system (FS) operation request for a target FS, making a first determination that migration for a source FS is not complete, making a second determination that the FS operation request specifies a directory and that a directory level attribute for the directory on the target FS specifies that the directory is un-migrated. In response to the first and second determination, creating, using the meta-data for content in the directory, a directory entry for a file in the directory on the target FS, where the directory entry for the file is associated with a file level attribute that specifies the file is un-migrated, adding an unique identification (UID) for the file to a pending list, adding the UID for the directory to a removed list, and servicing, after the creating, the first FS operation request using target FS. | 07-28-2011 |
20110179424 | METHOD AND SYSTEM FOR SELF-TUNING OF HARDWARE RESOURCES - A system for self-tuning hardware resources includes a processor, a hardware resource, an operating system (OS), a metric monitoring unit (MMU), and a configuration engine (CE). The OS determines: the hardware resource; a metric for monitoring the hardware resource; a hardware resource management policy for the hardware resource; and a primary and secondary sub-ranges for the metric. The OS sends a hardware resource management policy directive to the CE. The MMU monitors the hardware resource to obtain data for the metric. The CE receives the hardware resource management policy directive, determines the primary and secondary sub-ranges from the hardware resource management policy directive, obtains data for the metric from the MMU. When data is outside the primary sub-range and inside the secondary sub-range, the CE determines and executes a hardware resource optimization routine to bring hardware resource utilization into compliance with the primary sub-range. | 07-21-2011 |
20110179402 | METHOD AND SYSTEM FOR COMPILING A DYNAMICALLY-TYPED METHOD INVOCATION IN A STATICALLY-TYPED PROGRAMMING LANGUAGE - A method for compiling source code, involving: obtaining a statement of the source code comprising a method call, where the source code is composed in a statically-typed programming language; determining whether the method call is a dynamic method call; upon determining that the method call is a dynamic method call, compiling a dynamic method invocation without performing type checking on the method call; upon determining that the method call is not a dynamic method call: performing type checking on the method call, selecting a target method to invoke, and compiling a static method invocation to invoke the target method. | 07-21-2011 |
20110179400 | System and method for overflow detection USING PARTIAL EVALUATIONS - A method for overflow detection using partial evaluations. The method includes obtaining a section of code from a source code file stored on a storage device, analyzing the section of code to identify a buffer with an index, determining a plurality of statements that are statically-computable and dependent on the index of the buffer, and generating a code segment including the plurality of statements. The method further includes replacing an access statement of the plurality of statements with a conditional statement returning true when bounds of the buffer are exceeded, where the access statement uses the index to access the buffer, adding an unconditional statement returning false to the code segment, and executing the code segment on a computer processor to obtain a determination of whether the bounds of the buffer are exceeded. | 07-21-2011 |
20110179258 | PRECISE DATA RETURN HANDLING IN SPECULATIVE PROCESSORS - The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode. | 07-21-2011 |
20110179254 | LIMITING SPECULATIVE INSTRUCTION FETCHING IN A PROCESSOR - The described embodiments relate to a processor that speculatively executes instructions. During operation, the processor often executes instructions in a speculative-execution mode. Upon detecting an impending pipe-clearing event while executing instructions in the speculative-execution mode, the processor stalls an instruction fetch unit to prevent the instruction fetch unit from fetching instructions. In some embodiments, the processor stalls the instruction fetch unit until a condition that originally caused the processor to operate in the speculative-execution mode is resolved. In alternative embodiments, the processor maintains the stall of the instruction fetch unit until the pipe-clearing event has been completed (i.e., has been handled in the processor). | 07-21-2011 |
20110179231 | SYSTEM AND METHOD FOR CONTROLLING ACCESS TO SHARED STORAGE DEVICE - A system and method for controlling access to a shared storage device in a computing cluster having at least two nodes configured as cluster members provide fencing and quorum features without using the device controller hardware/firmware so fencing can be provided with storage devices that do not support disk reservation operations, such as with non-SCSI compliant disks. A polling thread on each node periodically reads a designated storage space on the shared storage device at a polling interval to determine if its corresponding node registration key is present, and halts the node if the key has been removed. A cluster membership agent removes a corresponding node registration key from the designated storage space of the shared storage device and publishes new membership information indicating that the corresponding node has departed the cluster only after delaying for a time period greater than the polling interval. | 07-21-2011 |
20110179230 | METHOD OF READ-SET AND WRITE-SET MANAGEMENT BY DISTINGUISHING BETWEEN SHARED AND NON-SHARED MEMORY REGIONS - A method of read-set and write-set management distinguishes between shared and non-shared memory regions. A shared memory region, used by a transactional memory application, which may be shared by one or more concurrent transactions is identified. A non-shared memory region, used by the transactional memory application, which is not shared by the one or more concurrent transactions is identified. A subset of a read-set and a write-set that access the shared memory region is checked for conflicts with the one or more concurrent transactions at a first granularity. A subset of the read-set and the write-set that access the non-shared memory region is checked for conflicts with the one or more concurrent transactions at a second granularity. The first granularity is finer than the second granularity. | 07-21-2011 |
20110179208 | TIME DIVISION MULTIPLEXING BASED ARBITRATION FOR SHARED OPTICAL LINKS - A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel. | 07-21-2011 |
20110178997 | METHOD AND SYSTEM FOR ATTRIBUTE ENCAPSULATED DATA RESOLUTION AND TRANSCODING - A computer readable medium having software instructions that, when executed, perform a method for preserving data stored in a file system with a plurality of files. The method involves determining whether storage capacity of the file system has reached a threshold level, wherein the threshold level is stored in at least one of a plurality of size-reducing policies, obtaining a criterion from the at least one size-reducing policy, identifying a subset of the plurality of files that match the criterion, accessing metadata of each of the identified subset of files, wherein the metadata of each of the identified subset of files comprises at least one option for reducing a size of the file, and performing a size-reducing action to reduce a size of each of the identified subset of files based on the option for reducing the size of each of the identified subset of files and the criterion. | 07-21-2011 |
20110176675 | Method and system for protecting keys - A method of protecting a media key including obtaining the media key, obtaining an auxiliary key, calculating a split key using the media key and the auxiliary key, encrypting the split key using a wrap key to generate an encrypted split key, assembling the encrypted split key and a communication key to obtain a data bundle, and sending the data bundle to a token, where the media key is extracted from the data bundle on the token to protect data on a storage device. | 07-21-2011 |
20110173467 | SYSTEM AND METHOD FOR CONTROLLING ENERGY USAGE IN A SERVER - A system for controlling energy usage in a server having a processor, where the system includes a memory for storing energy cost information, and a controller for determining a transaction rate for the processor. The controller is also for determining a cumulative of energy expended by the server based on the determined transaction rate for each of a number of available power level states (P-states) for operation of the processor, and for selecting one of the available P-states for operation of the processor based on the determined cumulative energy expended and the stored energy cost information. | 07-14-2011 |
20110173426 | METHOD AND SYSTEM FOR PROVIDING INFORMATION TO A SUBSEQUENT OPERATING SYSTEM - A method for transferring execution to a subsequent operating system. The method includes rebooting a computer system. Rebooting the computer system includes initializing an in-kernel boot loader. The in-kernel boot loader executes in a kernel of an initial operating system. Rebooting the computer system further includes populating, by the in-kernel boot loader, an initialization data structure using system data gathered during the execution of the initial operating system, loading, by the in-kernel boot loader, the subsequent operating system, and transferring control of the computer system from the initial operating system to the subsequent operating system. The subsequent operating system accesses the initialization data structure to identify available hardware. The method further includes executing the subsequent operating system on the available hardware of the computer system. | 07-14-2011 |
20110170819 | ELECTRO-OPTIC MODULATOR WITH INVERSE TAPERED WAVEGUIDES - An integrated circuit that includes an optical waveguide to convey an optical signal via an optical mode in an on-chip optical waveguide is described. In this integrated circuit, a cross-sectional area of the optical waveguide may be tapered in proximity to an electro-optic modulator in the integrated circuit, such as a germanium electro-optic modulator or a quantum-well (QW) electro-optic modulator. In particular, the cross-sectional area may be tapered from a first diameter distal from the electro-optic modulator to a second diameter proximate to the electro-optic modulator. This so-called ‘inverse taper’ may increase the spatial extent or size of the optical mode, thereby allowing the optical signal to be optically coupled to or from the electro-optic modulator with low optical loss. | 07-14-2011 |
20110169522 | FAULT-TOLERANT MULTI-CHIP MODULE - A multi-chip module (MCM) is described. This MCM includes multiple sites, where a given site in the multiple sites includes multiple chips with proximity connectors that communicate information through proximity communication within the MCM via multiple components associated with the given site. Note that the MCM includes global redundancy and local redundancy at the given site. In particular, the global redundancy involves providing one or more redundant sites in the multiple sites. Furthermore, the local redundancy involves providing one or more redundant chips in the multiple chips and one or more redundant components in the multiple components. | 07-14-2011 |
20110167297 | CLOCK-DATA-RECOVERY TECHNIQUE FOR HIGH-SPEED LINKS - A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample. | 07-07-2011 |
20110164384 | TANDEM FAN ASSEMBLY WITH AIRFLOW-STRAIGHTENING HEAT EXCHANGER - A tandem fan system with an airflow-straightening heat exchanger removes heat from an airflow while providing optimal airflow pressure. The tandem fan system includes a first fan assembly and a second fan assembly, wherein each fan assembly has an inlet face and an outlet face, and includes at least one fan configured to propel a flow of air from the inlet face to the outlet face. The tandem fan system also includes a heat exchanger coupled between the first and second fan assemblies, wherein the heat exchanger includes at least one fin array and one or more heat pipes. The fin array and heat pipe combination is configured to draw heat from a flow of air that flows through the heat exchanger, and to straighten the flow of air so that the flow is perpendicular to the inlet face of the second fan assembly. | 07-07-2011 |
20110161294 | METHOD FOR DETERMINING WHETHER TO DYNAMICALLY REPLICATE DATA - The disclosed embodiments provide a system that determines whether to dynamically replicate data segments on a node in a computing cluster that stores a collection of data segments. During operation, the system identifies a data segment from the collection that is predicted to be frequently accessed by future tasks executing in the cluster. The system then determines a slowdown that would result for the current workload of the node if the data segment were to be replicated to the node. The system also determines a predicted future benefit that would be associated with replicating the data segment to the node. If the predicted slowdown is less than the predicted future benefit, the replication system replicates the data segment to the node. | 06-30-2011 |
20110158088 | Self-Configuring Networking Devices For Providing Services in a Network - A method for use in a datacenter for load balancing services. A native registry is operated to provide a naming service storing service access information for services active in a network. On a node, an instance of a service is provided, and the native registry is updated with access information for the service. The method includes providing a content switch with a node controller such as on a network device. The method includes obtaining, with the node controller, service configuration information for the service from the native registry that includes the service access information. The node controller activates the service on the network by configuring the content switch based on the obtained service configuration information. The method includes the service node publishing a service definition for the service that includes the service access information and other information such as a service name, an IP address, and a load balancing algorithm. | 06-30-2011 |
20110154308 | REDUNDANT RUN-TIME TYPE INFORMATION REMOVAL - Redundant run-time type information is removed from a compiled program. The redundant type information may be unneeded and/or duplicate. Unneeded type information is removed by selecting instances of type information from read only data sections of object files. The entire compiled program is searched for instructions that use the instances. The instances that do not correspond to such instructions are removed from the object files. Duplicate type information is removed by selecting instances of type information from read only data sections of object files. The read only data sections of the other object files in the compiled program are then searched for the selected instances. The selected instances that exist in the read only data sections of the other object files are removed. Redundant type information may be removed from individual object files before concatenation into a single binary file and/or from a single binary file after concatenation. | 06-23-2011 |
20110154122 | SYSTEM AND METHOD FOR OVERFLOW DETECTION USING SYMBOLIC ANALYSIS - A method for demand-driven symbolic analysis involves obtaining a section of code comprising an instruction from a source code file and determining a critical variable in the section of code and data dependencies related to the critical variable. The method further involves iteratively computing a symbolic value representing a range of values of the critical variable according to the data dependencies, determining a set of control predicates relevant to the critical variable at the instruction, refining the range of values according to the set of control predicates to generate a second range of values for the symbolic value, and reporting an error when the second range of values exceeds a predetermined value. | 06-23-2011 |
20110153928 | MEMORY UTILIZATION TRACKING - A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register for storing an access count, a low threshold register for storing a low threshold, and a high threshold register for storing a high threshold. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action. | 06-23-2011 |
20110153797 | SYSTEM AND METHOD FOR PERFORMING DISTRIBUTED TRANSACTIONS USING GLOBAL EPOCHS - A method for performing distributed transactions of a cluster. The method includes, in response to a lock request including a first epoch from a first node, setting a local epoch to a maximum of the first epoch and the local epoch, sending a first lock including the local epoch to the first node, and in response to a conflicting lock request including a second epoch from a second node, setting the local epoch to a maximum of the second epoch and the local epoch, where the conflicting lock request is delayed until after the first lock is released. The method further includes, in response to a reintegration request including a third epoch from the first node, setting the local epoch to a maximum of the third epoch and the local epoch and performing a reintegration based on the reintegration request, where the reintegration is logged using the local epoch. | 06-23-2011 |
20110150200 | WEB GUIDED COLLABORATIVE AUDIO - A system for conducting a conference call based on a community document. The system includes a data network, a first conference client device and a second conference client device communicatively coupled to the data network, wherein the first conference client device is associated with a first user of the conference call and the second conference client device is associated with a second user of the conference call, and a conference server device communicatively coupled to the data network. | 06-23-2011 |
20110150159 | CLOCK-FORWARDING TECHNIQUE FOR HIGH-SPEED LINKS - A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link. | 06-23-2011 |
20110150077 | QUANTIZATION PARAMETER PREDICTION - A method for encoding a video frame. The method including obtaining a current frame from a video stream, where the video stream includes a number of frames, determining a first base QP value for the current frame, and sending the first base QP value for the current frame to a decoder. The method also includes obtaining a first macroblock from the current frame, where the first macroblock includes a first image on the current frame, determining a first actual quantization parameter (QP) value for the first macroblock, and determining a first reference block for the first macroblock. The method also includes determining a first predicted QP value for the first macroblock using the first reference block, calculating a first ΔQP value for the first macroblock, and sending the first ΔQP value, a first prediction mode, and a first reference vector to the decoder. | 06-23-2011 |
20110150060 | Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer in Mission Mode - Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1's and 0's) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link. | 06-23-2011 |
20110149539 | BASE PLATE FOR USE IN A MULTI-CHIP MODULE - A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips. | 06-23-2011 |
20110147915 | COMBINED POWER MESH TRANSITION AND SIGNAL OVERPASS/UNDERPASS - A zipper structure includes a first contiguous full-dense-mesh (FDM) array of a first supply in top metal and a second contiguous FDM array of a second supply in top-1 metal, a third contiguous FDM array of the second supply in top metal and a fourth contiguous FDM array of the first supply in top-1 metal, and a signal line, such that portions of the first contiguous FDM array and the second contiguous FDM array overlap and portions of the third contiguous FDM array and the fourth contiguous FDM array overlap. The Zipper structure facilitates connecting the first contiguous FDM array to the fourth contiguous FDM array by VIAs and a first connector lines and the second contiguous FDM array to the third contiguous FDM array by VIAs and a second connector lines, such that portion of the signal line overlaps with the first connector lines and the second connector lines. | 06-23-2011 |
20110147907 | ACTIVE PLASTIC BRIDGE CHIPS - A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor material. A plurality of base chips are assembled to the package assembly. The package assembly positions and aligns the plurality of base chips such that the bridge circuits bridge the base chips and enable proximity communication between the base chips. | 06-23-2011 |
20110145834 | CODE EXECUTION UTILIZING SINGLE OR MULTIPLE THREADS - A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread. | 06-16-2011 |
20110145815 | VIRTUAL HOT PLUGGING OF DEVICES AND VIRTUAL DEVICES - A device list is created for an operating system and/or a virtualized operating system. A bus node is created for each bus. Interface nodes are created as child nodes of the respective bus and a status indicator indicates whether a device connected to the interface is accessible. A device node is created for the device connected to the interface. Virtualized interface nodes are created as child nodes of the device node for each virtual device included in the device and a status indicator indicates whether the respective virtual device is accessible. Then, devices and/or virtual devices may be added and/or removed utilizing the list. After a device and/or virtualized device has been removed for one operating system and/or virtualized operating system, it may then be added to another. In this way, devices and/or virtualized devices can be virtually hot plugged without physically connecting and/or disconnecting devices. | 06-16-2011 |
20110145543 | EXECUTION OF VARIABLE WIDTH VECTOR PROCESSING INSTRUCTIONS - A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code. | 06-16-2011 |
20110141868 | DATA STORAGE SYSTEM AND METHOD FOR CALIBRATING SAME - Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage. Methods and systems of tape technology disclose optical tape media including: configurations, formulations, markings, and structure; optical tape manufacturing methods, systems, and apparatus methods and systems including: curing processes, coating methods, embossing, drums, testing, tracking alignment stamper strip; optical tape methods and systems including: pick up head adapted for the disclosed optical tape; and optical tape uses including optical storage media devices for multimedia applications | 06-16-2011 |
20110141863 | DATA STORAGE SYSTEM AND METHOD FOR CALIBRATING SAME - Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage. Methods and systems of tape technology disclose optical tape media including: configurations, formulations, markings, and structure; optical tape manufacturing methods, systems, and apparatus methods and systems including: curing processes, coating methods, embossing, drums, testing, tracking alignment stamper strip; optical tape methods and systems including: pick up head adapted for the disclosed optical tape; and optical tape uses including optical storage media devices for multimedia applications | 06-16-2011 |
20110141630 | SUPERCAPACITOR LEAK DETECTION AND MANAGEMENT - Some embodiments of the present invention provide a system that facilitates the operation of a supercapacitor. During operation, the system measures an electrical parameter of the supercapacitor using a set of conductor rings surrounding a capacitor seal of the supercapacitor. Next, the system determines the presence of a leak in the supercapacitor based on the electrical parameter. Finally, the system manages the operation of the supercapacitor based on the presence of the leak. | 06-16-2011 |
20110138372 | REGISTER PRESPILL PHASE IN A COMPILER - The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions. | 06-09-2011 |
20110138149 | PREVENTING DUPLICATE ENTRIES IN A NON-BLOCKING TLB STRUCTURE THAT SUPPORTS MULTIPLE PAGE SIZES - One embodiment provides a system that prevents duplicate entries in a non-blocking TLB that supports multiple page sizes and speculative execution. During operation, after a request for translation of a virtual address misses in the non-blocking TLB, the system receives a TLB fill. Next, the system determines a page size associated with the TLB fill, and uses this page size to determine a set of bits in the virtual address that identify the virtual page associated with the TLB fill. The system then compares this set of bits with the corresponding bits of other virtual addresses associated with pending translation requests. If the system detects that a second virtual address for another pending translation request is also satisfied by the TLB fill, the system invalidates the duplicate translation request associated with the second virtual address. | 06-09-2011 |
20110135320 | TECHNIQUE FOR CALIBRATING AND CENTERING AN OPTICAL RECEIVER - A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver. | 06-09-2011 |
20110135315 | OPTICAL RECEIVER WITH A CALIBRATION MODE - An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit. | 06-09-2011 |
20110134915 | APPARATUS AND METHOD FOR MANAGING PACKET CLASSIFICATION TABLES - Methods and apparatus are provided for managing classification of packets within a multi-function input/output device, and for allowing the device's classification tables to be cleared in a non-blocking manner. The input/output device conveys multiple communication connections corresponding to multiple physical and/or virtual PCIe (Peripheral Component Interconnect Express) functions bound to software images executing on hosts. The device comprises gate logic configured to indicate statuses of the functions or the DMA engines bound to the functions. When the gate logic indicates a particular destination function is valid, the packet is transferred normally after being classified. A portion of the logic corresponding to a given function is reprogrammed to indicate the function is invalid when that function is reinitialized (e.g., FLR or Function Level Reset). The function's entries in packet classification tables are cleared afterward. When the logic indicates a function is invalid, packets destined for that function are dropped. | 06-09-2011 |
20110119528 | HARDWARE TRANSACTIONAL MEMORY ACCELERATION THROUGH MULTIPLE FAILURE RECOVERY - The described embodiments provide a processor (e.g., processor | 05-19-2011 |
20110119318 | ZERO-COPY MATURING OF LARGE OBJECTS IN GENERATIONAL HEAP WITH COPYING COLLECTION - A method for performing garbage collection promotion, comprising determining that an age of a large young object is greater than a predetermined tenuring threshold, wherein the predetermined tenuring threshold specifies an age beyond which objects are promoted, setting a plurality of types of a plurality of large memory regions from young to old to promote the large young object to a large old object, wherein the plurality of large memory regions host the large young object, scavenging references of the large old object, wherein the large old object is a large promoted object, scanning a large young object list to identify a plurality of unvisited large young objects, wherein a plurality of visited bits of the plurality of unvisited large young objects are unset, and releasing a plurality of unvisited large memory regions, wherein the unvisited large memory regions host the plurality of unvisited large young objects. | 05-19-2011 |
20110109356 | APERTURE GENERATING CIRCUIT FOR A MULTIPLYING DELAY-LOCKED LOOP - A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal. | 05-12-2011 |
20110107292 | Extraction of Component Models from PCB Channel Scattering Parameter Data by Stochastic Optimization - Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data. | 05-05-2011 |
20110107289 | METHOD OF IMPLEMENTING PHYSICALLY REALIZABLE AND POWER-EFFICIENT CLOCK GATING IN MICROPROCESSOR CIRCUITS - A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions. | 05-05-2011 |
20110107187 | High Density Tape Drive Multi-Channel Low Density Parity Check Coding Control - An LDPC coding system includes a number of LDPC encoders and a number of LDPC decoders. The number of encoders/decoders is between one and one fewer than the total number of tracks on the high density tape are provided. The LDPC encoders are operable to break data from an incoming data sector into the data blocks to be written to the high density tape. The LDPC decoders are operable to assemble the data blocks into data sectors. | 05-05-2011 |
20110107050 | ADAPTIVE TRIGGERING OF GARBAGE COLLECTION - Methods and apparatus are provided for adaptively triggering garbage collection. During relatively steady or decreasing rates of allocation of free memory, a threshold for triggering garbage collection is dynamically and adaptively determined on the basis of memory drops (i.e., decreases in free memory) during garbage collection. If a significant increase in the rate of allocation of memory is observed (e.g., two consecutive measurements that exceed a mean rate plus two standard deviations), the threshold is modified based on a memory drop previously observed in conjunction with the current memory allocation rate, or a memory drop estimated to be possible for the current allocation rate. | 05-05-2011 |
20110107023 | Automatically Linking Partitions on a Tape Media Device - A system and method for automatically linking partitions on storage media for use within a storage management system is provided to minimize wasted space on the storage media, the time and expense traditionally spent reclaiming partitions containing invalid data, and the computer processing capability required to write data to and read data from the storage media. The storage management system includes a partitioned storage tape, a host application running on a server, and an archive device. The host application is operative to track location information for each host file or data object written to the storage tape. Using the location information, the host application is able to identify one or more “free” or writable partitions that are created on the storage tape as host files expire. Moreover, when writing host files to the storage tape, the archive device is operative to automatically link the writable partitions to form logical volumes such that when reading host files from the storage tape, the archive device can automatically navigate through the logical volumes. | 05-05-2011 |
20110106981 | CONFIGURATION SPACE COMPACTION - The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region. | 05-05-2011 |
20110106748 | TECHNIQUE FOR FAST POWER ESTIMATION USING PROBABILISTIC ANALYSIS OF COMBINATIONAL LOGIC - A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates. | 05-05-2011 |
20110103397 | TWO-PHASE ARBITRATION MECHANISM FOR A SHARED OPTICAL LINKS - A method for arbitration in an arbitration domain. The method includes: receiving, by each node of a plurality of nodes in the arbitration domain, an arbitration request from each sending node of the plurality of nodes in the arbitration domain, where the plurality of nodes in the arbitration domain each use a shared data channel to send data to a set of receiving nodes; assigning, by each node in the arbitration domain, consecutive time slots to each sending node based on a plurality of priorities assigned to the plurality of nodes in the arbitration domain; for each time slot: sending, from the arbitration domain, a switch request to a receiving node designated by the sending node, where the receiving node is in the set of receiving nodes; and sending, by the sending node, data to the receiving node via the shared data channel during the time slot. | 05-05-2011 |
20110102190 | FACILITATING POWER SUPPLY UNIT MANAGEMENT USING TELEMETRY DATA ANALYSIS - Some embodiments provide a system that analyzes telemetry data from a computer system. During operation, the system obtains the telemetry data as a set of telemetric signals from the computer system and validates the telemetric signals using a nonlinear, nonparametric regression technique. Next, the system assesses the integrity of a power supply unit (PSU) in the computer system by comparing the telemetric signals to one or more reference telemetric signals associated with the computer system. If the assessed integrity falls below a threshold, the system performs a remedial action for the computer system. | 05-05-2011 |
20110101833 | Ratcheting Rack-Mount Kit Reinforcement Mechanism for Storage Rack - A storage rack for supporting a server chassis in a storage cabinet. The storage rack includes front and rear vertical support members and one or more rack mount kits for slidably supporting one or more computing devices (e.g., servers). Each rack mount kit may include a pair of rail assemblies, each rail assembly including outer, middle and inner rail assemblies. The outer rail assembly may include first and second outer rail members that are slidable relative to each other and one or more locking mechanisms that may be operable to selectively limit sliding or translation of the first and second outer rail members relative to each other. In one arrangement, a locking mechanism may include a ratchet assembly that may allow the first and second outer rail members to slide in a first direction when the locking mechanism is engaged and in the first direction and an opposite second direction when the locking mechanism is released. | 05-05-2011 |
20110099535 | Encoding Switch on Ordered Universes with Binary Decision Diagrams - Various embodiments herein include one or more of systems, methods, software, and/or data structures to implement a multi-way branch statement in a computer programming language. The multi-way branch statement may include a plurality of case labels each having a non-primitive data type (e.g., strings) and being associated with a block of code to be executed dependent upon a control variable that also has a non-primitive data type. The implementation may include encoding the case labels for the multi-way branch statement as a binary decision diagram (BDD), such as a zero-suppressed binary decision diagram (ZDD), wherein the control variable for the multi-way branch statement may be compared with the case labels by stepping through the BDD. The BDD may include identifiers that provide information regarding which of the case labels is matched by the control variable, such that an appropriate code block may be executed. | 04-28-2011 |
20110099200 | DATA SHARING AND RECOVERY WITHIN A NETWORK OF UNTRUSTED STORAGE DEVICES USING DATA OBJECT FINGERPRINTING - A data sharing method using fingerprinted data objects for sharing data among untrusted network devices. Each peer device is adapted for storing a plurality of data objects, and a fingerprint generator is used to generate a fingerprint for each stored data object available for sharing or for recovery. The fingerprints are stored in a local data store, and a data manager running on one of the computer devices retrieves from another of the computer devices a copy of one of its data objects through the use of the associated fingerprints. The fingerprints include a hash value output from a strong hashing algorithm. The retrieving includes transmitting query messages with the fingerprints of the needed data objects to the networked, peer devices and then verifying the integrity of received data objects by generating a fingerprint of the received data objects that can be compared with the ones provided in the queries. | 04-28-2011 |
20110099175 | PLUPERFECT HASHING - Various embodiments herein include one or more of systems, methods, software, and/or data structures to implement a “pluperfect” hash function. Generally, a pluperfect hash function is a hash function that maps distinct elements in a set S to distinct hash values H with no collisions (i.e., perfect hash function) and also includes an additional constraint that the hash function does not map other elements outside the set S into the set of distinct hash values H. In some example embodiments, pluperfect hash functions are used to implement a multi-way branch statement in a computer programming language. The implementation may include generating hash values for each of the case labels of the branch statement according to a pluperfect hash function. | 04-28-2011 |
20110099154 | Data Deduplication Method Using File System Constructs - A data deduplication method providing direct look up and storage in an instance repository (IR). The method includes receiving a data object and processing the data object to generate a fingerprint that includes a location component, which defines a file location within the IR such as by first using a hash function to create a hash for the data object and parsing the hash value into sub-strings defining sub-directories of the IR. The method includes determining whether the data object is a duplicate by verifying the presence of a file in the IR at the file location. Determining if the data is unique involves performing a system call on the IR providing the location component as the file path. The method includes, when a file is not in the IR, updating the IR to store the data object as a file at the file location defined by the location component. | 04-28-2011 |
20110093731 | METHOD AND APPARATUS TO MAXIMIZE POWER OF A COMPUTER SYSTEM FOR EFFECTIVE TESTING - Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system. | 04-21-2011 |
20110093721 | PARAMETERIZABLE CRYPTOGRAPHY - Some embodiments provide systems and techniques for performing parameterizable cryptography. An encryption key can be determined based at least on a string associated with an authorization policy. The encryption key can then be used to encrypt information. The decryption key can also be determined based at least on the string associated with the authorization policy. Note that the authorization policy must be satisfied to decrypt information. In some embodiments, the systems and techniques for performing parameterizable cryptography are blindable. These blindable embodiments can be used to preserve privacy. | 04-21-2011 |
20110093646 | PROCESSOR-BUS ATTACHED FLASH MAIN-MEMORY MODULE - A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the address to a cache line in a cache memory associated with a remote processor, and sending a coherency message from the module to the remote processor to change a state of the cache line in the cache memory. The method further includes receiving, at the module, the cache line from the remote processor, sending, using processor bus and in response to the read request, the cache line to the requesting processor, identifying a requested page stored within the flash memory based on the address, storing a copy of the requested page in the memory buffer, and writing the cache line to the copy of the requested page. | 04-21-2011 |
20110093251 | VIRTUALIZING COMPLEX NETWORK TOPOLOGIES - In general, the invention relates to a creating a network model on a host. The invention includes: gathering first component properties associated with a first physical network device on a target network; creating a first container using first component properties; determining that a second physical network device is operatively connected to the first physical network device via a physical network link; gathering second component properties associated with the physical network link; creating a first VNIC associated with the first container; determining that at least one virtual network device is executing on the second physical network device; gathering third component properties associated with the at least one virtual network device; creating a second container, wherein the second container is configured using the third component properties; and creating a second VNIC associated with the second container. | 04-21-2011 |
20110091157 | THREE-DIMENSIONAL MACRO-CHIP INCLUDING OPTICAL INTERCONNECTS - A multi-chip module (MCM), which includes a three-dimensional (3D) stack of chips that are coupled using optical interconnects, is described. In this MCM, disposed on a first surface of a middle chip in the 3D stack, there are: a first optical coupler, an optical waveguide, which is coupled to the first optical coupler, and a second optical coupler, which is coupled to the optical waveguide. The first optical coupler redirects an optical signal from the optical waveguide to a first direction (which is not in the plane of the first surface), or from the first direction to the optical waveguide. Moreover, the second optical coupler redirects the optical signal from the optical waveguide to a second direction (which is not in the plane of the first surface), or from the second direction to the optical waveguide. Note that an optical path associated with the second direction passes through an opening in a substrate in the middle chip. | 04-21-2011 |
20110091035 | HARDWARE KASUMI CYPHER WITH HYBRID SOFTWARE INTERFACE - A system including a memory; a software interface, operatively connected to the memory, and configured to generate a modified version of a confidentially key (CKey), and a modified version of an integrity key (IKey); and a Kasumi engine having a hardware implementation of a Kasumi cipher and configured to load the modified version of the CKey from the memory to perform a confidentiality function, and to load the modified version of the IKey from memory to perform an integrity function. | 04-21-2011 |
20110090915 | METHOD AND SYSTEM FOR INTRA-HOST COMMUNICATION - A system including first and second virtualized execution environments and a hypervisor for sending packets between virtualized execution environments. The first virtualized execution environment includes a first VNIC associated with a first hardware address (HA), a first proxy VNIC associated with a second HA, and a virtual switch. A Vswitch table for the virtual switch includes entries associating the first HA with the first VNIC and the second HA with the first proxy VNIC. The second virtualized execution environment includes a second proxy VNIC associated with the first HA. The virtual switch receives a first packet associated with the second HA. The virtual switch sends the first packet to the first proxy VNIC when Vswitch table entry associates the second HA with the first proxy VNIC. The first VNIC proxy sends the first packet from the first virtualized execution environment to the second virtualized execution environment using the hypervisor. | 04-21-2011 |
20110090910 | ENHANCED VIRTUAL SWITCH - A system and method for providing network connectivity to a host, involving creating a virtual switch on the host, specifying at least one data link attribute of the virtual switch, creating a plurality of virtual network interface cards (VNICs) on the host, associating each of the plurality of VNICs with the virtual switch, and assigning the at least one data link attribute of the virtual switch to each of the plurality of VNICs, where the virtual switch is connected to a physical network interface card (NIC) associated with the host, where each of the plurality of VNICs is associated with a different one of a plurality of execution environments, where the plurality of execution environments is located on the host, and where the plurality of VNICs is located on the host. | 04-21-2011 |
20110090225 | SYSTEM AND METHOD FOR APPLYING LEVEL OF DETAIL SCHEMES - A method for level of detail in a 3D environment application involves establishing a tiered system for processing a graphical object at a distance from a perspective point. The tiered system comprises a first level and a second level, the first level for processing the graphical object at a first range from the perspective point, and the second level for processing the graphical object at a second range from the perspective point. The method also involves determining the distance of the graphical object from the perspective point, assigning, while rendering the graphical object and based on the distance, the graphical object to a corresponding level of the tiered system, and executing a virtual processor assigned to the graphical object. The virtual processor executes every frame when the graphical object is assigned to the first level, less than every frame when assigned to the second level, and displaying the graphical object. | 04-21-2011 |
20110089540 | SEMICONDUCTOR DIE WITH INTEGRATED ELECTRO-STATIC DISCHARGE DEVICE - A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap. | 04-21-2011 |
20110082965 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 04-07-2011 |
20110078110 | FILESYSTEM REPLICATION USING A MINIMAL FILESYSTEM METADATA CHANGELOG - In general, the invention relates to replicating a source file system stored on a first memory by obtaining a first unread entry from a changelog associated with the source file system, querying the source file system using the first unread entry to obtain a current first object file status, a current first object file path, a current first parent directory status, and a current first parent directory path, determining, based on the querying, whether a first object file on the source file system has changed at some time after the execution of the first unread entry, if the first object file has not changed, performing a first action on a target file system, and if the first object file has changed, performing a second action on the target file system. | 03-31-2011 |
20110075380 | SELF-LOCKING FEATURES IN A MULTI-CHIP MODULE - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released. | 03-31-2011 |
20110074011 | MECHANICAL COUPLING IN A MULTI-CHIP MODULE USING MAGNETIC COMPONENTS - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates. | 03-31-2011 |
20110072326 | SRAM MACRO TEST FLOP - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit. | 03-24-2011 |
20110069973 | EDGE-COUPLED OPTICAL PROXIMITY COMMUNICATION - An optical module is described. This optical module includes at least two optical devices that communicate with each other using edge-to-edge optical coupling of an optical signal between optical components in the two optical devices. Note that the edge-to-edge optical coupling may occur without mode converters at edges of either of the optical devices. Furthermore, the edge-to-edge optical coupling may be facilitated by an alignment substrate, which is mechanically coupled to the two optical devices. This alignment substrate aligns the edges of the two optical devices so that they are approximately parallel to each other, and aligns the optical components in the two optical devices. | 03-24-2011 |
20110069925 | MACRO-CHIP INCLUDING A SURFACE-NORMAL DEVICE - A multi-chip module (MCM) is described. This MCM includes two substrates having facing surfaces. Disposed on a surface of a first of these substrates, there is an optical waveguide, having an eigenmode in the plane of the surface, and an optical coupler, which redirects optical signals to and/or from the optical waveguide and a direction normal to the surface. Furthermore, disposed on a surface of a second of the substrates, which faces the surface of the first substrate, and which overlaps the optical coupler, there is an optoelectronic device. This optoelectronic device, which has an eigenmode in a direction perpendicular to the surface of the second substrate, selectively receives or provides the optical signal to and/or from the optical coupler. For example, the selective receiving or providing may be controlled by selectively applying a potential to the quantum-well device, thereby changing the optical properties of the optoelectronic device. | 03-24-2011 |
20110068827 | PASSIVE CAPACITIVELY INJECTED PHASE INTERPOLATOR - A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal. | 03-24-2011 |
20110068479 | ASSEMBLY OF MULTI-CHIP MODULES USING SACRIFICIAL FEATURES - A multi-chip module (MCM) is described. This MCM includes two substrates, having facing surfaces, which are mechanically coupled. Disposed on a surface of a first of these substrates, there is a negative feature, which is recessed below this surface. A positive feature in the MCM, which includes an assembly material other than a bulk material in the substrates, at least in part mates with the negative feature. For example, the positive feature may be disposed on the surface of the other substrate. Alternatively, prior to assembly of the MCM, the positive feature may be a separate component from the substrates (such as a micro-sphere). Note that the assembly material has a bulk modulus that is less than a bulk modulus of the material in the substrates. Furthermore, at least a portion of the positive feature may have been sacrificed when the mechanical coupling was established. | 03-24-2011 |
20110067107 | INTEGRATED INTRUSION DEFLECTION, DETECTION AND INTROSPECTION - Methods and apparatus are provided for integrated deflection, detection and intrusion. Within a single computer system configured for operating system virtualization (e.g., Solaris, OpenSolaris), multiple security functions execute in logically independent zones or containers, under the control and administration of a global zone. Such functions may illustratively include a demilitarized zone (DMZ) and a honeypot. Management is facilitated because all functions work within a single operating system, which promotes the ability to configure, monitor and control each function. Any given zone can be configured with limited resources, a virtual network interface circuit and/or other features. | 03-17-2011 |
20110061233 | RIB REINFORCEMENT OF PLATED THRU-HOLES - Systems and methods for providing mechanically reinforced plated through-holes (PTH) in PCBs, which advantageously allow improved soldering capabilities and reliability, are described herein. Such systems and methods are achieved by reducing the heat sinking effects of PTHs by providing one or more vias surrounding the PTHs to provide an electrical connection between the PTH and the internal and bottom conductive layers of a PCB. In this regard, the PTHs are spaced apart from at least one of the internal conductive layers (e.g., ground or power layers), so the heat sinking effects are reduced. This feature enables molten solder to substantially fill the entire PTH before freezing, thereby improving the mechanical and electrical connection between an electrical component and the PCB. One or more electrically-nonfunctional lands (or “rib reinforcements”) are provided in internal conductive layers to mechanically support the walls of the PCB. These rib reinforcements improve the mechanical strength of the PTHs without affecting the electrical performance and without impacting the ability to solder components to the PCB. | 03-17-2011 |
20110060821 | SYSTEM AND METHOD FOR DETERMINING AFFINITY GROUPS AND CO-LOCATING THE AFFINITY GROUPS IN A DISTRIBUTING NETWORK - In at least one embodiment, an apparatus for determining one or more affinity groups in a distributed network is provided. A first distributed computing device is operably coupled to a plurality of clients for enabling electronic interactive activities therebetween. The first distributed computing device is configured to detect at least one network interaction among the plurality of clients. The first distributed computing device is further configured to generate at least one weighted value based on the number of detected network interactions. The first distributed computing device is further configured to establish an affinity group comprising at least one client from the plurality of clients based on the at least one weighted value. | 03-10-2011 |
20110055758 | SMART NAVIGATOR FOR PRODUCTIVITY SOFTWARE - A productivity software application in which a user chooses actions, from at least one of a menu bar, a tool bar, or a task pane, runs on a computer. While running the productivity software application, the computer monitors actions chosen by the user. Data is generated that represents a navigation menu. The navigation menu includes a limited set of choices based on previous actions chosen by the user in the productivity software application. The computer outputs the data representing the navigation menu for visual display, and receives input indicative of a user choice from the limited set of choices in the navigation menu. | 03-03-2011 |
20110055346 | DIRECT MEMORY ACCESS BUFFER MANAGEMENT - Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls. | 03-03-2011 |
20110054705 | SYSTEM AND METHOD FOR CONTROLLING COMPUTER SYSTEM FAN SPEED - Computer system fans having fixed operating states corresponding to discreet operating speeds may be controlled by collecting temperature information upstream or downstream of the fans and commanding the fans to switch between the fixed operating states based on the temperature information at a frequency sufficient to controllably achieve speeds between the discreet operating speeds. | 03-03-2011 |
20110051357 | SYSTEM FOR MINIMIZING MECHANICAL AND ACOUSTICAL FAN NOISE COUPLING - A system and method of spread-spectrum fan control for an air-cooled system is provided for reducing the vibrational and acoustical noise associated with the air-cooled system. The method includes generating a first control signal that controls a blade-passing frequency of a first cooling fan and a second control signal that controls a blade-passing frequency of a second cooling fan, wherein the first and second control signals may be pulse width modulated (“PWM”) signals. One or more noise generators independently vary duty cycles for the first and second PWM signals within a range around respective first and second blade-passing frequency set points. As a result, the blade-passing frequencies for the first and second cooling fans are independently and randomly modulated within a range around the respective first and second blade-passing frequency set points. | 03-03-2011 |
20110047346 | EFFICIENT INTERLEAVING BETWEEN A NON-POWER-OF-TWO NUMBER OF ENTITIES - Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log | 02-24-2011 |
20110043260 | INTEGRATED PULSE-CONTROL AND ENABLE LATCH CIRCUIT - The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit. | 02-24-2011 |
20110040548 | PHYSICS-BASED MOSFET MODEL FOR VARIATIONAL MODELING - A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form. | 02-17-2011 |
20110035561 | STORE QUEUE WITH TOKEN TO FACILITATE EFFICIENT THREAD SYNCHRONIZATION - Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue. | 02-10-2011 |
20110029843 | CYCLE SLIP DETECTION AND CORRECTION - A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip. | 02-03-2011 |
20110026225 | Method and Apparatus for Liquid Cooling Computer Equipment - A cooling system for cooling computer component with a liquid provided at atmospheric pressure, or low pressure, that flows through channel defined in the computer component. The liquid is pumped from a reservoir to a discharge port, or weir, that is located above the computer component. The liquid flows through an in-feed manifold to diverters that direct the liquid into in-feed tanks located above a row of the computer component. The liquid flows through the channels and flow control orifices to a drain that returns the liquid to the reservoir. | 02-03-2011 |
20110018120 | HIGH-BANDWIDTH RAMP-STACK CHIP PACKAGE - A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost. | 01-27-2011 |
20110010696 | DUPLICATE VIRTUAL FUNCTION TABLE REMOVAL - One or more embodiments of the present invention relate to a method for duplicate virtual function table removal. The method includes identifying, using a processor of a computer, a first virtual function table formed when a first source code is compiled into a first object code. The method further includes using the processor, identifying a second virtual function table formed when a second source code is compiled into a second object code. The method further includes, independent of linking the first object code to a first executable binary code and the second object code to a second executable binary code, identifying, using the processor, that the first virtual function table and the second virtual function table are identical and, using the processor, deleting the second virtual function table. | 01-13-2011 |
20110010478 | SYSTEM AND METHOD FOR DEVICE RESOURCE ALLOCATION AND RE-BALANCE - In at least one embodiment, an apparatus for providing resources from a plurality of on-board device nodes to a hot-plugged device node in a computer is provided. The apparatus comprises a resource manager configured to receive a resource request over a bus system indicative of a set of desired resources from the hot-plugged device node. The resource manager is further configured to probe a parent device and at least one upper level device node positioned above the parent device node for the set of desired resources. The resource manager is further configured to provide the set of desired resources from the parent device node and one or more nodes of the at least one upper level device node over the bus system for transmission to the hot-plugged device node to enable the hot-plugged device node to operate in the intended manner. | 01-13-2011 |
20110004882 | Method and system for scheduling a thread in a multiprocessor system - A method for scheduling a thread on a plurality of processors that includes obtaining a first state of a first processor in the plurality of processors and a second state of a second processor in the plurality of processors, wherein the thread is last executed on the first processor, and wherein the first state of the first processor includes the state of a cache of the first processor, obtaining a first estimated instruction rate to execute the thread on the first processor using an estimated instruction rate function and the first state, obtaining a first estimated global throughput for executing the thread on the first processor using the first estimated instruction rate and the second state, obtaining a second estimated global throughput for executing the thread on the second processor using the second state, comparing the first estimated global throughput with the second estimated global throughput to obtain a comparison result, and executing the thread, based on the comparison result, on one selected from a group consisting of the first processor and the second processor, wherein the thread performs an operation on one of the plurality of processors. | 01-06-2011 |
20100333189 | METHOD AND SYSTEM FOR ENFORCING SECURITY POLICIES ON NETWORK TRAFFIC - A computer readable medium that includes computer readable program code embodied therein. The computer readable medium causes the computer system to receive, by a data link rule enforcer, a packet from a packet source of the packets, and obtain a data link rule applying to a data link. The data link is operatively connected to the packet source, and the data link is associated with a media access control (MAC) address. The computer readable medium further causes the computer system to determine, by the data link rule enforcer, whether the packet complies with the data link rule, and drop, by the data link rule enforcer, the packet when the packet fails to comply with the data link rule. | 12-30-2010 |
20100333113 | METHOD AND SYSTEM FOR HEURISTICS-BASED TASK SCHEDULING - A computer readable storage medium including executable instructions for heuristics-based task scheduling. Instructions include receiving a first event notification associated with a first event, where the first event is determined from the first event notification. Instructions further include determining whether a predicate for an action is satisfied by the first event, where the action predicate, the action, and an action parameter are associated with a task object in a task pool. Instructions further include obtaining the action parameter when the action predicate is satisfied by the first event, where a priority is assigned using a heuristics policy to the task object based on the action parameter. Instructions further include inserting the task object into a task queue using the assigned priority. The action associated with the task object is performed by an execution thread. The performance of the action is a second event associated with a second event notification. | 12-30-2010 |
20100333108 | PARALLELIZING LOOPS WITH READ-AFTER-WRITE DEPENDENCIES - Some embodiments provide a system that increases parallelization in a computer program. During operation, the system obtains a binary associative operator and a ordered set of elements associated with a prefix operation in the computer program. Next, the system divides the elements into multiple sets of contiguous iterations based on a number of processors used to execute the computer program. The system then performs, in parallel on the processors, a set of local reductions on the contiguous iterations using the binary associative operator. Afterwards, the system calculates a set of boundary prefixes between the contiguous iterations using the local reductions. Finally, the system applies, in parallel on the processors, the boundary prefixes to the contiguous iterations using the binary associative operator to obtain a set of prefixes for the prefix operation. | 12-30-2010 |
20100333097 | METHOD AND SYSTEM FOR MANAGING A TASK - A computer readable storage medium including executable instructions for managing a task. Instructions include receiving a request. Instructions further include determining a task corresponding with the request using a request-to-task mapping. Instructions include obtaining a task entry corresponding with the task from a task store, where the task entry associates the task with an action and a predicate for performing the action. Instructions further include creating a task object in a task pool using the task entry. Instructions further include receiving an event notification at the task engine, where the event notification is associated with an event. Instructions further include determining whether the predicate for performing the action is satisfied by the event. Instructions further placing the task object in a task queue when the predicate for performing the action is satisfied by the event. | 12-30-2010 |
20100333093 | FACILITATING TRANSACTIONAL EXECUTION THROUGH FEEDBACK ABOUT MISSPECULATION - One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program. | 12-30-2010 |
20100333091 | HIGH PERFORMANCE IMPLEMENTATION OF THE OPENMP TASKING FEATURE - A method and system for creating and executing tasks within a multithreaded application composed according to the OpenMP application programming interface (API). The method includes generating threads within a parallel region of the application, and setting a counter equal to the quantity of the threads. The method also includes, for each one of the plurality of threads, assigning an implicit task, and executing the implicit task. Further, the method includes, upon encountering a task construct, during execution of the implicit tack, for an explicit asynchronous task generating the explicit asynchronous task, adding the explicit asynchronous task to a first task queue, where the first task queue corresponds to the one of the plurality of threads; and incrementing the counter by one. | 12-30-2010 |
20100333090 | METHOD AND APPARATUS FOR PROTECTING TRANSLATED CODE IN A VIRTUAL MACHINE - One embodiment provides a system that protects translated guest program code in a virtual machine that supports self-modifying program code. While executing a guest program in the virtual machine, the system uses a guest shadow page table associated with the guest program and the virtual machine to map a virtual memory page for the guest program to a physical memory page on the host computing device. The system then uses a dynamic compiler to translate guest program code in the virtual memory page into translated guest program code (e.g., native program instructions for the computing device). During compilation, the dynamic compiler stores in a compiler shadow page table and the guest shadow page table information that tracks whether the guest program code in the virtual memory page has been translated. The compiler subsequently uses the information stored in the guest shadow page table to detect attempts to modify the contents of the virtual memory page. Upon detecting such an attempt, the system invalidates the translated guest program code associated with the virtual memory page. | 12-30-2010 |
20100333011 | TOUCH SCREEN INPUT RECOGNITION AND CHARACTER SELECTION - A system and method of character input using a virtual keyboard, which may have a reduced number of keys. The virtual keyboard may be displayed on a touch screen and may include a plurality of keys. The virtual keyboard may have a plurality of keys, each key having a number of characters or symbols. Characters associated with a particular key may be selected through a series of related touch screen inputs. | 12-30-2010 |
20100332945 | FACILITATING PROBABILISTIC ERROR DETECTION AND CORRECTION AFTER A MEMORY COMPONENT FAILURE - Some embodiments of the present invention provide a system that provides error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X12-30-2010 | |
20100332944 | FACILITATING ERROR DETECTION AND CORRECTION AFTER A MEMORY COMPONENT FAILURE - Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C-2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed. If the failed memory component contains a data-bit column for the block of data, the system uses checkbits from the two checkbit columns to correct the data-bit column, and then stores the corrected data-bit column. Next, the system generates and stores new checkbits in a functioning memory component, wherein the new checkbits provide single-error-correction and double-error-detection for erroneous bits in the block of data, but do not provide for detection and correction of a failed memory component. | 12-30-2010 |
20100332901 | ADVICE-BASED FEEDBACK FOR TRANSACTIONAL EXECUTION - One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a failure state of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides an advice state associated with the recorded failure state to the program to facilitate a response to the transaction failure by the program. | 12-30-2010 |
20100332883 | METHOD AND SYSTEM FOR EVENT-BASED MANAGEMENT OF RESOURCES - A system for dispatching a thread to a resource obtains a thread and utilization data for all resources. The system determines if there is a thread-resource affinity. The system uses thread-resource affinity to identify a resource and a timestamp for when the thread last completed executing on the resource. The system determines if the resource qualifies under a dispatch policy. The system uses utilization data to determine a timestamp for when the resource last transitioned to a not powered state. When the second timestamp precedes the first timestamp, the system dispatches the thread to the resource and generates a power management event. The system determines if the power management event satisfies a throttle policy. The system discards the power management event when throttle policy is unsatisfied and determines whether to adjust the current power state of the resource based on the power management event when throttle policy is satisfied. | 12-30-2010 |
20100332775 | HYBRID INTERLEAVING IN MEMORY MODULES - A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module. | 12-30-2010 |
20100332766 | SUPPORTING EFFICIENT SPIN-LOCKS AND OTHER TYPES OF SYNCHRONIZATION IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM - Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations. | 12-30-2010 |
20100332765 | HIERARCHICAL BLOOM FILTERS FOR FACILITATING CONCURRENCY CONTROL - Some embodiments provide a system that facilitates concurrency control in a computer system. During operation, the system generates a set of signatures associated with memory accesses in the computer system. To generate the signatures, the system creates a set of hierarchical Bloom filters (HBFs) corresponding to the signatures, and populates the HBFs using addresses associated with the memory accesses. Next, the system compares the HBFs to detect a potential conflict associated with the memory accesses. Finally, the system manages concurrent execution in the computer system based on the detected potential conflict. | 12-30-2010 |
20100332698 | EFFICIENT BUFFER MANAGEMENT IN A MULTI-THREADED NETWORK INTERFACE - Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed. | 12-30-2010 |
20100332622 | Distributed Resource and Service Management System and Method for Managing Distributed Resources and Services - A distributed resource and service management system includes at least one node and a registry service. The at least one node is configured to execute at least one node controller. The registry service is configured to provide at least one service description via a control interface, and to offer logical resources to the at least one node controller. The at least one node controller is configured to discover the registry service, to initiate on-going communications with the registry service, and to execute at least one of queries, updates and inserts to the registry service to maintain service levels. | 12-30-2010 |
20100332446 | STORAGE POOL SCRUBBING WITH CONCURRENT SNAPSHOTS - A method for scrubbing a storage pool. The method includes loading a scrub queue with a number of identifiers corresponding to a number of datasets, selecting a first identifier from the scrub queue, where the first identifier corresponds to a first dataset, initiating a scrubbing of the first dataset. The method further includes, upon receiving an indication of a requirement to pause the scrubbing, pausing the scrubbing of the first dataset, creating a bookmark recording a last location within the first dataset that was scrubbed before pausing the scrubbing of the first dataset, detecting at least one change to a storage pool, and performing a modification in response to detecting the at least one change to the storage pool. | 12-30-2010 |
20100332199 | NOISE REDUCTION TECHNIQUE FOR MONITORING ELECTROMAGNETIC SIGNALS - One embodiment provides a system that analyzes a target electromagnetic signal radiating from a monitored system. During operation, the system monitors the target electromagnetic signal using a set of antennas to obtain a set of received target electromagnetic signals from the monitored system. Next, the system calculates a weighted mean of the received target electromagnetic signals using a first pattern-recognition model. The system then subtracts the received target electromagnetic signals from the weighted mean of the received target electromagnetic signals to obtain a set of noise-reduced signals for the monitored system. Finally, the system assesses the integrity of the monitored system by analyzing the noise-reduced signals using a second pattern-recognition model. | 12-30-2010 |
20100332189 | EMBEDDED MICROCONTROLLERS CLASSIFYING SIGNATURES OF COMPONENTS FOR PREDICTIVE MAINTENANCE IN COMPUTER SERVERS - Some embodiments of the present invention provide a system that analyzes data from a computer system. During operation, the system obtains the sensor data from a component in the computer system using a set of sensors. Next, the system transmits the sensor data to a microcontroller unit (MCU) coupled to the sensors and stores the sensor data in internal memory of the MCU. Finally, the system assesses the integrity of the component by analyzing the sensor data using a pattern-recognition apparatus in the MCU. | 12-30-2010 |
20100332185 | ANALYTICAL BANDWIDTH ENHANCEMENT FOR MONITORING TELEMETRIC SIGNALS - Some embodiments provide a system that analyzes telemetry data from a monitored system. During operation, the system obtains the telemetry data as a set of telemetric signals from the monitored system and groups the telemetry data into one or more clusters of correlated telemetric signals from the telemetric signals. Next, the system increases a bandwidth associated with monitoring the telemetric signals. To increase the bandwidth, the system omits one or more of the correlated telemetric signals from each of the clusters during sampling of the telemetric signals and estimates the omitted correlated telemetric signals by applying a nonlinear, nonparametric regression technique to the sampled telemetric signals. | 12-30-2010 |
20100329685 | OPTICAL DEVICE WITH REDUCED THERMAL TUNING ENERGY - An optical device that includes multiple optical modulators having actual operating wavelengths at a given temperature is described. Because of differences between the actual operating wavelengths and target operating wavelengths of the optical modulators, heating elements may be used to thermally tune the optical modulators so that the actual operating wavelengths match corresponding carrier wavelengths in a set of optical signals. Furthermore, control logic in the optical device may assign the optical modulators to the corresponding carrier wavelengths based at least on differences between the carrier wavelengths and the actual operating wavelengths, thereby reducing an average thermal tuning energy associated with the heating elements. | 12-30-2010 |
20100329607 | OPTICAL CONNECTOR WITH REDUCED MECHANICAL-ALIGNMENT SENSITIVITY - An optical connector is described. This optical connector spatially segregates optical coupling between an optical fiber and an optical component, which relaxes the associated mechanical-alignment requirements. In particular, the optical connector includes an optical spreader component disposed on a substrate. This optical spreader component is optically coupled to the optical fiber at a first coupling region, and is configured to optically couple to the optical component at a second coupling region that is at a different location on the substrate than the first coupling region. Moreover, the first coupling region and the second coupling region are optically coupled by an optical waveguide. | 12-30-2010 |
20100329460 | METHOD AND APPARATUS FOR ASSURING ENHANCED SECURITY - Some embodiments provide a system to assure enhanced security, e.g., by assuring that information is not revealed over a covert channel. All communications between a source system and a destination system may pass through an intermediate system. In some embodiments, the intermediate system may perform an additional level of blinding to ensure that the source system does not covertly reveal information to the destination system. In some embodiments, the intermediate system may request the source system to perform a modification operation, and then check if the source system performed the modification operation. Examples of the modification operation include a blinding operation and a cryptographic hashing operation. | 12-30-2010 |
20100329450 | INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS - Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor. | 12-30-2010 |
20100329390 | ADAPTIVE OFFSET-COMPENSATING DECISION-FEEDBACK RECEIVER - A circuit that receives input signals from a transmitter via proximity communication, such as capacitively coupled proximity communication, is described. Because proximity communication may block DC content, the circuit may restore the DC content of input signals. In particular, a refresh circuit in the circuit may short inputs of the circuit to each other at least once per clock cycle (which sets a null value). Furthermore, a feedback circuit ensures that, if there is a signal transition in the input signals during a current clock cycle, it is passed through to an output node of the circuit. On the other hand, if there is no signal transition in the input signals during the current clock cycle, the feedback circuit may select the appropriate output value on the output node based on the output value during the immediately preceding clock cycle. | 12-30-2010 |
20100329332 | METHOD AND SYSTEM FOR LINEAR QUANTIZATION AND DEQUANTIZATION - A method including receiving a set of input data in a first matrix format. The method further includes compressing the set of input data to obtain a first set of compressed data in a second matrix format, where compressing the set of input data includes using a quantization equation, the quantization equation including Yq(i,j)=[(Y(i,j)+offset)<12-30-2010 | |
20100329259 | UPPER LAYER BASED DYNAMIC HARDWARE TRANSMIT DESCRIPTOR RECLAIMING - In general, the invention relates to reclaiming transmit descriptors by configuring a media access control (MAC) to execute a first MAC layer thread to reclaim a first number of transmit descriptors (TDs) from a first hardware transmit ring (HTR) using a first reclaim algorithm, where the first reclaim algorithm is associated with a first transmission pattern and a first TDR status. The invention further includes receiving, by a virtual NIC (VNIC) executing within the MAC layer, a first number of packets, forwarding the first number of packets to a device driver on the host associated with the physical NIC, and forwarding the first number of packets from the device driver to the physical NIC using the first number of TDs, where the first plurality of TDs are reclaimed by the first MAC layer thread according to the first reclaim algorithm. | 12-30-2010 |
20100329253 | METHOD AND APPARATUS FOR PACKET CLASSIFICATION AND SPREADING IN A VIRTUALIZED SYSTEM - Some embodiments of the present invention provide a system for packet classification and spreading in a virtualized system. The system can use information in a packet's header to determine a destination system-image in the virtualized system, and a packet-spreading policy for the destination system-image. The system can determine a key using the information in a packet's header. Alternatively, the system can hash the information in the packet's header to obtain an index value. Next, the system can use the key or the index value to perform a lookup in a table which associates keys or index values with system images and/or packet-spreading policies. Once the destination system-image and the packet-spreading policy are determined, the system can deliver the packet to a thread on the destination system-image according to the packet-spreading policy. | 12-30-2010 |
20100329250 | SIMPLE FAIRNESS PROTOCOLS FOR DAISY CHAIN INTERCONNECTS - A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate. | 12-30-2010 |
20100329063 | DYNAMICALLY CONTROLLED VOLTAGE REGULATOR FOR A MEMORY - A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM. | 12-30-2010 |
20100328892 | MOLDED HEAT SINK AND METHOD OF MAKING SAME - A heat sink for use with a heat generating component includes a molded cooling block including a molded cooling passage for receiving a cooling medium. The cooling block is configured to be positioned in sufficient heat transfer relationship with respect to the heat generating component so that the cooling medium receives heat from the heat generating component. | 12-30-2010 |
20100328798 | SYSTEM AND METHOD FOR DETERMINING VIBRATION OF AT LEAST ONE HARD DISK DRIVE - A system for determining vibration of at least one hard disk drive includes one or more computers configured to command a plurality of reads from the at least one hard disk drive such that, for each of the plurality of reads, data stored on the at least one hard disk drive is retrieved directly from the at least one hard disk drive. The one or more computers are also configured to obtain read rate information related to the plurality of reads and to determine a vibration level experienced by the at least one hard disk drive based on the read rate information. | 12-30-2010 |
20100327982 | INVERTING DIFFERENCE OSCILLATOR - The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO. | 12-30-2010 |
20100327937 | CONFIGURABLE PULSE GENERATOR - The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal. | 12-30-2010 |
20100327466 | TECHNIQUE FOR FABRICATING MICROSPRINGS ON NON-PLANAR SURFACES - A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated. | 12-30-2010 |
20100327460 | CAPACTIVE CONNECTORS WITH ENHANCED CAPACITIVE COUPLING - A single-chip module (SCM) and a multi-chip module (MCM) that includes at least two instances of the SCM are described. The SCM includes a pad disposed on a substrate. This pad has a top surface that includes a pattern of features. A given feature in the pattern of features has a height that extends above a minimum thickness of the pad, thereby increasing a capacitance associated with the pad relative to a configuration in which the top surface is planar. Furthermore, pads disposed on the two instances of the SCM in the MCM may each have a corresponding pattern of features that increases the capacitive coupling between the pads relative to a configuration in which the top surfaces of either or both of the pads are planar. Note that the pads may be aligned such that features in the patterns of features on these pads are interdigited with each other. | 12-30-2010 |
20100326193 | System and Method for Characterizing Vibration of a Rack Structure - A system for characterizing vibration of a rack structure having at least one hard disk drive disposed therein and a vibration exciter operatively associated with the rack structure includes one or more computers. The one or more computers are configured to command the vibration exciter to provide vibration input to the rack structure and to command a plurality of reads from the at least one hard disk drive such that, for each of the plurality of reads, data stored on the at least one hard disk drive is retrieved from the at least one hard disk drive. The one or more computers are also configured to obtain read rate information related to the plurality of reads and to identify at least one resonant frequency of the rack structure based on the read rate information. | 12-30-2010 |
20100325630 | PARALLEL NESTED TRANSACTIONS - A system for managing transactions, including a first reference cell associated with a starting value for a first variable, a first thread having an outer atomic transaction including a first instruction to write a first value to the first variable, a second thread, executing in parallel with the first thread, having an inner atomic transaction including a second instruction to write a second value to the first variable, where the inner atomic transaction is nested within the outer atomic transaction, a first value node created by the outer atomic transaction and storing the first value in response to execution of the first instruction, and a second value node created by the inner atomic transaction, storing the second value in response to execution of the second instruction, and having a previous node pointer referencing the first value node. | 12-23-2010 |
20100325619 | FAULT TOLERANT COMPILATION WITH AUTOMATIC OPTIMIZATION ADJUSTMENT - A compilation method is provided for correcting compiler errors that include compiler internal errors and errors produced by running a validation suite. The method includes running a compiler on a computer and storing a set of optimization levels in memory accessible by the compiler. The method includes receiving a source file with the compiler that includes a user-defined optimization level to be used in compiling the source file. The method includes identifying a set of functions within the source file and using compiler components to compile these functions using the original optimization level. When the compiling results in an internal error occurring and being reported for one or more of the functions, the method includes using an optimization adjustment module to process the internal error and assign an adjusted or lower optimization level to the one or more functions and recompiling of these functions again with the lower optimization level. | 12-23-2010 |
20100325618 | FAULT TOLERANT COMPILATION WITH AUTOMATIC ERROR CORRECTION - A compilation method is provided for automated user error correction. The method includes using a compiler driver run by a processor to receive a source file for compilation. With a compiler component invoked by the compiler driver, the method includes identifying an error in the source file such as a linking problem or syntax error in the user's program. The method includes receiving with the compiler driver an error message corresponding to the identified error. With an error corrector module run by the processor, the method includes processing the error message to determine an error correction for the identified error in the source file. The compiler driver modifies the source file based on the error correction and compiles the modified source file with the compiler component. | 12-23-2010 |
20100325600 | ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN - Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements. | 12-23-2010 |
20100325452 | AUTOMATIC CLOCK-GATING INSERTION AND PROPAGATION TECHNIQUE - Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element. | 12-23-2010 |
20100325374 | DYNAMICALLY CONFIGURING MEMORY INTERLEAVING FOR LOCALITY AND PERFORMANCE ISOLATION - Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page. | 12-23-2010 |
20100324882 | ESTIMATING BALL-GRID-ARRAY LONGEVITY IN A COMPUTER SYSTEM - A method for generating a service action for a computer system is described. During the method, a longevity index value for a packaging technology (such as solder joints in a BGA) in the computer system is calculated using thermal and vibration telemetry data (which is collected in the computer system) and a longevity model. This longevity model may be based on accelerated failure testing of the packaging technology, field failures of the packaging technology in a group of computer systems (which includes the computer system) and/or thermal and vibration telemetry data for the group of computer systems. Furthermore, using the longevity index value, the service action for the computer system is determined. Based on the longevity index value, remedial action (such as repairs to the computer system) may be scheduled and performed. | 12-23-2010 |
20100318828 | Method And System For Generating A Power Consumption Model Of At Least One Server - A system for generating a power consumption model of at least one server includes one or more computers configured to obtain n time series telemetry signals indicative of operating parameters of the at least one server, obtain a time series power signal indicative of power consumed by the at least one server, and correlate each of the n time series telemetry signals with the time series power signal. The one or more computers are further configured to select a set of the n time series telemetry signals having an overall correlation with the time series power signal greater than a predetermined threshold, and generate a power consumption model of the at least one server based on at least the set of the n time series telemetry signals. | 12-16-2010 |
20100318610 | METHOD AND SYSTEM FOR A WEAK MEMBERSHIP TIE-BREAK - In general, the invention relates to a method for managing a two-node cluster. The method includes determining, by a first server node, that a second server node is disconnected from the two-node cluster when a first heartbeat response is not received from the second server node and sending a first echo request from the first server node to a first external system, where the first external system is specified on each server node of the two-node cluster. The method further includes receiving a first echo response for the first echo request from the first external system at the first server node and, in response to receiving the first echo response, providing, by the first server node, services of the two-node cluster independent of the second server node. | 12-16-2010 |
20100316065 | METHOD AND APPARATUS FOR MODULATING THE WIDTH OF A HIGH-SPEED LINK - The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes. | 12-16-2010 |
20100315223 | COOLING-CONTROL TECHNIQUE FOR USE IN A COMPUTER SYSTEM - A method for providing control signals to a fan in a computer system is described. During the method, an electronic device receives temperature measurements and a fan-speed measurement performed in the computer system. Using a pattern-recognition model, the electronic device validates the measurements, and excludes any inaccurate measurements, such as those associated with drifting or failed sensors. Next, the electronic device determines control signals for a fan in the computer system using a model of coolant flow in the computer system and/or a slope of a phase-frequency curve of a cross power spectral density function corresponding to a pair of temperature profiles measured, as a function of time, by a pair of thermal sensors. Then, the determined control signals are provided to the fan. | 12-16-2010 |
20100306510 | SINGLE CYCLE DATA MOVEMENT BETWEEN GENERAL PURPOSE AND FLOATING-POINT REGISTERS - Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (RF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution unit, a working register file (WRF), an FRF, and an IRF. To achieve the single cycle movement functionality, the integer execution unit may physically own the WRF, IRF, and FRF, and may monitor and control any dependencies between them. Thus, since the integer execution unit has direct read access to both the IRF and the FRF, data may be moved between the two register files using the single cycle operation of the integer execution unit, without the need to store and load the data from memory. | 12-02-2010 |
20100306358 | HANDLING OF MULTIPLE MAC UNICAST ADDRESSES WITH VIRTUAL MACHINES - A method for managing a guest OS executing on a host. The method includes receiving, from the guest OS associated with a first MAC address, a second MAC address, wherein the first MAC address is associated with a first guest VNIC, wherein the second MAC address is associated with a second guest VNIC; configuring an intermediate VNIC executing on the host OS to forward packets associated with the second MAC address to the guest OS, wherein packets associated with the first MAC address and received by the intermediate VNIC are forwarded to the guest OS; and forwarding the second MAC address from the intermediate VNIC to a device driver associated with a physical NIC, wherein the device driver configures a classifier on the physical NIC to forward packets associated with the second MAC address to a first HRR located on the physical NIC associated with the intermediate VNIC. | 12-02-2010 |
20100306256 | Distributed Database Write Caching With Limited Durability - A distributed database system includes a central data server, and a plurality of application nodes for receiving connections from clients. Each application node is in communication with the central data server, and has a data cache which maintains local copies of recently used data items. The central data server keeps track of which data items are stored in each data cache and makes callback requests to the data caches to request the return of data items that are needed elsewhere. Data items, including modified data items, are cached locally at a local application node so long as the locally cached data items are only being accessed by the local application node. The local application node handles transactions and stores changes to the data items. The local application node forwards changes, in order by transaction, to the central data server to insure consistency, thereby providing limited durability write caching. | 12-02-2010 |
20100306236 | Data Policy Management System and Method for Managing Data - A method for managing data includes identifying nodes of an archiving file system executing on one or more computers that have been updated, acquiring time ordered node state change events within the archiving file system, storing the node state change events, and reading the stored node state change events. The method further includes acquiring current information contained within the nodes that has been updated, updating data contained within a database system executing on the one or more computers to reflect the acquired information, querying the database system, and enforcing data policies upon the archiving file system based on the results of the query. | 12-02-2010 |
20100306165 | RADIO FREQUENCY MICROSCOPE FOR AMPLIFYING AND ANALYZING ELECTROMAGNETIC SIGNALS - One embodiment provides a technique for analyzing a target electromagnetic signal radiating from a monitored system. During the technique, the monitored system is positioned at a first locus of an ellipsoidal surface to amplify the target electromagnetic signal received at a second locus of the ellipsoidal surface. Next, the amplified target electromagnetic signal is monitored using an antenna positioned at the second locus of the ellipsoidal surface. Finally, the integrity of the monitored system is assessed by analyzing the amplified target electromagnetic signal monitored by the antenna. | 12-02-2010 |
20100305892 | NEAR-ISOTROPIC ANTENNA FOR MONITORING ELECTROMAGNETIC SIGNALS - One embodiment provides a system that analyzes a target electromagnetic signal radiating from a monitored system. During operation, the system monitors the target electromagnetic signal using a near-isotropic antenna that includes a set of receiving surfaces arranged in a regular polyhedron. Next, the system obtains a set of received target electromagnetic signals from the receiving surfaces. Finally, the system assesses the integrity of the monitored system by separately analyzing each of the received target electromagnetic signals. | 12-02-2010 |
20100303075 | MANAGING TRAFFIC ON VIRTUALIZED LANES BETWEEN A NETWORK SWITCH AND A VIRTUAL MACHINE - A computer readable medium comprising software instructions for managing resources on a host, wherein the software instructions comprise functionality to: configure a classifier located on a NIC, to forward packets addressed to a first destination address to a first HRR mapped to a first VNIC, wherein packets addressed to the first destination address are associated with a first PFC lane; configure the classifier to forward packets addressed to a second destination address to a second HRR, wherein packets addressed to the second destination address are associated with a second PFC lane; and transmit, by the first VNIC, a pause frame associated with the first PFC lane to a switch operatively connected to the physical NIC, wherein the switch, in response to receiving the pause frame, stores packets associated with the first PFC lane in a buffer without transmitting the packets. | 12-02-2010 |
20100302249 | APPARATUS, SYSTEMS AND METHODS FOR LAYOUT OF SCENE GRAPHS USING NODE BOUNDING AREAS - A value is assigned to a layout bound of a first node in a scene graph. The layout bound constitutes a bounding volume for the object corresponding to the node and may be the display properties of the object and a first set of display modifiers for the node but not a second set. A display layout is calculated for a second node in the scene graph based on the value of the layout bound. Then, nodes of the scene graph are rendered to generate a display on a display device according to the calculated display layout. The value of the layout bound may be assignable, creating greater flexibility in controlling layout. Additionally, the value assigned to the layout bound may be changed. In this way, layout of nodes with respect to each other is flexible and visual effects and animations can either be factored into that layout or not. | 12-02-2010 |
20100301915 | LATCH WITH SINGLE CLOCKED DEVICE - A D-latch circuit includes a feed forward circuit, a full keeper circuit, and an output buffer circuit. The feed forward circuit inputs a clock signal and a data signal. The feed forward circuit is connected to an input of the full keeper circuit. The feed forward circuit is connected to an output of the full keeper circuit and an input of the output buffer circuit. The output buffer circuit outputs an output signal. The D-latch consists of a single clocked device that switches with the clock signal. | 12-02-2010 |
20100301914 | LATCH WITH CLOCKED DEVICES - A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node. | 12-02-2010 |
20100296383 | REDUCED ENERGY CONSUMPTION USING ACTIVE VIBRATION CONTROL - Embodiments of a computer system that includes a vibration-cancelling mode, and a related method and computer-program product (e.g., software) for use with the computer system, are described. During operation, a processor monitors operations in the computer system, and may select either the vibration-cancelling mode or an inactive mode based on the monitored operations. For example, the processor may select the vibration-cancelling mode when there are input/output-(I/O) intensive workloads to an array of one or more hard disk drives (HDDs) in the computer system. In this way, the processor may reduce the energy consumption associated with vibration-induced retries to the HDDs (and reduced I/O throughput) without increasing the energy consumption associated with active vibration damping at other times, such as when the computer system is idle or during processor-intensive workloads. | 11-25-2010 |
20100292959 | Telemetry data analysis using multivariate sequential probability ratio test - One embodiment provides a system that analyzes telemetry data from a monitored system. During operation, the system periodically obtains the telemetry data as a set of telemetry variables from the monitored system and updates a multidimensional real-time distribution of the telemetry data using the obtained telemetry variables. Next, the system analyzes a statistical deviation of the multidimensional real-time distribution from a multidimensional reference distribution for the monitored system using a multivariate sequential probability ratio test (SPRT) and assesses the integrity of the monitored system based on the statistical deviation of the multidimensional real-time distribution. If the assessed integrity falls below a threshold, the system determines a fault in the monitored system corresponding to a source of the statistical deviation. | 11-18-2010 |
20100290736 | OPTICAL DEVICE WITH LARGE THERMAL IMPEDANCE - Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon), and includes a thermally tunable optical waveguide that has good thermal isolation from its surroundings. In particular, a portion of a semiconductor in the optical device, which includes the optical waveguide, is free standing above a gap between the semiconductor layer and the substrate. By reducing the thermal coupling between the optical waveguide and the external environment, the optical device can be thermally tuned with significantly less power consumption. | 11-18-2010 |
20100290144 | INVARIANT MULTI-DIMENSIONAL VIBRATION-RESILIENCE-SIGNATURE GENERATION SYSTEM - One embodiment of the present invention provides a system that generates vibration-resistance signatures for hard disk drives (HDDs). In this system, a set of HDDs is mechanically affixed to a disk enclosure. The system additionally includes a vibration generator which is mechanically coupled to the disk enclosure and can apply a translational vibration profile to the disk enclosure. The system further includes a coupling mechanism between the set of HDDs and the disk enclosure which translates the translational vibration profile into both translational and rotational vibrations for the set of HDDs in multiple dimensions. The system additionally includes a monitoring mechanism which monitors an HDD performance metric from the set of HDDs while the HDDs are subject to the translational and rotational vibrations. The system also includes a signature-generation mechanism which uses the monitored HDD performance metric to generate vibration-resistance signatures for the set of HDDs. | 11-18-2010 |
20100287516 | METHODS AND SYSTEM FOR SELECTING GATE SIZES, REPEATER LOCATIONS, AND REPEATER SIZES OF AN INTEGRATED CIRCUIT - A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendant gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins. | 11-11-2010 |
20100287455 | ENFORCING NETWORK BANDWIDTH PARTITIONING FOR VIRTUAL EXECUTION ENVIRONMENTS WITH DIRECT ACCESS TO NETWORK HARDWARE - A method for enforcing network bandwidth partitioning. The method includes verifying that a guest driver in a guest operating system (OS) is configured to enforce a resource usage policy, wherein the guest OS resides on a host, mapping a hardware receive ring (HRR) residing on a physical network interface card (NIC) operatively connected to the host to the guest OS, wherein after the mapping the guest OS is configured to receive packets directly from the HRR, determining, using monitoring information, that the guest OS should not receive packets directly from the HRR, and in response to the determination, creating a data path from the HRR to a host OS executing on the host, receiving packets for the guest OS from the HRR by the host OS over the data path, and forwarding the packets from the host OS to the guest OS. | 11-11-2010 |
20100287356 | LARGE MEMORY PAGES FOR SHARED LIBRARIES - A method for loading shared libraries. The method includes receiving an indication of a requirement to load the shared library into the virtual memory and determining that the shared library is a candidate for using shared large pages. Further, the method includes, in response to the determination, storing a text section of the shared library in a shared large page of the virtual memory and storing a data section of the shared library in a page of the virtual memory, where the virtual memory is mapped to a physical memory of the computer, where, within an address space of the virtual memory, a starting address of the text section of the shared library is separated from a starting address of the data section of the shared library by a predefined distance, and where the predefined distance is larger than a size of the large page. | 11-11-2010 |
20100287347 | METHOD AND SYSTEM FOR MAPPING DATA TO A PROCESS - The invention relates to mapping data to a process. A method of the invention includes receiving a request to copy a parent process, where the parent process is associated with a first virtual memory address space that includes a first mapping to a page of a file loaded into physical memory. The method includes creating a child process (of the parent process) associated with a second virtual memory address space. The method includes determining that a fork count is greater than a fork count threshold and a COW count to fork count ratio is greater than a threshold ratio. The fork count is associated with the file and the COW count is associated with the page. The method includes creating a copy of the page in physical memory and further includes creating a second mapping from the second virtual memory address space to the copy of the page. | 11-11-2010 |
20100287184 | APPARATUS, SYSTEMS AND METHODS FOR CONFIGURABLE DEFAULTS FOR XML DATA - A data tree is generated in memory by parsing a first XML file. Default setting requests and validation requests are read from a second XML file. Default data values for nodes in the data tree are generated by executing default data generation code from locations specified in the default setting requests and recorded in the data tree. The content of data stored in nodes of the data tree is then validated by executing validation code from locations specified in the validation requests. The data tree is then searched by getting a nodepath, parsing the nodepath into a plurality of path pieces, searching the data tree based on each of the path pieces, and returning one or more nodes of the data tree based on the search that satisfy the path pieces. A data value of one or more nodes or child nodes may be specified to narrow the search. | 11-11-2010 |
20100286974 | TECHNIQUE USING POWER MACROMODELING FOR REGISTER TRANSFER LEVEL POWER ESTIMATION - A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model. | 11-11-2010 |
20100284781 | MITIGATING MECHANICAL VIBRATIONS CAUSED BY A FAN IN A COMPUTER SYSTEM - One embodiment provides a system that mitigates vibrations caused by cooling fans in a computer system. More specifically, the system includes a cooling fan mechanically coupled to the chassis of the computer system, wherein vibrations generated by the cooling fan are coupled to the chassis. The system also includes an actuation mechanism that creates a relative displacement between the cooling fan and the chassis when a control signal is applied to the actuation mechanism. The system additionally includes a detection mechanism which detects the relative displacement and generates a feedback signal which represents the relative displacement. The system further includes a control signal generation mechanism which converts the feedback signal into the control signal, which is subsequently applied to the actuation mechanism. When the control signal is applied to the actuation mechanism, the relative displacement between the cooling fan and the chassis vibrationally decouples the cooling fan from the chassis. | 11-11-2010 |
20100284279 | METHOD AND SYSTEM FOR MONITORING NETWORK COMMUNICATION - A method for monitoring communication on a network. The method includes configuring a classifier using a monitoring rule, receiving a plurality of packets from the network; analyzing each of the plurality of packets by the classifier to determine to which of the plurality of packets satisfies the monitoring rule; forwarding any of the plurality of packets that satisfy the monitoring rule to a first hardware receive ring (HRR) located on a first physical network interface (NI), forwarding any of the plurality of packets that do not satisfy the monitoring rule to a second HRR, and transmitting a first number of packets from the first HRR directly to user level memory, wherein the user level memory resides on a host operatively connected to the first physical NI. | 11-11-2010 |
20100283793 | SYSTEM AVAILABLE CACHE COLOR MAP - A method involving receiving an indication of a requirement to allocate at least one page for a process, where pages are associated with cache colors; generating a selection bitmap by performing a logical operation of a system available colors bitmap and a process bitmap, where the system available colors bitmap and the process bitmap each include one bit corresponding to each cache color, where each bit of the system available colors bitmap indicates whether a number of pages associated with a corresponding cache color that are available to be allocated is above a minimum threshold, and where each bit of the process bitmap indicates whether any pages associated with the corresponding cache color have been recently allocated for the process. The method also includes selecting, using the selection bitmap, a cache color; and allocating a page for the process, wherein the allocated page is associated with the selected cache color. | 11-11-2010 |
20100282932 | SERVER CHASSIS RACK RAIL WITH SELF-ALIGNING, MAGNETIC GUIDE ASSEMBLY FOR POSITIONING SERVERS IN STORAGE RACK - A storage rack for supporting a server chassis in a storage cabinet. The storage rack includes vertical supports and outer rails attached to the vertical supports. The storage rack includes first and second middle rails supported by the first and second outer rails such that the middle rails may slide upon the outer rails. First and second inner rails slidably engage with the first and second outer rails and are typically attached the sides of the chassis. The storage rack further includes first and second magnetic guide assemblies that are each attached to an exposed end of one of the first and second inner rails. Each of the magnetic guide assemblies includes first and second magnetic alignment elements extending outward an alignment distance from the exposed end of the corresponding one of the inner rails such that magnetic forces assist both in initial alignment and in engagement. | 11-11-2010 |
20100281442 | TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES - Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit. | 11-04-2010 |
20100281201 | PROTOCOL TRANSLATION IN A DATA STORAGE SYSTEM - A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor, memory, and a storage module. The storage module includes a storage controller, and an interface block for connecting the storage module to a corresponding memory-mapped interface. The storage unit further includes a host channel adaptor. The storage unit host channel adapter is connected to a corresponding memory-mapped interface. The storage unit host channel adapter is capable of remote direct memory access to the input/output server. Protocol translation logic is configured to intercept a memory access request from the storage controller, and initiate a corresponding remote direct memory access to the input/output server through the storage unit host channel adapter and the input/output server host channel adapter. | 11-04-2010 |
20100280651 | DATA CARTRIDGE AND TAPE LIBRARY INCLUDING FLASH MEMORY - A data storage system for use with a plurality of tape cartridges is provided. Each tape cartridge includes a length of tape media and an amount of flash memory. The data storage system includes a tape cartridge library having a plurality of storage cells. Each storage cell is configured to store a tape cartridge. The tape cartridge library further includes a plurality of tape drives. Each tape drive is configured to access a tape cartridge when the tape cartridge is received in the tape drive. The system further includes a robotic tape mover and a flash memory access mechanism. The robotic tape mover moves tape cartridges between the plurality of storage cells and the plurality of tape drives. The flash memory access mechanism is configured in the tape cartridge library to access the flash memory of a tape cartridge when the tape cartridge is in the tape cartridge library. | 11-04-2010 |
20100275053 | CLOCK SKEW MEASUREMENT FOR MULTIPROCESSOR SYSTEMS - Systems and methods (“utility”) for providing more accurate clock skew measurements between multiple CPUs in a multiprocessor computer system by utilizing the cache control or management protocols of the CPUs in the multiprocessor system. The utility may utilize a time stamp counter (TSC) register of the CPUs in the multiprocessor computer system to detect the clock skew between the various CPUs in the system. Further, the delay between measurements of the TSC registers of the CPUs may be minimized by utilizing the features of the hardware cache control or management protocols of the computer system, thereby providing more accurate clock skew measurements. | 10-28-2010 |
20100274551 | SUPPORT FOR A NON-NATIVE APPLICATION - Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary. Moreover, the product includes program code for fast-forwarding at least one thread so that its state is consistent with the guest instruction boundary | 10-28-2010 |
20100271793 | PRINTED CIRCUIT BOARD WITH OPTIMIZED MOUNTING HOLES AND ALIGNMENT PINS - A mounting plane assembly (e.g., backplane or midplane) is provided for interconnecting a plurality of daughterboards in a server computer. The mounting plane assembly includes a printed circuit board (“PCB”) that has a plurality of shared mounting holes for attaching connector alignment pins to a front side of the PCB as well as mechanical support elements to a back side of the PCB through the same mounting holes. | 10-28-2010 |
20100271100 | MINIMAL BUBBLE VOLTAGE REGULATOR - A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator. | 10-28-2010 |
20100271099 | FINE GRAIN TIMING - A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain. | 10-28-2010 |
20100271085 | DELAY CHAIN INITIALIZATION - A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous. | 10-28-2010 |
20100271076 | PRECISION SAMPLING CIRCUIT - A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input. | 10-28-2010 |
20100268960 | SYSTEM AND METHOD FOR ENCRYPTING DATA - A method for encrypting data includes receiving a block of plaintext for a data set at one or more computers, acquiring a cryptographic key for the data set, generating an initialization vector for the block of plaintext based on the block of plaintext, and encrypting the block of plaintext using the cryptographic key and the initialization vector. | 10-21-2010 |
20100266295 | OPTICAL-SIGNAL-PATH ROUTING IN A MULTI-CHIP SYSTEM - Embodiments of a system are described. This system includes an array of chip modules (CMs) that are configured to communicate data signals with each other via optical communication. In a given CM module, optical signal paths, such as waveguides, are routed in the same way as in the other CMs in the array. In this way, a common optical design in the CMs may be used in the system to prevent data conflicts during the optical communication. | 10-21-2010 |
20100266277 | DATA TRANSMISSION USING DIRECT AND INDIRECT OPTICAL PATHS - A system for transmitting data, including: a transmitter node having a setup path packet and multiple data packets; a receiver node connected to the transmitter node by a first optical channel (OC); and a first intermediate node having a first forwarding module and connected to the transmitter node by a second OC and to the receiver node by a third OC, where the transmitter node transmits the setup path packet and a first subset of the multiple data packets to the first intermediate node using the second OC, where the first forwarding module relays, in response to receiving the setup packet, the first subset to the receiver node by switching the first subset from the second OC to the third OC, and where the receiver node receives a second subset of the multiple data packets from the transmitter node using the first OC. | 10-21-2010 |
20100266276 | BROADBAND AND WAVELENGTH-SELECTIVE BIDIRECTIONAL 3-WAY OPTICAL SPLITTER - Embodiments of a bidirectional 3-way optical splitter are described. This bidirectional 3-way optical splitter includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes. | 10-21-2010 |
20100266240 | MULTI-CHIP SYSTEM INCLUDING CAPACITIVELY COUPLED AND OPTICAL COMMUNICATION - Embodiments of a system are described. This system includes an array of chip modules (CMs) and a baseplate, where the baseplate is configured to communicate data signals via optical communication. Moreover, the array includes first CMs mechanically coupled to first alignment features on the baseplate, and adjacent second CMs mechanically coupled to second alignment features on the baseplate. In this array, a given first CM is electrically coupled to a given set of electrical proximity connectors. Additionally, the array includes bridge components, wherein a given bridge component is electrically coupled to the second SCM and another set of electrical proximity connectors, which is electrically coupled to the set of electrical proximity connectors, thereby facilitating communication of other data signals between adjacent first CMs and second CMs via electrical proximity communication. Moreover, the given bridge component is optically coupled to the baseplate, thereby facilitating optical communication of the data signals between CMs via the baseplate. | 10-21-2010 |
20100264973 | ECONOMY PRECISION PULSE GENERATOR - A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit. | 10-21-2010 |