STMICROELECTRONICS GRENOBLE2 SAS Patent applications |
Patent application number | Title | Published |
20130163615 | CONTROL DEVICE, FOR INSTANCE FOR SYSTEMS-ON-CHIP, AND CORRESPONDING METHOD - A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device ( | 06-27-2013 |
20130070830 | CHARACTERIZATION OF THE JITTER OF A CLOCK SIGNAL - A method for characterizing jitter of an internal clock signal of a circuit may include generating a series of samples of the internal clock signal by a reference clock signal, comparing the word formed by the N most recent samples of the series to an N-bit pattern, where N is an integer greater than, or equal to 2, and incrementing a first counter if the word complies with the pattern. The method may also include incrementing a second counter when the count of the first counter reaches a first threshold X1, and incrementing a third counter when the count of the first counter reaches a second threshold different from the first. The method may include calculating an average p and a standard deviation σ of a Gaussian density curve as a function of the counts reached in the second and third counters. | 03-21-2013 |
20130061016 | VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER - A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed. | 03-07-2013 |
20120210288 | METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING FOR SOURCE IDENTIFIER ALLOCATION - A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order. | 08-16-2012 |
20120210093 | METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING TO MODIFY SOURCE IDENTITY - A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field. | 08-16-2012 |
20100232687 | METHOD AND DEVICE FOR REORDERING IMAGE DATA HAVING A DISTRIBUTION OF THE BAYER PATTERN TYPE - The present disclosure relates to a method for reordering data organized according to a matrix configuration, comprising steps of reading line by line input data having a matrix configuration ( | 09-16-2010 |