Shenzhen STS Microelectronics Co. LTD. Patent applications |
Patent application number | Title | Published |
20090174391 | ZERO CURRENT DETECTOR FOR A DC-DC CONVERTER - A zero current detector for a DC-DC converter includes a first transistor having a drain, a gate, and a source for sensing the voltage of a first terminal of a power transistor; a second transistor having a drain, a gate, and a source for sensing the voltage of a second terminal of a power transistor; and a third transistor having a coupled gate and drain for receiving a reference current that is coupled to the gates of the first and second transistors and a source coupled to the source of the first transistor, wherein an output signal is provided by the drains of the first and second transistors. A load is coupled to the drains of the first and second transistors. The zero current detector also includes a fourth transistor having a current path coupled between the source of the second transistor and the second terminal of the power transistor and a gate for receiving a control signal. | 07-09-2009 |
20090039857 | DRIVER WITH CONTROL INTERFACE FACILITATING USE OF THE DRIVER WITH VARIED DC-TO-DC CONVERTER CIRCUITS - A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal. | 02-12-2009 |
20080292027 | DRM receiver and demodulation method - A Digitial Radio Mondiale (DRM) receiver and demodulation method includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. This reduces the processing/computational requirements and the design complexity of the DRM receiver. | 11-27-2008 |
20080285638 | Channel equalization in a receiver - A method of estimating a channel response of a channel is provided that includes transforming a frequency domain signal received via the channel into a time domain signal and searching the time domain signal for a location of minimum energy. The method also includes padding the time domain signal with zeroes at the location of minimum energy and transforming the padded time domain signal to a second frequency domain signal. The second frequency domain signal is used as an estimated channel response for the channel. | 11-20-2008 |
20080279314 | Digital Radio Mondiale receiver integer carrier frequency offset estimation - A method and apparatus for estimating a carrier frequency offset (CFO) in a Digital Radio Mondiale receiver is provided. Orthogonal frequency-division multiplexing (OFDM) demodulation is performed on a received DRM signal to produce OFDM symbols. A cell characteristic in corresponding cells in the OFDM symbols is compared and a carrier index of a frequency pilot cell in the cells is identified based upon the compared cell characteristic. The CFO is estimated based on the identified carrier index of the frequency pilot cell. The ratio of values of the cell characteristic in corresponding cells may be calculated and the frequency pilot cell identified by identifying cells for which the cell characteristic is most nearly equal. The CFO may be estimated by comparing the identified carrier index with an expected carrier index of a frequency pilot cell. | 11-13-2008 |
20080279313 | Sample clock frequency offset estimation in DRM - A system and method for estimating sample clock frequency offset (ε | 11-13-2008 |
20080279090 | DRM receiver with analog and digital separation filter and demodulation method - A Digital Radio Mondiale (DRM) receiver and demodulation method includes an analog and digital separation filter for filtering and separating a DRM-encoded signal and a non DRM-encoded signal from a composite RF signal received at the receiver. The DRM receiver includes a programmable downsampler and a programmable N-point Fast Fourier Transform (FFT) to recover and demodulate the OFDM symbols in a received DRM-encoded RF signal. The received signal is digitally sampled at a rate operably integer downsampled to achieve a number N samples in the useful portion of the OFDM symbol for input to an N-point FFT, where N equal to a power of two. The downsampling rate and size (N-points) of the FFT depend on the DRM encoding and transmission parameters, notably the robustness mode and spectrum occupancy. The structure and operation of the receiver in this manner simplifies the design and reduces the required filter order of the analog and digital separation filter. | 11-13-2008 |
20080278870 | OVER CURRENT DETECTION CIRCUITS FOR MOTOR DRIVER - A motor driver having over current detection circuitry includes an H-bridge having a first differential input, a second differential input, and a differential output; a sensing circuit coupled to the differential output of the H-bridge; a comparison and logic circuit coupled to the sensing circuit; a pair of pre-driver circuits coupled to the comparison and logic circuit for driving at least one of the differential inputs of the H-bridge; and a pair of level shifters coupled between the comparison and logic circuit and the sensing circuit. The H-bridge includes a first side having a first transistor coupled to a second transistor, and a second side having a third transistor coupled to a fourth transistor. The first and third transistors are power PDMOS transistors, and the second and fourth transistors are power NDMOS transistors. The pair of level shifters are used to assure that the V | 11-13-2008 |
20080224761 | OPAMP-LESS BANDGAP VOLTAGE REFERENCE WITH HIGH PSRR AND LOW VOLTAGE IN CMOS PROCESS - A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core. | 09-18-2008 |