SANDISK TECHNOLOGIES INC. Patent applications |
Patent application number | Title | Published |
20160141301 | THREE DIMENSIONAL NON-VOLATILE MEMORY WITH SEPARATE SOURCE LINES - A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages. | 05-19-2016 |
20160141029 | HEALTH DATA ASSOCIATED WITH A RESISTANCE-BASED MEMORY - A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path. | 05-19-2016 |
20160140011 | VISUAL INDICATOR FOR PORTABLE DEVICE - A portable device may perform a method that includes detecting that the portable device is coupled to a host device via a host interface of the portable device. The method includes generating a visual indication at a visual indicator of the portable device. The visual indication is indicative of a data transfer capacity of the host interface. | 05-19-2016 |
20160133324 | SHAPED DATA ASSOCIATED WITH AN ERASE OPERATION - A method includes, in a data storage device including a resistive memory, receiving an erase command to erase a portion of the resistive memory. The method further includes sending shaped data to be stored at the portion of the resistive memory responsive to the erase command. | 05-12-2016 |
20160133322 | DISTURB CONDITION DETECTION FOR A RESISTIVE RANDOM ACCESS MEMORY - A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information. | 05-12-2016 |
20160125960 | SYSTEM AND METHOD FOR WRITE ABORT DETECTION - Systems, apparatuses, and methods are provided for write abort detection. A memory system may write data to one or more cells in a memory. An abrupt shutdown may interrupt the write, resulting in an uncertainty as to the state of the memory cells. In order to determine the state of the memory cells, after power-up, a first section of memory that includes the memory cells is analyzed, such as counting values of logic “0”s stored in the memory cells of the first section of memory. However, the values in the first section of memory may be subject to error, hindering the accuracy of write abort detection. In order to reduce or cancel the effect of the errors, a second section of memory (which may suffer from similar errors as the first section) is analyzed, such as by counting values of logic “0”s stored in the memory cells of the second section of memory. The differential value of the counts from the two sections is determined, thereby reducing or eliminating the effect of the errors, and then analyzed to determine the state of the first section of memory for write abort detection. | 05-05-2016 |
20160124982 | SYSTEM AND METHOD FOR SELECTIVELY ROUTING CACHED OBJECTS - A monitoring application and method for using a monitoring application are disclosed. The monitoring application is configured to manage file system objects in a memory device layer (including copying of the file system objects) and is configured to manage one or more data structures to enable the management of the file system objects to be transparent to the application layer and/or the operating system layer. | 05-05-2016 |
20160120031 | SEMICONDUCTOR PACKAGE WITH DUAL SECOND LEVEL ELECTRICAL INTERCONNECTIONS - A semiconductor package such as a multi-chip package is disclosed. The semiconductor package may be configured for dual second level interconnection onto a printed circuit board of a host device. Thus, a single semiconductor package may be used on host printed circuit boards having different configurations. | 04-28-2016 |
20160118136 | ERROR DETECTION METHOD - Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect. | 04-28-2016 |
20160118135 | TWO-STROBE SENSING FOR NONVOLATILE STORAGE - A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements. | 04-28-2016 |
20160118134 | WORD LINE DEPENDENT TWO STROBE SENSING MODE FOR NONVOLATILE STORAGE ELEMENTS - A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements. | 04-28-2016 |
20160118131 | Adaptive Program Pulse Duration Based On Temperature - Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state. | 04-28-2016 |
20160118128 | METHODS FOR REDUCING BODY EFFECT AND INCREASING JUNCTION BREAKDOWN VOLTAGE - Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect. | 04-28-2016 |
20160118125 | COMPACTION PROCESS FOR A DATA STORAGE DEVICE - A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process. | 04-28-2016 |
20160117260 | Method and Computing Device for Encrypting Data Stored in Swap Memory - The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area. | 04-28-2016 |
20160111164 | Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory - Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized. | 04-21-2016 |
20160109926 | MODIFIED WRITE PROCESS BASED ON A POWER CHARACTERISTIC FOR A DATA STORAGE DEVICE - A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold. | 04-21-2016 |
20160103732 | Storage Module and Method for Datapath Bypass - A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided. | 04-14-2016 |
20160099078 | DATA STORAGE DEVICE HAVING REFLOW AWARENESS - A method includes, responsive to a power-up event at a data storage device that includes a memory, reading a flag stored at the data storage device and determining that the flag has a first value indicating that a reflow operation has not previously been detected at the memory. The method also includes, in response to determining that the flag has the first value, performing reflow detection at the memory. The method further includes, in response to the reflow detection indicating that the reflow operation has occurred, setting the flag to a second value. | 04-07-2016 |
20160099065 | LATCH INITIALIZATION FOR A DATA STORAGE DEVICE - A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die. The set of bits includes at least a first bit having a first value and a second bit having a second value that is different than the first value. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information. | 04-07-2016 |
20160099034 | I/O PIN CAPACITANCE REDUCTION USING TSVS - Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance. | 04-07-2016 |
20160098216 | SYSTEM AND METHOD FOR REFRESHING DATA IN A MEMORY DEVICE - Systems, apparatuses, and methods are provided that refresh data in a memory. Data is programmed into the memory. After which, part or all of the data may be refreshed. The refresh of the data may be different from the initial programming of the data in one or more respects. For example, the refresh of the data may include fewer steps than the programming of the data and may be performed without erasing a section of memory. Further, the refresh of the data may be triggered in one of several ways. For example, after programming the data, the data may be analyzed for errors. Based on the number of errors found, the data may be refreshed. | 04-07-2016 |
20160098215 | Method and System for Adaptively Assigning Logical Block Address Read Counters Using a Tree Structure - Systems, apparatuses, and methods are provided that dynamically reassign counters (or other memory monitors) in a memory. A plurality of counters may be assigned to different address ranges within an overall address range of a memory. The value of the counter may be indicative of activity, such as reads, within a respective assigned address range. Depending on the value of the counter, the respective address range of the counter may be dynamically changed. For example, a counter with a high value (indicating higher activity within the address range) may have its respective address range divided, with two counters being assigned to each of the divided address ranges. Likewise, counters with low values (indicating less activity within the address ranges) may have their respective address ranges combined, with a single counter being assigned to the combined address ranges. Thus, in subdividing and combining address ranges, the number of counters assigned may remain the same, while still monitoring the activity with the overall address range. | 04-07-2016 |
20160093383 | METHOD AND APPARATUS FOR RELOCATING DATA IN NON-VOLATILE MEMORY - Apparatus and methods implemented therein, in response to receiving an indication to program data to both a primary and secondary memory page determine whether a folding operation is in progress. In response to determining that the folding operation is in progress, programming of the data is delayed until completion of the folding operation. In response to determining the completion of the folding operation, data is programmed to the primary memory page and secondary memory page. | 03-31-2016 |
20160093372 | READING RESISTIVE RANDOM ACCESS MEMORY BASED ON LEAKAGE CURRENT - A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current. | 03-31-2016 |
20160092325 | FAILURE LOGGING MECHANISM TO REDUCE GARBAGE COLLECTION TIME IN PARTIALLY REUSED BAD BLOCKS - A memory system logs failures to optimize garbage collection in partial bad blocks that are reused in non-volatile memory. A failure in a primary block may be logged in an inverse global address table. A garbage collection operation can reference the log in order to automatically avoid the failure in the primary block when the primary block is picked as the source block for garbage collection. Likewise, the garbage collection operation may scan only the logged wordlines in the secondary block when the secondary block is picked as the source block for garbage collection. | 03-31-2016 |
20160092302 | INITIALIZATION SCHEME DURING DUAL PROGRAMMING OF A MEMORY SYSTEM - A memory system or flash memory device may include mechanism for handling power loss with a dual programming architecture. The state of primary and secondary blocks may be reconstructed to a state immediately preceding a power loss. The reconstruction may include comparing error correction code (ECC) headers of blocks to recreate a block exchange with fewer control updates. The comparison can be used to identify a primary and secondary block. The header may identify a particular stream, identify a free block, identify a release block, and other information. | 03-31-2016 |
20160092122 | METHOD AND APPARATUS FOR WEAR-LEVELLING NON-VOLATILE MEMORY - Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated. | 03-31-2016 |
20160086675 | WORD LINE DEPENDENT TEMPERATURE COMPENSATION SCHEME DURING SENSING TO COUNTERACT CROSS-TEMPERATURE EFFECT - Methods for reducing cross-temperature dependent word line failures using a temperature dependent sensing scheme during a sensing operation are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time, source line voltage, or bit line voltage) may be set based on a temperature of the memory cells during sensing and a word line location of the memory cells to be sensed. In one example, the memory array may comprise a NAND memory array that includes a NAND string and the sensing time for sensing a memory cell of the NAND string and the source line voltage applied to a source line connected to a source end of the NAND string may be set based on the temperature of the memory cells during sensing and the word line location of the memory cells to be sensed. | 03-24-2016 |
20160086674 | TEMPERATURE DEPENDENT SENSING SCHEME TO COUNTERACT CROSS-TEMPERATURE THRESHOLD VOLTAGE DISTRIBUTION WIDENING - Methods for reducing cross-temperature threshold voltage distribution widening by applying a temperature dependent sensing scheme during read operations are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time and the read voltage applied to the memory cells during the sensing time) may be set and/or adjusted based on a temperature of the memory cells during the read operation, a previous temperature of the memory cells when the memory cells were programmed, and the programmed states of neighboring memory cells. In some cases, the sensing time for sensing a memory cell of a NAND string and the source voltage applied to a source line connected to the NAND string may be set based on the temperature of the memory cells during sensing and the previous temperature of the memory cells when the memory cells were programmed. | 03-24-2016 |
20160085464 | Storage Module and Method for On-Chip Copy Gather - A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided. | 03-24-2016 |
20160077968 | SYSTEM AND METHOD FOR CONFIGURING AND CONTROLLING NON-VOLATILE CACHE - Systems and methods for configuring, controlling and operating a non-volatile cache are disclosed. A host system may poll a memory system as to the memory system's configuration of its non-volatile cache. Further, the host system may configure the non-volatile cache on the memory system, such as the size of the non-volatile cache and the type of programming for the non-volatile cache (e.g., whether the non-volatile cache is programmed according to SLC or the type of TRIM used to program cells in the non-volatile cache). Moreover, responsive to a command from the host to size the non-volatile cache, the memory system may over or under provision the cache. Further, the host may control operation of the non-volatile cache, such as by sending selective flush commands. | 03-17-2016 |
20160077961 | Storage Module and Method for Scheduling Memory Operations for Peak-Power Management and Balancing - A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains a count of time slots over a period of time. The period of time corresponds to an amount of time between periodic power peaks of a memory operation. For each time slot, the storage module determines whether to commence a memory operation on one or more of the plurality of memory dies based on whether a power peak generated in the time slot by the memory operation would exceed a power threshold allowed for the time slot. Other embodiments are provided. | 03-17-2016 |
20160070643 | SYSTEM AND METHOD OF COUNTING PROGRAM/ERASE CYCLES - A method includes, in a data storage device that includes a memory, detecting an operation associated with a block of the memory. The operation is associated with a program/erase cycle. The method further includes, responsive to detecting the operation, performing a comparison between a random number and at least one value of a set of values. The method includes selectively adjusting a value of a counter associated with the block based on the comparison. | 03-10-2016 |
20160070488 | MULTI-STAGE PROGRAMMING AT A STORAGE DEVICE USING MULTIPLE INSTRUCTIONS FROM A HOST - A method performed by a data storage device includes receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device and receiving a second instruction of the first set of instructions to write the first group of pages of data. A first stage of a multi-stage programming operation is performed at a first physical address of the memory using a first copy of the first group of pages, and a second stage of the multi-stage programming operation is performed at the first physical address of the memory using a second copy of the first group of pages. The first copy and the second copy are received from the host device in association with the first instruction and the second instruction, respectively. | 03-10-2016 |
20160064090 | Charge Redistribution During Erase In Charge Trapping Memory - Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole. | 03-03-2016 |
20160064084 | Programming Memory With Reduced Short-Term Charge Loss - Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed. | 03-03-2016 |
20160064079 | THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY AND DRAM MEMORY DEVICES ON A SINGLE SUBSTRATE - A three-dimensional NAND stacked non-volatile memory array and a DRAM memory array are provided. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are integrated on a single substrate. | 03-03-2016 |
20160062657 | DYNAMIC HOST COMMAND REJECTION - A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table. | 03-03-2016 |
20160055910 | Storage Module and Method for Using Healing Effects of a Quarantine Process - A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge. | 02-25-2016 |
20160054937 | TEMPERATURE ACCELERATED STRESS TIME - A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions. | 02-25-2016 |
20160049203 | SYSTEM AND METHOD OF USING MULTIPLE READ OPERATIONS - Systems and methods are described for reading a storage element of a memory. In a particular embodiment, a method, in a data storage device including a controller and a non-volatile memory, where the non-volatile memory includes a plurality of storage elements, includes performing multiple read operations at a storage element of the non-volatile memory. Each read operation of the multiple read operations is performed using the same reading voltage. The method further includes determining a read value of the storage element based on the multiple read operations. | 02-18-2016 |
20160041891 | Storage Module and Method for Analysis and Disposition of Dynamically Tracked Read Error Events - A method for analyzing a read error event is provided comprising reading a page of data stored in memory, determining a read error event for the page of data, and identifying a scope of the read error event in the memory. In another embodiment, a method for performing a preliminary read error recovery is provided comprising reading a first data unit from memory and identifying a bit error rate for a first data unit with a correction engine, determining that the bit error rate is above a threshold, accessing a data structure including entries identifying data units and read error event information associated with the data units, identifying a second data unit in an entry that matches the first data unit, and performing a preliminary read error recovery process on the first data unit using the information in the entry to reduce the bit error rate below the threshold. | 02-11-2016 |
20160041786 | Storage Module and Method for Optimized Power Utilization - A storage module and method are provided for optimized power utilization. In one embodiment, a storage module is provided comprising a storage controller and a plurality of memory dies in communication with the storage controller. The storage controller determines if sufficient power is available to perform an operation on one of the memory dies. In response to determining that sufficient power is not available to perform the operation on one of the memory dies, the storage controller determines if suspending an in-progress operation on another one of the memory dies would provide enough power to perform the operation. In response to determining that suspending the in-progress operation would provide enough power to perform the operation, the storage controller suspends the in-progress operation and performs the operation. Instead of suspending an in-progress operation, the storage controller can instead use a reduced power version of the operation or the in-progress operation. | 02-11-2016 |
20160041774 | COMMAND AND DATA SELECTION IN STORAGE CONTROLLER SYSTEMS - A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached. | 02-11-2016 |
20160034353 | Storage Module and Method for Improved Error Correction by Detection of Grown Bad Bit Lines - A storage module and method are provided for improved error correction by detection of grown bad bit lines. In one embodiment, a storage module is provided comprising a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word. | 02-04-2016 |
20160034198 | SYSTEM AND METHOD FOR MANAGING DISCARDABLE OBJECTS - A method and system of managing data in a storage device is provided. The method includes receiving a request to store content in a storage device. If the content is discardable content, the content is divided into a plurality of discardable data objects, each associated with at least one type of discarding priority data. The discardable data objects in the storage device are managed based on the discarding priority data associated with each discardable data object. Management of discardable objects may include selection and deletion of discardable objects based on discarding priority data, as well as further subdivision of existing discardable objects, to maintain a desired amount of free space on the storage device. The system may include a host having a processor and a storage device interface configured to execute the method, or a storage device having a processor configured to execute the disclosed methods. | 02-04-2016 |
20160034187 | Storage Module and Method for Virtual Abort - A storage module and method for virtual abort are disclosed. In one embodiment, a virtual abort of a read command is provided. The read command triggers a read operation that comprises reading data from the storage module's memory, processing the data by at least one processing module as the data moves along a data path from the memory to the storage module's host interface module, and then providing the data to a host via the host interface module. When an abort command is received, the storage module allows the data that is read from the memory to be processed by the at least one processing module as the data moves along the data path to the host interface module but prevents the host interface module from providing the data to the host. In another embodiment, a virtual abort of a write command is provided. | 02-04-2016 |
20160019054 | Method and System for Generating a ROM Patch - A method and system for generating a ROM patch are provided. In one embodiment, a computing device obtains an original assembly code and a modified assembly code which is a modified version of the original assembly code, the original assembly code being used for an executable code which is stored in a ROM of a device. The computing device compares the original assembly code and the modified assembly code to identify difference(s) in the modified assembly code with respect to the original assembly code. The computing device then compiles the difference(s) (sometimes, after adjusting the differences) and generates a ROM patch by converting the compiled difference(s) into a replacement executable code for some of the executable code stored in the ROM of the device. In another embodiment, a method and system for using a ROM patch are disclosed. | 01-21-2016 |
20160019036 | Method and System for Using a ROM Patch - A method and system for using a ROM patch are provided. In one embodiment, a computing device obtains an original assembly code and a modified assembly code which is a modified version of the original assembly code, the original assembly code being used for an executable code which is stored in a ROM of a device. The computing device compares the original assembly code and the modified assembly code to identify difference(s) in the modified assembly code with respect to the original assembly code. The computing device then compiles the difference(s) (sometimes, after adjusting the differences) and generates a ROM patch by converting the compiled difference(s) into a replacement executable code for some of the executable code stored in the ROM of the device. In another embodiment, a method and system for using a ROM patch are disclosed. | 01-21-2016 |
20160006458 | DECODING TECHNIQUES FOR LOW-DENSITY PARITY CHECK CODES - A data storage device includes a memory. A method includes initiating a decoding process at the data storage device to decode data sensed from the memory. The method further includes accessing a mapping table to determine a variable node message value during a variable node processing operation of the decoding process. | 01-07-2016 |
20160005464 | COUNTER FOR WRITE OPERATIONS AT A DATA STORAGE DEVICE - A data storage device includes a resistive random access memory (ReRAM). A method includes storing data in the ReRAM by performing a first number of write operations to a storage region of the ReRAM. The storage region is tracked by a counter. The method further includes incrementing a value of the counter a second number of times responsive to storing the data in storage region. The second number is less than the first number. | 01-07-2016 |
20160004596 | DATA STORAGE DEVICE WITH IN-MEMORY PARITY CIRCUITRY - A data storage device includes a memory die. The memory die includes parity circuitry and a memory having a three-dimensional (3D) memory configuration. The memory includes a first block, a second block, and a third block. A method includes generating parity information based on first data associated with a first word line of the first block and further based on second data associated with a second word line of the second block. The parity information is generated by the parity circuitry. The method further includes writing the parity information to a third word line of the third block. | 01-07-2016 |
20160004464 | SYSTEM AND METHOD OF UPDATING METABLOCKS - A method includes, in a data storage device that includes a non-volatile memory having multiple memory dies, determining whether one or more metablocks are metablock update candidates based on relinking metrics corresponding to the one or more metablocks. Each memory die of the multiple memory dies includes multiple blocks of storage elements and metablocks are formed through linking of blocks from the multiple memory dies. The method also includes comparing a number of the metablock update candidates to a relinking pool threshold. The method further includes, in response to the number of the metablock update candidates satisfying the relinking pool threshold, updating the linking of the blocks of the metablock update candidates to form updated metablocks. | 01-07-2016 |
20150380096 | DYNAMIC ADJUSTMENT OF READ VOLTAGE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read. | 12-31-2015 |
20150371712 | DYNAMIC ADJUSTMENT OF READ VOLTAGE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read. | 12-24-2015 |
20150371703 | MEMORY CELLS USING MULTI-PASS PROGRAMMING - A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes using a four-pass programming technique to program a block of the non-volatile memory cells. | 12-24-2015 |
20150364198 | PARTIAL BLOCK ERASE FOR A THREE DIMENSIONAL (3D) MEMORY - A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string. | 12-17-2015 |
20150363342 | Storage Module and Method for Determining Ready/Busy Status of a Plurality of Memory Dies - A storage module and method are provided for determining ready/busy status of a plurality of memory dies. In one embodiment, a bus has a ready/busy line that is shared among the plurality of memory dies, and a time-division multiplex signal on the shared ready/busy line is used to communicate the ready/busy status of each of the memory dies. In another embodiment, each of the memory dies sends its ready/busy status to the storage controller using a different one of a plurality of data lines in the bus. In yet another embodiment, each of the memory dies sends a pulse across the ready/busy line with a different pulse width. To avoid collisions, each memory die waits a different number of clock cycles before attempting to send its pulse status after determining that the shared ready/busy line is in use. | 12-17-2015 |
20150363266 | PARITY SCHEME FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory. The non-volatile memory may include a first word line, a second word line, and a third word line. The second word line may be between the first word line and the third word line. The non-volatile memory may further include a first string and a second string. The first string may be adjacent to the second string. The data storage device may further include circuitry configured to store parity information at a fourth word line of the non-volatile memory. The parity information may correspond to a combination of first data associated with the first word line and the first string, second data associated with the first word line and the second string, third data associated with the third word line and the first string, and fourth data associated with the third word line and the second string. | 12-17-2015 |
20150363262 | ERROR CORRECTING CODE ADJUSTMENT FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller operationally coupled to the non-volatile memory. The controller is configured to access information stored at the non-volatile memory. The information includes a user data portion and an error correcting code (ECC) portion corresponding to the user data portion. The controller is further configured to modify the ECC portion in response to an error rate associated with the information exceeding a threshold. The one or more ECC parameters are modified without erasing or re-programming the user data portion. | 12-17-2015 |
20150357413 | Three Dimensional NAND Device Having a Wavy Charge Storage Layer - A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile. | 12-10-2015 |
20150348642 | Storage Device and Method for Performing a Self-Refresh Operation - A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device. | 12-03-2015 |
20150347325 | OBTAINING DIAGNOSTIC INFORMATION THROUGH HOST INTERFACES - Systems, methods, and apparatuses are provided to obtain diagnostic information from a storage device. A read command may be transmitted to a storage device, where the read command conforms to a block level storage protocol and is directed to an unused logical unit of storage memory included in the storage device, to an invalid logical block address, and/or to a mode page. The unused logical unit may be a predetermined logical unit of the storage memory that is not allocated by a file system. Diagnostic data may be received from the storage device in response to the read command. The diagnostic data may be information related to operation of the storage device and/or a component of the storage device. | 12-03-2015 |
20150347053 | Systems and Methods for Immediate Physical Erasure of Data Stored In a Memory System In Response to a User Command - Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further configured to perform one or more operations to render the memory system inoperable in response to the destruct command received from the host. | 12-03-2015 |
20150341038 | System and Method for Process and Temperature Calibration of Capacitor-Based Oscillators - A method and device for calibrating an oscillator and a temperature sensor in an electronic device are provided. A same temperature cycle, which includes at least two distinct temperatures, may be used to obtain data to calibrate both the oscillator and the temperature sensor. One of the distinct temperatures may comprise an ambient temperature, and a second distinct temperature may comprise a heated temperature greater than the ambient temperature. The electronic device (or a calibration device separate from the electronic device) may receive the readings from the oscillator and the temperature sensor at the two distinct temperatures in the same temperature cycle, and may determine an oscillator correction factor and a temperature sensor correction factor. | 11-26-2015 |
20150339195 | METHOD AND SYSTEM FOR SECURE SYSTEM RECOVERY - Apparatus and methods implemented therein are disclosed for recovery of information stored in non-volatile memory of embedded and external solid-state memory devices. The apparatus comprises a memory system. The memory system has a non-volatile memory and a memory controller. The memory controller is coupled to the non-volatile memory. The memory controller is also coupled to a memory interface. The memory controller searches the non-volatile memory to locate initialization information required to initialize the memory controller. The memory controller, in response to failing to successfully locate or execute the initialization information, is configured to transmit an indication via the memory interface. | 11-26-2015 |
20150339187 | SYSTEM AND METHOD OF STORING REDUNDANCY DATA - A data storage device includes a controller operatively coupled to a non-volatile memory. The non-volatile memory includes a plurality of blocks. When the controller is configured to operate according to a first mode, a portion of a first redundancy block of the plurality of blocks stores first redundancy data corresponding to a first group of multiple data portions. The multiple data portions stored in multiple blocks of the plurality of blocks. When the controller is configured to operate according to a second mode, the portion of the first redundancy block stores second redundancy data corresponding to a single block of the plurality of blocks. | 11-26-2015 |
20150339186 | ERROR CORRECTION USING MULTIPLE DATA SOURCES - A data storage device includes a memory and a controller. A method includes accessing data stored at the memory to generate a first logical page. The method further includes generating a second logical page. Generating the second logical page includes accessing parity information from the memory. The parity information is associated with the first logical page. The method further includes generating a third logical page. Generating the third logical page includes modifying a first value of the first logical page based on a second bit value of the second logical page. | 11-26-2015 |
20150325298 | MEMORY ACCESS TECHNIQUES FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION - A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes writing first data at a first physical page that is disposed within the memory at a first distance from a substrate of the memory. The first data is written at the first physical page using a first write technique. The method further includes writing second data at a second physical page that is disposed within the memory at a second distance from the substrate. The second distance is greater than the first distance. The second data is written at the second physical page using a second write technique that is different than the first write technique. | 11-12-2015 |
20150325297 | EFFICIENT REPROGRAMMING METHOD FOR TIGHTENING A THRESHOLD VOLTAGE DISTRIBUTION IN A MEMORY DEVICE - Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. During programming, a temporary lockout mode is provided for memory cells which pass a verify test. During a checkpoint program-verify iteration, all memory cells of a target data state are subject to the verify test. The memory cells in the temporary lockout mode are therefore subject to the verify test a second time. Memory cells that fail the verify test in the checkpoint program-verify iteration are programmed further. A normal or slow programming mode is used for a memory cell depending on whether it had reached the temporary lockout mode. Threshold voltage distributions are narrowed by reprogramming some of the memory cells. | 11-12-2015 |
20150325290 | DATA OPERATIONS IN NON-VOLATILE MEMORY - A method includes receiving an in-place refresh command to refresh data at a particular location in a non-volatile memory. The method also includes re-writing the data into the particular location of the non-volatile memory to refresh the data at the particular location in response to the in-place refresh command. | 11-12-2015 |
20150324251 | ERROR CORRECTING CODE TECHNIQUES FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION - A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes encoding first data to be stored at a first physical page. The first physical page is disposed within the memory at a first distance from a substrate of the memory, and the first data is encoded using a first encoding technique. The method further includes encoding second data to be stored at a second physical page. The second physical page is disposed within the memory at a second distance from the substrate that is greater than the first distance. The second data is encoded using a second encoding technique that is different than the first encoding technique. | 11-12-2015 |
20150324148 | PROCESSING SHAPED DATA - Systems and methods of processing shaped data to include selectively performing a modification operation. The modification operation may be performed in response to determining that shaped data satisfies one or more shaping adjustment criteria. Shaping of data may be discontinued to at least a portion of a memory based on a health metric for the portion satisfying a threshold. | 11-12-2015 |
20150324137 | Method and Computing Device for Using Both Volatile Memory and Non-Volatile Swap Memory to Pre-Load a Plurality of Applications - The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area. | 11-12-2015 |
20150324132 | Method and Computing Device for Fast Erase of Swap Memory - The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area. | 11-12-2015 |
20150324120 | Method and Computing Device for Controlling Bandwidth of Swap Operations - The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area. | 11-12-2015 |
20150324119 | Method and System for Improving Swap Performance - A method and system for improving swap performance are provided. In one embodiment, a computing device is provided with a volatile memory and a non-volatile memory, wherein the non-volatile memory has a first swap area with multi-level cell (MLC) memory and a second swap area with single-level cell (SLC) memory. One of the characteristics of SLC memory is that data is written more quickly in the SLC memory than the MLC memory. A determination is made whether the computing device is operating in normal mode or burst mode. If it is determined that the computing device is operating in normal mode, data is moved from the volatile memory to the first swap area during a swap operation. If it is determined that the computing device is operating in burst mode, data is moved from the volatile memory to the second swap area during a swap operation. | 11-12-2015 |
20150318380 | Thin Film Transistor - Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole. | 11-05-2015 |
20150318298 | TRENCH VERTICAL NAND AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench. | 11-05-2015 |
20150318297 | METHOD OF SELECTIVE FILLING OF MEMORY OPENINGS - A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes providing an opening having a different sidewall material exposed on a sidewall of the opening than a bottom material exposed on a bottom of the opening, selectively forming a sacrificial material on the bottom of the opening but not on the sidewall of the opening, selectively forming a first layer on the sidewall of the opening but not on the sacrificial material located on the bottom of the opening, and selectively removing the sacrificial material to expose the bottom material on the bottom of the opening such that the first layer remains on the sidewall of the opening. | 11-05-2015 |
20150318295 | VERTICAL FLOATING GATE NAND WITH OFFSET DUAL CONTROL GATES - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack. | 11-05-2015 |
20150318055 | System Method and Apparatus for Screening a Memory System - A system and method of writing data to a memory block includes receiving user data in a memory controller, the user data to be written to the memory block. The user data is first written to a buffer in the memory controller. A screening pattern is written to at least one screening column in the memory block and a first memory integrity test is performed. The first memory integrity test includes reading screening column data from the at least one screening column and comparing the screening column data read from the at least one screening column to the screening pattern. The user data is written to at least one user data column in the memory block when the screening column data read from the at least one screening column matches the screening pattern in the first memory integrity test. | 11-05-2015 |
20150311112 | Patterning Method For Low-K Inter-Metal Dielectrics And Associated Semiconductor Device - Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance. | 10-29-2015 |
20150303911 | ANALOG BREAK BEFORE MAKE SYSTEM, METHOD AND APPARATUS - A system and method of providing an analog make before break circuit includes a first transistor coupled in series with a second transistor, the first transistor being configured for conducting a high portion of an input signal, the second transistor being configured for conducting a low portion of the input signal. A third transistor is configured to interrupt a connection between the input signal and a first transistor input node, the third transistor having a third transistor threshold voltage between of about 90 and about 110 percent of a second transistor threshold voltage. A fourth transistor is configured to interrupt a connection between the input signal and a second transistor input node, the fourth transistor having a fourth transistor threshold voltage of between about 90 and about 110 percent of a first transistor threshold voltage. | 10-22-2015 |
20150301933 | Multi-Level Redundancy Code for Non-Volatile Memory Controller - In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set. | 10-22-2015 |
20150301907 | Storage Module and Method for Determining Whether to Back-Up a Previously-Written Lower Page of Data Before Writing an Upper Page of Data - A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module receives a command to write an upper page of data to memory cells that have already been programmed with a lower page of data. The storage module determines whether a command to protect the lower page of data was previously received. The storage module backs-up the lower page of data in another area of the memory before writing the upper page of data to the memory cells only if it is determined that the command to protect the lower page of data was previously received. The storage module then writes the upper page of data to the memory cells. | 10-22-2015 |
20150301885 | Neighboring Word Line Program Disturb Countermeasure For Charge-Trapping Memory - Techniques are provided for reading data from memory cells which are arranged along a common charge trapping layer. One example is in a 3D stacked non-volatile memory device. Memory cells on a word line layer WLLn can be disturbed by programming of memory cells on an adjacent word line layer WLLn+1, resulting in uncorrectable errors. In this case, the memory cells on WLLn can be read in a data recovery read operation which applies an elevated pass voltage to WLLn+1. The elevated pass voltage causes a decrease and narrowing of the threshold voltages on WLLn which facilitates reading. The data recovery read operation compensates for the lower threshold voltages of the cells by lowering the control gate voltage, raising the source voltage or adjusting a sensing period, demarcation level or pre-charge level in sensing circuitry. The elevated pass voltage can be stepped up in repeated read attempts until there are no uncorrectable errors or a limit is reached. | 10-22-2015 |
20150301763 | Storage Module and Method for Adaptive Burst Mode - A storage module and method for adaptive burst mode are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands from a host controller in communication with the storage module, store the plurality of write commands in a command queue in the storage module, and choose one of a plurality of burst modes in which to operate the memory based on how many write commands are stored in the command queue. | 10-22-2015 |
20150301755 | PROTECTION SCHEME WITH DUAL PROGRAMMING OF A MEMORY SYSTEM - A memory system or flash memory device may include a linking or grouping of blocks that are used for dual writing. In particular, meta-blocks in the memory may be linked in such a way that enables a data transfer to simultaneously occur in two meta-blocks. The dual versions of the programming may be used for error correction. If there is a failure or write error in one of the meta-blocks, then the data from the other meta-block may be used. If there is no failure then the secondary meta-block may be erased. | 10-22-2015 |
20150301754 | Storage Module and Method for Configuring the Storage Module with Memory Operation Parameters - A storage module and method for configuring the storage module with memory operation parameters are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a selection of one of a plurality of sets of memory operation parameters stored in the storage module and perform at least one of a read operation and a write operation on the memory in accordance with the selected set of memory operation parameters. | 10-22-2015 |
20150294721 | Memory Card - A memory card is provided comprising a plurality of electrical contacts, a controller, and a memory, where a housing encloses the controller and the memory and exposes the plurality of electrical contacts. In one embodiment, the memory card further comprises an extendible gripping portion movable between first and second positions, wherein the extendible gripping portion is more exposed from the housing in the second position than in the first position. In another embodiment, the end of the housing forms a notch shaped to mate with a mating removal tool. In yet another embodiment, the length of the memory card is less than about 32 mm and the width of the memory card is about 24 mm, and the memory card has a fingernail grip on the housing. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. | 10-15-2015 |
20150287733 | IN-SITU SUPPORT STRUCTURE FOR LINE COLLAPSE ROBUSTNESS IN MEMORY ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch. | 10-08-2015 |
20150287459 | Methods For Programming ReRAM Devices - A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed. | 10-08-2015 |
20150286919 | Memory Card - A memory card is provided comprising a plurality of electrical contacts, a controller, and a memory, where a housing encloses the controller and the memory and exposes the plurality of electrical contacts. In one embodiment, the memory card further comprises an extendible gripping portion movable between first and second positions, wherein the extendible gripping portion is more exposed from the housing in the second position than in the first position. In another embodiment, the end of the housing forms a notch shaped to mate with a mating removal tool. In yet another embodiment, the length of the memory card is less than about 32 mm and the width of the memory card is about 24 mm, and the memory card has a fingernail grip on the housing. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. | 10-08-2015 |
20150261613 | Storage Module and Method for Improving Boot Time During Block Binary Searches - A storage controller is configured to find a last-written page in a block in a memory by sending a command to the memory to read a page of data, receiving at least some of the data from that page, and analyzing the at least some of the data from that page to determine if that page is a written page. In one embodiment, the storage controller instructs the memory to read the page of data using a sense time that is shorter than a sense time used to read a page of data in response to a read request from a host controller. Additionally or alternatively, the amount of the data received by the storage controller can be less than the amount of data received when reading a page of data in response to a read request from a host controller. | 09-17-2015 |
20150255481 | Metal Replacement Process For Low Resistance Source Contacts In 3D NAND - A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path. | 09-10-2015 |
20150255166 | Compensating Source Side Resistance Versus Word Line - A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell. | 09-10-2015 |
20150254384 | Virtual Critical Path (VCP) System and Associated Methods - A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal. | 09-10-2015 |
20150234756 | Datapath Management in a Memory Controller - A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption. | 08-20-2015 |
20150234706 | ERROR DETECTION AND HANDLING FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method includes writing a first logical page to a physical page of the non-volatile memory. In response to a multistate error indication satisfying a threshold, the method further includes rewriting the first logical page at the non-volatile memory. The multistate error indication is determined based on the first logical page. | 08-20-2015 |
20150228351 | Self-Adjusting Regulation Current for Memory Array Source Line - To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level. | 08-13-2015 |
20150226614 | Reference Voltage Generator for Temperature Sensor with Trimming Capability at Two Temperatures - A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels. | 08-13-2015 |
20150223335 | PRINTED CIRCUIT BOARD WITH COEXTENSIVE ELECTRICAL CONNECTORS AND CONTACT PAD AREAS - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 08-06-2015 |
20150221391 | State-Dependent Lockout In Non-Volatile Memory - A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data. | 08-06-2015 |
20150221348 | Sense Amplifier With Efficient Use Of Data Latches - A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level. | 08-06-2015 |
20150220552 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150220551 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150220550 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150220268 | Storage Module and Host Device for Storage Module Defragmentation - A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided. | 08-06-2015 |
20150214235 | NON-VOLATILE STORAGE ELEMENT WITH SUSPENDED CHARGE STORAGE REGION - Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid. | 07-30-2015 |
20150213896 | Methods for Balancing Write Operations of SLC Blocks in Different Memory Areas and Apparatus Implementing the Same - Data is received at a computer memory to be programmed in single-level-cell mode. A stress level of a first section of the computer memory is determined. A stress level of a second section of the computer memory is determined. The stress levels of the first and second sections of the computer memory are compared to determine which one of the first and second sections is a less stressed single-level-cell mode section of the computer memory. The data received at the computer memory is programmed in the less stressed single-level-cell mode section of the computer memory. | 07-30-2015 |
20150213893 | Pattern Breaking in Multi-Die Write Management - A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length. | 07-30-2015 |
20150213844 | DIGITAL RAMP RATE CONTROL FOR CHARGE PUMPS - Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage. | 07-30-2015 |
20150212883 | ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE - Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches. | 07-30-2015 |
20150212878 | NON-BLOCKING COMMANDS - Methods, systems, and devices are provided that processes storage commands. Data may be read from a storage memory at a storage device based on a read command received at the storage device from a host. An error may be detected in the data read from the storage memory at the storage device. In response to the error, placeholder data may be transmitted from the storage device to the host without transmitting an indication that the read command failed or succeeded. Corrected data may be transmitted from the storage device to the host, where the host replaces the placeholder data with the corrected data. | 07-30-2015 |
20150212732 | Pattern Breaking in Multi-Die Write Management - A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length. | 07-30-2015 |
20150206824 | I/O PIN CAPACITANCE REDUCTION USING TSVS - Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance. | 07-23-2015 |
20150200019 | ERASE SPEED ADJUSTMENT FOR ENDURANCE OF NON-VOLATILE STORAGE - Techniques are disclosed herein for erasing non-volatile storage. The erase has two or more phases. The first phase includes erasing a group of non-volatile storage elements at a first speed until the group of non-volatile storage elements pass a first verify level. The second phase is performed after the group of non-volatile storage elements pass the first verify level. The second phase includes erasing the group of non-volatile storage elements at a second speed that is less than the first speed until the group of non-volatile storage elements pass a second verify level that is lower than the first verify level. Erasing at the first speed results in a fast erase without significant risk of over-erasing the storage elements. Erasing at the second speed during the second phase prevents or reduces over-erasure which could damage the storage elements. | 07-16-2015 |
20150200014 | Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory - A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements. | 07-16-2015 |
20150188523 | Input Receiver With Multiple Hysteresis Levels - An integrated circuit (“IC”) includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input voltages. This circuit may improve the input noise immunity of the external input signals and timing by allowing for a selection one of the plurality of levels depending on parameters of the input (e.g. noise level). | 07-02-2015 |
20150188491 | System and Method for Calibrating Capacitor-Based Oscillators in Crystal-less Devices - A method for calibrating an oscillator in an electronic device and an electronic device configured for calibration are provided. Multiple signals are sent to the electronic device from another electronic device, such as from a host device. With knowledge of the time interval between the multiple signals, the electronic device may calibrate the oscillator in the electronic device. For example, the electronic device may be a USB-compliant electronic device. The USB-compliant electronic device may receive Start of Frame (SoF) signals from a host device, which in one USB implementation is received at 1 mSec intervals. The USB-compliant electronic device may count the output of the oscillator between receipt of different SoF signals in order to determine the frequency of the oscillator at different oscillator settings. | 07-02-2015 |
20150187442 | REUSING PARTIAL BAD BLOCKS IN NAND MEMORY - A system handles bad blocks in block-based NAND memory by remapping wordlines that are unusable. Rather than eliminate usage of an entire block, the system may dynamically remap the block to exclude only the unusable wordlines. The partial blocks utilize portions of the memory with good wordlines and the portions of memory with bad wordlines are redirected to one or more replacement blocks. | 07-02-2015 |
20150187399 | PULSE MECHANISM FOR MEMORY CIRCUIT INTERRUPTION - In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described. | 07-02-2015 |
20150186270 | NON-VOLATILE MEMORY AND METHOD WITH ADAPTIVE LOGICAL GROUPS - A nonvolatile memory is organized into blocks as erase units and physical pages as read/write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages are further aggregated into ogical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller RAM. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams. | 07-02-2015 |
20150186259 | METHOD AND APPARATUS FOR STORING DATA IN NON-VOLATILE MEMORY - Apparatus and methods implemented therein are disclosed for storing data in flash memories. The apparatus comprises a flash memory having several physical blocks, a logical to virtual mapping table, a virtual to physical mapping table and a memory controller. The memory controller retrieves a virtual block address from the logical to virtual mapping table. The virtual block address corresponds to an entry in the virtual to physical mapping table. The entry in the virtual to physical mapping table contains a reference to a physical block. The memory controller uses the virtual block address to retrieve the reference to the physical block and stores data in the physical block. The memory controller copies the stored data from the physical block to a second physical block. The memory controller then replaces the reference to the physical block contained in the entry of the virtual to physical mapping table with a reference to the second physical block. | 07-02-2015 |
20150186074 | Storage Module and Method for Configuring Command Attributes - A storage module and method for configuring command attributes are provided. In one embodiment, a storage module is provided comprising a controller having hardware function blocks and further comprising a memory storing associations between command codes and command attributes for the hardware function blocks. The storage module receives a command that includes a command code and determines if the command code is stored in the memory. If the command code is stored in the memory, the storage module configures the hardware function blocks using the command attributes associated with command code and processes the command with the configured hardware function blocks. The associations are configurable after the storage module has been manufactured. This allows new or different associations to be defined after the storage module has been manufactured. | 07-02-2015 |
20150186068 | COMMAND QUEUING USING LINKED LIST QUEUES - A method, apparatus, and system may be provided for queuing storage commands. A command buffer may store storage commands for multiple command queues. Linked list controllers may control linked lists, where each one of the linked lists identifies the storage commands that are in a corresponding one of the command queues. The linked list storage memory may store next command pointers for the storage commands. A linked list element in any of the linked lists may include one of the storage commands stored in the command buffer and a corresponding one of the next command pointers stored in the linked list storage memory. | 07-02-2015 |
20150181413 | Mobile Device Peripheral - A mobile device peripheral is provided comprising a wireless memory sub-system configured for carrying out wireless data communications with a mobile device. The mobile device peripheral also has a battery configured to provide power to the wireless memory sub-system and a housing configured to hold the wireless memory sub-system and battery. The housing is further configured to physically attach the mobile device peripheral to the mobile device so that the mobile device peripheral and mobile device are carryable together as a single unit. The mobile device peripheral can take the form of a mobile device case or cover, for example. In another embodiment, the mobile device peripheral has a power splitter configured to split power received from a power connector to charge both the battery of the mobile device peripheral and the battery of the mobile device. | 06-25-2015 |
20150180474 | WIDE SUPPLY RANGE HIGH SPEED LOW-TO-HIGH LEVEL SHIFTER - A level shifter may include a first current source configured to source current to a node that pulls up an output voltage of the level shifter to a logic high level and a second current source configured to sink away current from the node to pull down the output voltage to a logic low level. When the output voltage at the node reaches the logic high voltage, the first current source may be deactivated while a latch connected to the node maintains the output voltage at the logic high level. Similarly, when the output voltage reaches the logic low voltage, the second current source may be deactivated while the latch maintains the output voltage at the logic low level. | 06-25-2015 |
20150179660 | Three Dimensional NAND Device with Channel Located on Three Sides of Lower Select Gate and Method of Making Thereof - A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode. | 06-25-2015 |
20150179284 | SYSTEM AND METHOD OF MANAGING TAGS ASSOCIATED WITH READ VOLTAGES - A data storage device includes a controller coupled to a non-volatile memory. The non-volatile memory is configured to store multiple tags that include a first tag and a second tag. The controller is configured to determine one or more candidate values associated with a candidate tag. The one or more candidate values may be determined based on an operation applied to the first tag and the second tag. The controller is further be configured to cause the non-volatile memory to remove the first tag or the second tag from the multiple tags. | 06-25-2015 |
20150179275 | ASYMMETRIC STATE DETECTION FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected. | 06-25-2015 |
20150179260 | SYSTEMS AND METHODS OF SHAPING DATA - A method of shaping data includes receiving data represented as a first set of bits, where each bit of the first set of bits corresponds to a logical value. A first write current to write a first logical value to a storage element is less than a second write current to write a second logical value to the storage element. The method also includes applying a shaping operation to generate a second set of bits, where a proportion of bits having the first logical value is larger for the second set of bits than for the first set of bits. The method also includes writing the second set of bits to the memory. | 06-25-2015 |
20150179254 | MITIGATING DISTURB EFFECTS FOR NON-VOLATILE MEMORY - A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold. | 06-25-2015 |
20150178310 | SYSTEMS AND METHODS OF STORING DATA ASSOCIATED WITH CONTENT OF A DATA STORAGE DEVICE - A method performed in a host device includes receiving an input based on a user-visible code associated with a data storage device. The user-visible code corresponds to an identifier of the data storage device. The method includes sending first data associated with the identifier to a server via a network and receiving, from the server at a first time, a copy of second data identifying content stored in the data storage device. The second data is stored in a network-based storage device associated with the server. The method includes displaying, via a user interface of the host device, an indication of the content of the data storage device to enable the content of the data storage device to be identified at the host device independently of whether the data storage device is coupled to the host device. | 06-25-2015 |
20150178197 | Addressing Auto address Assignment and Auto-Routing in NAND Memory Network - A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme. | 06-25-2015 |
20150178194 | SYSTEMS AND METHODS OF ADDRESS-AWARE GARBAGE COLLECTION - A method includes determining a first logical block address (LBA) range of a first set of data units of a first candidate block of the memory. The method also includes determining a second LBA range of a second set of data units of a relocation block of the memory. The method also includes determining that the first LBA range matches the second LBA range. The method further includes relocating first valid data of the first candidate block to the relocation block of the memory in response to determining that the first LBA range matches the second LBA range, where the first LBA range corresponds to multiple LBAs. | 06-25-2015 |
20150178189 | Systems and Methods for Scheduling Post-Write Read in Nonvolatile Memory - Post-write reading of data stored in a memory is performed only after a threshold amount of time has elapsed from the time the data was programmed. The threshold amount of time is at least the relaxation time of the memory cells, so that memory cells have reached stable states when post-write reading is performed. | 06-25-2015 |
20150178188 | Storage Module and Method for Re-Enabling Preloading of Data in the Storage Module - A storage module and method for re-enabling preloading of data in the storage module are disclosed. In one embodiment, a storage module is provided with a memory and a register. In response to receiving a register-setting command, the storage module sets a value in the register to enable preloading of data in the memory. The storage module then receives the data for storage in the memory. After the storage module has determined that all of the data has been received, the storage module changes the value in the register to disable further preloading of data. In response to receiving a register-resetting command, the storage module resets the value in the register to re-enable preloading of data even though the storage module already changed the value in the register to disable further preloading of data. | 06-25-2015 |
20150178151 | DATA STORAGE DEVICE DECODER AND METHOD OF OPERATION - A data storage device includes a nonvolatile memory and a controller having a decoder. The nonvolatile memory is operatively coupled to the controller. The nonvolatile memory is configured to store a set of bits. The decoder is configured to receive the set of bits from the memory. The decoder is further configured to perform a decoding operation using the set of bits based on a parity check matrix. The parity check matrix includes a block row. The block row has a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix within the block row by at least a threshold number of null sub-matrices of the block row. | 06-25-2015 |
20150178013 | SYSTEMS AND METHODS OF COMPRESSING DATA - A method includes, in response to a first write command corresponding to first data and a first context which is identifiable with a first identifier and to a second write command corresponding to second data and a second context identifiable with a second identifier, determining whether the first identifier of the first context matches the second identifier of the second context. The method also includes, if the first identifier of the first context is determined to match the second identifier of the second context, forming a compression group of data including the first data and the second data, and generating compressed data corresponding to the compression group of data. | 06-25-2015 |
20150177988 | SYSTEM AND METHOD OF IMPLEMENTING A TABLE STORAGE SUPPORT SCHEME - A data storage device may be configured to update a table used by a host device, such as a table stored at the data storage device. For, example, the data storage device may generate and store an updated version of a portion of the table. A storage location of the updated version of the portion may be tracked using a data structure that corresponds to a second version of the table. The second version of the table may be discarded or made accessible to the host device responsive to an indicator detected by the data storage device. | 06-25-2015 |
20150162909 | LOAD IMPEDANCE ADJUSTMENT FOR AN INTERFACE OF A DATA STORAGE DEVICE - A data storage device includes a signal source. A load is responsive to the signal source. A method includes adjusting an impedance of the load to reduce an impedance mismatch between the signal source and the load. | 06-11-2015 |
20150162825 | Dynamic Load Matching Charge Pump for Reduced Current Consumption - A charge pump is regulated based up its output level. The regulation circuitry adjusts the frequency of the pump's clock based on feedback from pump's output. The pump's clock signal is generated by an oscillator whose frequency depends on a reference voltage level. The reference voltage level is dependent upon a regulation signal. In an example, a transistor whose gate is controlled by the regulation level is part of a series of elements in voltage divider, where the reference value is taken from a node of the divider. | 06-11-2015 |
20150162088 | String Dependent Parameter Setup - In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone. | 06-11-2015 |
20150162087 | WRITE SCHEME FOR CHARGE TRAPPING MEMORY - In a charge trapping memory, data that would otherwise be likely to remain adjacent to unwritten word lines is written three times, along three immediately adjacent word lines. The middle copy is protected from charge migration on either side and is considered a safe copy for later reading. Dummy data may be programmed along a number of word lines to format a block for good data retention. | 06-11-2015 |
20150162086 | Systems and Methods for Partial Page Programming of Multi Level Cells - Multiple bits of data are programmed together to each cell of a segment of a word line while other segments of the same word line are unprogrammed. Subsequently, additional segments are similarly programmed. Data is read from a partially programmed word line (with a mix of programmed and unprogrammed segments) using a single reading scheme. | 06-11-2015 |
20150161044 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory device and a controller. Mapping circuitry is configured, in response to receiving data, to apply a one-to-many mapping to each group of multiple groups of bits in the received data to generate mapped data that includes multiple groups of mapped bits. Storage elements of the memory device are partitioned into multiple skip groups and the mapped bits of each group of mapped bits are interleaved across the skip groups such that different bits of a group of mapped bits are written into different skip groups. | 06-11-2015 |
20150160893 | Lower Page Only Host Burst Writes - In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage. | 06-11-2015 |
20150160866 | DYNAMIC INTERFACE CALIBRATION FOR A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. A method includes calibrating a first portion of the interface in response to a first bit transition from a first bit value to a second bit value of data to be sent via the interface. | 06-11-2015 |
20150160857 | Lower Page Only Host Burst Writes - In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage. | 06-11-2015 |
20150160706 | MULTIPLE POWER SUPPLY DELIVERY FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a host interface. A method includes supplying a first supply voltage to the host interface during a first mode of operation of the non-volatile memory. The method further includes supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of the non-volatile memory. | 06-11-2015 |
20150155156 | LOW PROFILE WIRE BONDED USB DEVICE - A low profile USB flash memory device, and methods of forming same, are disclosed. The USB flash memory device includes an integrated circuit memory portion and a USB connector. The memory portion and the USB connector may be integrally formed on the same substrate. The USB flash memory device includes a substrate on which is mounted one or more flash memory die, a controller die, passive components and an LED for indicating when the memory is being accessed. In contrast to prior art USB memory devices which used TSOP packages mounted on a printed circuit board, the semiconductor die of the present invention are affixed to the substrate and wire bonded in a SIP configuration. Omitting the encapsulated TSOP packages allows a reduction in the overall thickness of the USB flash memory device. | 06-04-2015 |
20150154132 | SYSTEM AND METHOD OF ARBITRATION ASSOCIATED WITH A MULTI-THREADED SYSTEM - A data storage device includes a controller coupled to a non-volatile memory via a data path element. The controller includes a first queue that includes a first set of requests and a second queue that includes a second set of requests. The controller further includes logic configured to assign a particular request from the first queue or from the second queue to have access to the data path element. When the logic is in a first mode, the logic selects a particular request is selected based on an arbitration scheme applied to the first queue and the second queue. When the logic is in a second mode, the logic selects a prioritized request from the first set of requests or the second set of requests independently of the arbitration scheme. | 06-04-2015 |
20150154118 | Storage Module and Method for Managing Logical-to-Physical Address Mapping - A storage module and method for managing logical-to-physical address mapping are disclosed. In one embodiment, a storage module is provided comprising a memory having a plurality of wordlines and a controller. The controller is configured to use a logical-to-physical address map to convert a logical address to a physical address of a wordline. A plurality of logical addresses in the map point to a single wordline, and the single wordline contains both data associated with the plurality of logical addresses and information about where to find each of the plurality of logical addresses in the single wordline . Storing the information about where to find each of the plurality of logical addresses in the wordline itself avoids the delay and complexity of using a larger logical-to-physical address map or multiple maps. | 06-04-2015 |
20150154112 | BATCH COMMAND TECHNIQUES FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method includes sending a memory command from the controller to the non-volatile memory. The memory command indicates multiple sense operations to be performed at a single plane of the non-volatile memory. | 06-04-2015 |
20150154111 | APPARATUS AND METHOD OF OFFLOADING PROCESSING FROM A DATA STORAGE DEVICE TO A HOST DEVICE - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes sending an instruction to a host device to cause the host device to perform one or more specified computations. The method further includes receiving a response from the host device. The response is based on execution of the one or more specified computations. | 06-04-2015 |
20150154109 | Memory System Controller Including a Multi-Resolution Internal Cache - A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions. | 06-04-2015 |
20150154108 | MULTI-DIE WRITE MANAGEMENT - A die assignment scheme assigns data in the order it is received, to multiple memory dies. Any busy dies are skipped until they become ready again so that the system does not wait for busy dies to become ready. Immediately sequential writes to the same die are prohibited so that reading speed is not impacted. | 06-04-2015 |
20150154069 | Adaptive Data Re-Compaction After Post-Write Read Verification Operations - Approaches are presented for adaptively re-compacting data when errors are found during a post-write verify in a non-volatile memory system, such as flash NAND memory. In one example, user data along with corresponding parity data is written into a block of non-volatile memory. After writing in the user data, but prior to writing the corresponding parity data, the user data is checked. For any word lines that fail this post-write verify, the parity data for the block is adjusted to remove the contribution of any failed word lines before this modified parity data is written into the block. The data corresponding to the failed word lines can then be written elsewhere in the memory system. | 06-04-2015 |
20150149694 | Adaptive Context Disbursement for Improved Performance in Non-Volatile Memory Systems - A controller circuit for a non-volatile memory of one or more memory circuits is described. The controller is connectable by a port with the memory circuits through a bus structure and can operate the memory circuits according to one or more threads. The controller includes a command processing section to issue high level commands for execution in the memory circuits and a memory circuit interface module to issue in sequence by the port to the memory circuits a series of instruction derived from the high level commands. A queue manager on the controller derives the series of instructions from the high level commands. When deriving a series of instruction from a set of high level data access commands, the queue manager can modify the timing for the issuance to the memory circuit interface module of memory circuit check status instructions based upon feedback from the memory circuit interface module and the state of earlier instruction in the series. | 05-28-2015 |
20150149693 | Targeted Copy of Data Relocation - In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable. Subsequent reads of the relocated data directed to binary cache. | 05-28-2015 |
20150143030 | Update Block Programming Order - Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time. | 05-21-2015 |
20150143029 | DYNAMIC LOGICAL GROUPS FOR MAPPING FLASH MEMORY - A memory system or flash card may include a controller that indexes a global address table (GAT) with a single data structure that addresses both large and small chunks of data. The GAT may include both large logical groups and smaller logical groups for optimizing write amplification. The addressing space may be organized with a large logical group size for sequential data. For fragmented data, the GAT may reference an additional GAT page or additional GAT chunk that has a smaller logical group size. | 05-21-2015 |
20150143026 | TEMPERATURE BASED FLASH MEMORY SYSTEM MAINTENANCE - A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed. | 05-21-2015 |
20150143025 | Update Block Programming Order - Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time. | 05-21-2015 |
20150143023 | Detecting Access Sequences for Data Compression on Non-Volatile Memory Devices - Techniques are presented to allow non-volatile memory system to operate more efficiently by determining ranges of logical addresses that a host typically accesses as together. For example, the system's controller can determine that the host always, or most always, writes or reads a contiguous set of logical addresses as a single unit. The controller can exploit this information by operating on these ranges as single a unit for data operations it performs. To take one example, the memory system can treat such ranges as single units for on-system data compression prior to writing the data to non-volatile memory, thereby increasing the efficiency of such data compression. | 05-21-2015 |
20150135039 | BLOCK CLOSURE TECHNIQUES FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line. | 05-14-2015 |
20150135023 | DATA RETENTION DETECTION TECHNIQUES FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method includes writing an indication of a first error rate of a first set of bits to the non-volatile memory. The first set of bits is sensed from a word line of the non-volatile memory. The word line is sensed to generate a second set of bits in response to a first power-on event being initiated at the data storage device after writing the indication of the first error rate to the non-volatile memory. The method further includes setting a data retention flag in response to a difference between the first error rate and a second error rate associated with the second set of bits satisfying a threshold. | 05-14-2015 |
20150134918 | SINGLE INPUT/OUTPUT CELL WITH MULTIPLE BOND PADS AND/OR TRANSMITTERS - A storage module may include a controller configured to communicate with a memory having a plurality of memory dies. The controller may include a plurality of bond pads, where each bond pad is configured to communicate a same type of memory signal, and where each bond pad is electrically connected to at least one but less than all of the plurality of memory dies. A core of the controller may identify a memory die that it wants to communicate a memory signal and an associated bond pad with which to communicate the memory signal. | 05-14-2015 |
20150134885 | Identification and Operation of Sub-Prime Blocks in Nonvolatile Memory - In a block-erasable nonvolatile memory array, blocks are categorized as bad blocks, prime blocks, and sub-prime blocks. Sub-prime blocks are identified from their proximity to bad blocks or from testing. Sub-prime blocks are configured for limited operation (e.g. only storing non-critical data, or data copied elsewhere, or using some additional or enhanced redundancy scheme). | 05-14-2015 |
20150134857 | System and Method for I/O Optimization in a Multi-Queued Environment - A system and method for I/O optimization in a multi-queued environment are provided. In one embodiment, a host is provided that sorts commands into a plurality of queues, wherein a command is sorted based on its data characteristic. The host receives a read request from a storage module for commands in the plurality of queues and provides the storage module with the requested commands. In another embodiment, a storage module is provided that processes commands from a host based on the data characteristic of the queue that stored the command on the host. In another embodiment, a storage module sorts command completions into a plurality of queues, wherein a command completion is sorted based on its resulting status code. | 05-14-2015 |
20150131380 | ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY - When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines. | 05-14-2015 |
20150127882 | READ OPERATION PRIOR TO RETRIEVAL OF SCATTER GATHER LIST - A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a read command from a host device. The read command includes a starting logical block address (LBA) of the non-volatile memory, a number of logical blocks to be read (NLB), and a pointer to a scatter gather list (SGL). The controller is also configured to instruct the non-volatile memory to read a plurality of logical blocks from the non-volatile memory based on the starting LBA and the NLB. The controller is further configured to, after instructing the non-volatile memory to read the plurality of logical blocks, retrieve the SGL based on the pointer. The controller is configured to transfer a subset of the plurality of logical blocks identified by the SGL to the host device. | 05-07-2015 |
20150124527 | Detecting Programmed Word Lines Based On NAND String Current - A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block. | 05-07-2015 |
20150123191 | Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation - High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction. | 05-07-2015 |
20150121157 | Selection of Data for Redundancy Calculation By Likely Error Rate - Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. | 04-30-2015 |
20150121156 | Block Structure Profiling in Three Dimensional Memory - Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes. | 04-30-2015 |
20150120986 | DELAYED AUTOMATION TO MAXIMIZE THE UTILIZATION OF READ AND WRITE CACHE - A storage module may include a non-volatile memory module and a controller that communicates with the non-volatile memory module using a communications bus. In response to receipt of a host command, the controller may generate one or more sets of context commands for communication of data on the communications bus between the controller and an area of memory. The controller may execute the sets of context commands in a cache sequence. During execution of the context commands in the cache sequence, the controller may determine an opportunity window that occurs after execution of a context command of a prior set and before execution of a context command of a current set, during which the controller may utilize the communications bus. | 04-30-2015 |
20150117114 | WORD LINE COUPLING FOR DEEP PROGRAM-VERIFY, ERASE-VERIFY AND READ - In a non-volatile storage system, a reduced voltage is provided on a selected word line during a sensing operation, using down coupling from one or more adjacent word lines. Voltages of one or more adjacent word lines of a selected word line are driven down while a voltage of the selected word line is floated. Capacitive coupling from the one or more adjacent word lines to the selected word line reduces the voltage of the selected word line. The capacitive coupling can be provided during a read, a program-verify test or an erase-verify test. The erase-verify test can be performed on cells of even-numbered word lines while capacitive coupling is provided by odd-numbered word lines, or on cells of odd-numbered word lines while capacitive coupling is provided by even-numbered word lines. Voltages of non-adjacent word lines can be provided at fixed, pass voltage levels. | 04-30-2015 |
20150117099 | Selection of Data for Redundancy Calculation By Likely Error Rate - Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low. | 04-30-2015 |
20150117098 | POWER DROP PROTECTION FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory. A method includes programming a first page at a word line of the non-volatile memory. While programming a second page at the word line, first storage elements of the word line are selectively programmed in response to a power drop at the data storage device to increase a state separation that separates data values of the first page. | 04-30-2015 |
20150103595 | BIT LINE AND COMPARE VOLTAGE MODULATION FOR SENSING NONVOLATILE STORAGE ELEMENTS - In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed. | 04-16-2015 |
20150098271 | SYSTEM AND METHOD OF STORING DATA IN A DATA STORAGE DEVICE - A method that may be performed in a data storage device includes selecting a writing order for data to be written to a set of word lines of a block of a non-volatile memory. The data is organized in pages that are ordered according to a logical page address order. The writing order is selected from at least a first order or a second order that is distinct from the first order. Stored data in the non-volatile memory written according to the first order has logical page addresses that decrease with increasing values of word line physical addresses. The method also includes writing the data to the set of word lines according to the selected writing order and storing a flag value that indicates the selected writing order. | 04-09-2015 |
20150092496 | Dynamic Bit Line Bias For Programming Non-Volatile Memory - A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level. | 04-02-2015 |
20150092493 | Pseudo Block Operation Mode In 3D NAND - A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode. | 04-02-2015 |
20150091637 | Amplitude Modulation for Pass Gate to Improve Charge Pump Efficiency - Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section. | 04-02-2015 |
20150089325 | METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit. | 03-26-2015 |
20150089324 | METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit. | 03-26-2015 |
20150085575 | Multi-Word Line Erratic Programming Detection - Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members. | 03-26-2015 |
20150085573 | UPDATING READ VOLTAGES - A method performed at a data storage device includes adjusting a first read voltage and a second read voltage to form sets of read voltages. First representations of data are read from a logical page in the non-volatile memory according to the sets of read voltages. The first representations of the data correspond to multiple values of the first read voltage and the second read voltage. The first representations of the data are stored in a memory and second representations of the data are generated based on the first representations. A value of the first read voltage is selected based on syndrome weights corresponding to the second representations. | 03-26-2015 |
20150085571 | UPDATING READ VOLTAGES - A data storage device includes a controller that is configured to determine a first read voltage for a first page of a non-volatile memory (e.g., a lower page of a Multi-Level Cell flash memory device). The controller is also configured to determine a second read voltage for a second page (e.g., an upper page) of the non-volatile memory by applying an offset value to the first read voltage. The controller is also configured to store data identifying the first read voltage and the second read voltage. | 03-26-2015 |
20150082325 | APPARATUSES AND METHODS FOR GENERATING AND TRACING EVENT CODES - Apparatuses and methods implemented therein are disclosed for generating event codes and time stamped events from the generated event codes. In one embodiment the apparatus comprises a register, a counter, a timestamp fraction generator and an event code generator. The register is configured to receive a one of a set of asynchronous events. The counter is configured to receive a clock signal and generate periodic events of a configurable periodicity. The timestamp fraction generator is coupled to the register and generates a timestamp fraction in response to receiving an asynchronous event by obtaining a count from the counter at substantially the same time that the event is received. Finally, the event code generator generates an event code from the timestamp fraction and an identifier corresponding to the event. | 03-19-2015 |
20150082313 | APPARATUSES AND METHODS FOR GENERATING EVENT CODES INCLUDING EVENT SOURCE - Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event. | 03-19-2015 |
20150082120 | Selective In-Situ Retouching of Data in Nonvolatile Memory - In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge. | 03-19-2015 |
20150081952 | APPARATUS AND METHOD OF USING DUMMY DATA WHILE STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150081949 | APPARATUS AND METHOD OF USING DUMMY DATA WHILE STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150079765 | HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION - A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion. | 03-19-2015 |
20150079743 | METHODS OF FABRICATING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A method of fabricating a memory device, such as a three-dimensional NAND string, includes forming a trench through a stack of alternating first and second material layers to expose a source region of a semiconductor channel, partially filling the trench with a protective material, removing at least a portion of the alternating second material layers to form recesses between the first material layers, forming a conductive material in the recesses to form control gate electrodes for a memory device, depositing an insulating material over the sidewalls and bottom of the trench, etching through the insulating material and the protective material to expose the semiconductor channel at the trench bottom while leaving the insulating material on the trench sidewalls, and filling the trench with a source line that electrically contacts the source region while the insulating material is between the source line and the control gate electrodes along the trench sidewalls. | 03-19-2015 |