Renesas Electronics Corporation Patent applications |
Patent application number | Title | Published |
20160141882 | POWER TRANSMISSION DEVICE, WIRELESS POWER FEEDING SYSTEM, AND CONTROL METHOD - The present power transmission device performs a power transmission process for transmitting power in a wireless manner through electromagnetic field resonance coupling using a resonance circuit. In a case where a resonance frequency of the resonance circuit set to be the same as a frequency of a power transmission signal which is output as transmission power is deviated during transmission of the power, the present power transmission device detects a direction in which the resonance frequency is deviated and controls the power transmission process on the basis of a detection result thereof. Consequently, it is possible to determine not only whether or not a foreign substance is present in a power transmission region but also determines whether or not the foreign substance influences wireless power transmission with high accuracy, and thus reliability of the wireless power transmission system can be improved. | 05-19-2016 |
20160141396 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy. | 05-19-2016 |
20160141289 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET. | 05-19-2016 |
20160134250 | SEMICONDUCTOR MEMORY WITH THRESHOLD CURRENT SETTING CIRCUIT - A semiconductor device includes a first trans-impedance amplifier, a second trans-impedance amplifier, a peak hold circuit, a comparator and a threshold current setting circuit. The first trans-impedance amplifier converts a first current signal generated by a first photodiode, into which an optical signal is input, into a first voltage signal. The second trans-impedance amplifier converts a second current signal generated by a second photodiode, to which an optical signal is blocked, into a second voltage signal. The peak hold circuit holds the peak value of the first voltage signal. The comparator outputs a pulse on the basis of the first and second voltage signals. The threshold current setting circuit draws out a threshold current. | 05-12-2016 |
20160133715 | SEMICONDUCTOR DEVICE - The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved. | 05-12-2016 |
20160133315 | SEMICONDUCTOR DEVICE - A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. | 05-12-2016 |
20160126345 | Semiconductor device and method for manufacturing the same - A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. | 05-05-2016 |
20160126100 | SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING CONTACT AT CURVED PORTION OF EQUIPOTENTIAL RING ELECTRODE AND METHOD OF MANUFACTURING THE SAME - A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film. | 05-05-2016 |
20160118476 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE WITH SILICON LAYER CONTAINING CARBON - A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced. | 04-28-2016 |
20160118437 | MANUFACTURING METHOD OF BACK ILLUMINATION CMOS IMAGE SENSOR DEVICE USING WAFER BONDING - Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment. | 04-28-2016 |
20160112034 | CLOCK CORRECTION CIRCUIT AND CLOCK CORRECTION METHOD - An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock. | 04-21-2016 |
20160111357 | SEMICONDUCTOR DEVICE - A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided. | 04-21-2016 |
20160109915 | SEMICONDUCTOR DEVICE HAVING IDENTIFICATION INFORMATION GENERATING FUNCTION AND IDENTIFICATION INFORMATION GENERATION METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state. | 04-21-2016 |
20160105130 | SEMICONDUCTOR DEVICE AND INVERTER SYSTEM - A semiconductor device includes first and second resistor groups, first and second switch groups, a register, and an amplifier. The first resistor group includes plural first resistors connected in series between a first terminal and an output of the amplifier. The first switch group includes plural first switches. Each of the first switches is connected between a corresponding one of the connection point between the first resistors and the inverting input terminal of the amplifier. The second resistor group includes plural second resistors connected in series between a second terminal of the amplifier and a reference voltage source. The second switch group includes plural second switches. Each of the second switches is connected between a corresponding one of the connection point between the second resistors and a positive input terminal of the amplifier. The register selects each of first and second switches. | 04-14-2016 |
20160104516 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device | 04-14-2016 |
20160099374 | SEMICONDUCTOR DEVICE - A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region. The electric field shield film is positioned below the wiring, and has a cutout portion in an overlapping region which overlaps the wiring. By forming the cutout portion, end portions of the electric field shield film is arranged to be shifted. Therefore, formation of a deep concave portion which is based on a concave portion on the silicon oxide film and a step of the electric field shield film over the entire width of the wiring can be prevented, and the disconnection of the wiring can be prevented. | 04-07-2016 |
20160099251 | SEMICONDUCTOR DEVICE - An insulating film, which is sandwiched between a gate electrode formed on an SOI layer constituting an SOI substrate and an epitaxial layer formed on the SOI layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element. | 04-07-2016 |
20160099051 | RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE DEVICE - A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode. | 04-07-2016 |
20160098968 | DIGITAL-TO-ANALOG-CONVERSION CIRCUIT AND DATA DRIVER FOR DISPLAY DEVICE - DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2̂n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A−1+2̂n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A−4+2̂n) and (A+2̂n), and an at most {−4+2̂(n−2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {−3+2̂(n−2)} reference voltages that are other than the four number of reference voltages from the {1+2̂(n−2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2̂(n−2). | 04-07-2016 |
20160094239 | SEMICONDUCTOR DEVICE - A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits. | 03-31-2016 |
20160094027 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor. | 03-31-2016 |
20160093716 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished. | 03-31-2016 |
20160093557 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip. | 03-31-2016 |
20160093555 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member. | 03-31-2016 |
20160087729 | PHOTOCOUPLER WITH PROTRUSION - A photocoupler comprises an input side lead frame; an output side lead frame disposed facing the input side lead frame with a gap therebetween; a light emitting device mounted on a face of the input side lead frame facing the output side lead frame side; a light receiving device mounted on a face of the output side lead frame facing the input side lead frame side, opposite to and having a gap with the light emitting device; and a protrusion disposed on at least a part of an area around the light receiving device on the output side lead frame and being formed of conductive bonding wire or a bump, protruding to the input side lead frame side. | 03-24-2016 |
20160087626 | POWER CONTROL CIRCUIT - A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits. | 03-24-2016 |
20160087622 | SEMICONDUCTOR DEVICE - The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same. | 03-24-2016 |
20160087612 | SEMICONDUCTOR DEVICE - If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit | 03-24-2016 |
20160087069 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an SOI substrate and a MISFET formed on the SOI substrate. The SOI substrate has a base substrate, a ground plane region formed on the base substrate, a BOX layer formed on the ground plane region and an SOI layer formed on the BOX layer. The base substrate is made of silicon and the ground plane region includes a semiconductor region made of silicon carbide. | 03-24-2016 |
20160086961 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film. | 03-24-2016 |
20160086939 | SEMICONDUCTOR DEVICE - A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions. | 03-24-2016 |
20160085596 | MULTI-CPU SYSTEM AND MULTI-CPU SYSTEM SCALING METHOD - In an asymmetric multi-CPU system on which a plurality of type of CPUs with different data processing performance and power consumption are mounted in groups for each type, a plurality of forms of combination of the types and numbers of CPUs are defined in such a way that the maximum numbers of the overall data processing and power consumption very by stages. Then, the system performs a control of allocation of the data processing to the CPU identified by the form selected from the definition information according to the data processing environment, in order to reduce unnecessary power consumption according to the data processing environment, such as data processing load, and to easily achieve the required data processing performance. | 03-24-2016 |
20160079804 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD OF THE SAME - The present invention is directed to solve a problem that, in the case where NFC and power supply operation of wireless power supply or the like repeat in a time division manner, the count value of a charge timer is reset to an initial value and a charge timer erroneously operates during an NFC period. A charge output terminal charges a battery using DC output voltage. A voltage detecting circuit detects reach of battery voltage to a predetermined level, generates a control signal, and generates a level determination signal discriminating an NFC period and a wireless power supply period by detection of the level of a DC input voltage of an input terminal. During execution of operation of counting charge time of the battery by the charge timer, the voltage detecting circuit controls the charge timer by the control signal in the NFC period, and the charge timer holds the count values of the counting operation. | 03-17-2016 |
20160079409 | SEMICONDUCTOR DEVICE - A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In | 03-17-2016 |
20160079352 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage. | 03-17-2016 |
20160079294 | IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall. | 03-17-2016 |
20160079231 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region. | 03-17-2016 |
20160079186 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - There is provided a technology by which the position of 1 pin in a tabless package can be recognized easily. The rear surfaces of plural leads are exposed on a rear surface of a resin-sealed body which seals a semiconductor chip etc., a image recognition area is further provided adjacent to 1 pin (lead with index 1), and a rear surface of an identification mark is exposed from the rear surface of the resin-sealed body of the image recognition area. This identification mark is made of the same conductive member as the plural leads. | 03-17-2016 |
20160079160 | SEMICONDUCTOR DEVICE - The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side. | 03-17-2016 |
20160077909 | WATCHDOG CIRCUIT, POWER IC AND WATCHDOG MONITOR SYSTEM - A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation. | 03-17-2016 |
20160072621 | SEMICONDUCTOR DEVICE - In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis. | 03-10-2016 |
20160071858 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data. | 03-10-2016 |
20160071804 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P | 03-10-2016 |
20160071769 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE DEVICE, AND LIQUID CRYSTAL DISPLAY - In order to shield the light incident from the chip side surface or chip rear surface of a semiconductor chip that forms an LCD driver, a light-shielding film is formed over the chip side surface and chip rear surface of the semiconductor chip itself, not using a light-shielding tape that is a component separate from the semiconductor chip. Accordingly, the light-shielding tape as a separate component is not used, and hence the trouble that the light-shielding tape may protrude from the surface of a glass substrate whose thickness has been made small can be solved. As a result, the thinning of a liquid crystal display, and the subsequent thinning of the mobile phone in which the liquid crystal display is mounted can be promoted. | 03-10-2016 |
20160065074 | DC-DC CONVERTER AND CONTROL METHOD FOR THE SAME - A DC-DC converter according to the present invention includes a power supply control circuit—that generates pulse signals, an output transistor that is controlled to be turned on and off based on the pulse signal, a rectification transistor—that is controlled to be turned on and off based on a control signal, a coil provided between a node between the output transistor and the rectification transistor, and an external output terminal, a comparator that compares a voltage of the node—with a reference voltage, a first control circuit that generates a control signal based on a comparison result of the comparator, and a second control circuit that generates the control signal based on a backward-current detection timing and a reference timing. | 03-03-2016 |
20160065070 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source | 03-03-2016 |
20160064777 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area. | 03-03-2016 |
20160064654 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. A semiconductor device has a conductive film formed above a semiconductor substrate, a first ferromagnetic film formed over the conductive film, an insulation film formed over the first ferromagnetic film, and a second ferromagnetic film formed over the insulation film. The first ferromagnetic film, the insulation film, and the second ferromagnetic film form a tunnel magnetoresistive effect element. The conductive film is formed of a metal nitride. The first ferromagnetic film contains cobalt, iron, and boron. The insulation film contains magnesium oxide. | 03-03-2016 |
20160064559 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n | 03-03-2016 |
20160064538 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity. | 03-03-2016 |
20160064533 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n | 03-03-2016 |
20160064507 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a memory cell equipped with a control gate electrode and a memory gate electrode adjacent to each other via a charge storage layer and having improved performance. | 03-03-2016 |
20160064450 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a semiconductor device incorporating a CMOS image sensor, dangling bonds existing at the interface between a semiconductor substrate and an insulating film formed over the semiconductor substrate are selectively terminated with hydrogen. | 03-03-2016 |
20160064402 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element. | 03-03-2016 |
20160064397 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, using a control gate electrode and a memory gate electrode which are formed over a semiconductor substrate as a mask, n-type impurity ions are implanted from a direction perpendicular to a main surface of the semiconductor substrate. Then, using the control gate electrode, the memory gate electrode, and first and second sidewall spacers as a mask, other n-type impurity ions are implanted from a direction inclined relative to the direction perpendicular to the main surface of the semiconductor substrate. | 03-03-2016 |
20160064389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode. | 03-03-2016 |
20160064346 | SEMICONDUCTOR DEVICE - This invention provides a semiconductor device with improved reliability. A pad includes a slit portion formed so as to pass through the pad, and also includes a bonding portion positioned inside the slit portion in plan view, and an edge portion positioned outside the slit portion in plan view. In plan view, a via encloses the slit portion and is in contact with the bonding portion of the pad and the edge portion of the pad. | 03-03-2016 |
20160064343 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved. | 03-03-2016 |
20160064312 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device that can achieve downsizing of the semiconductor device. Convex portions are pressed against side surfaces other than one side surface of one chip mounting portion, thereby fixing the chip mounting portion without forming a convex portion corresponding to the one side surface of the chip mounting portion. Likewise, convex portions are pressed against side surfaces other than one side surface of the other chip mounting portion, thereby fixing the other chip mounting portion without forming a convex portion corresponding to the one side surface of the other chip mounting portion. | 03-03-2016 |
20160064226 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Improvements are achieved in the properties of a semiconductor device including a MISFET and a nonvolatile memory. Over a gate electrode included in the MISFET and a control gate electrode and a memory gate electrode each included in a memory cell, a stress application film is formed of a silicon nitride film. Then, by removing the silicon nitride film from over the control gate electrode and the memory gate electrode, an opening is formed over the control gate electrode and the memory gate electrode. Then, in a state where the opening is formed in the silicon nitride film, heat treatment is performed to apply a stress to the MISFET. By thus removing the stress application film (silicon nitride film) from over the memory cell, it is possible to avoid the degradation of the properties of the memory cell due to H (hydrogen) in the silicon nitride film. | 03-03-2016 |
20160064063 | SEMICONDUCTOR DEVICE - A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors. | 03-03-2016 |
20160062812 | SELF DIAGNOSIS METHOD, COMPILE APPARATUS AND COMPILER - The execution time of a self diagnosis program is reduced. A compiler apparatus includes: a specify unit that specifies, out of a plurality of resources included in a diagnosis target apparatus, a use resource group being a set of resources used by an instruction string included in an object program executed on the diagnosis target apparatus; a determine unit that determines, in accordance with the specified use resource group, a target resource group being a set of resources to be targets of a self diagnosis in the diagnosis target apparatus; and an output unit that outputs, for causing the self diagnosis on the determined target resource group to be executed in the diagnosis target apparatus, information based on the target resource group to the diagnosis target apparatus. | 03-03-2016 |
20160059853 | CONTROL SYSTEM, RELAY DEVICE AND CONTROL METHOD - A control system | 03-03-2016 |
20160056952 | SEMICONDUCTOR DEVICE, RADIO COMMUNICATION TERMINAL, AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit. | 02-25-2016 |
20160056850 | RECEIVER, COMMUNICATION DEVICE, AND COMMUNICATION METHOD - To provide a receiver, a communication device, and a communication method capable of restoring a signal transmitted via a non-contact transmission channel with high accuracy. A communication device has a transmission circuit that converts an input signal into a pulse, a non-contact transmission channel that has a primary side coil and a secondary side coil and transmits the pulse from the transmission circuit in a non-contact manner, a restoration circuit that restores the input signal on the basis of a reception signal corresponding to the pulse transmitted via the non-contact transmission channel, an initialization unit that initializes an output of the non-contact transmission channel, and an initialization control unit that outputs a control signal of controlling the initialization unit on the basis of the reception signal corresponding to the pulse received via the non-contact transmission channel. | 02-25-2016 |
20160056812 | CLOCK GENERATION CIRCUIT, DISPLAY DEVICE DRIVE CIRCUIT, AND CONTROL METHOD OF CLOCK GENERATION CIRCUIT - A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state. | 02-25-2016 |
20160056722 | DC-DC CONVERTER - A DC-DC converter includes a first switching element and a second switching element; a pulse signal generating circuit which generates a pulse signal used to control on/off periods of the switching elements; a limiting circuit which generates a minimum pulse width signal; a selector configured to select one of the pulse signal and the minimum pulse width signal, and a driver circuit switches the first and second switching element and a reverse current detecting circuit detects a reverse current. The driver circuit controls the first or second switching element, when the reverse current is detected. The selector selects the pulse signal when the reverse current is not detected, and selects the minimum pulse width signal when the reverse current is detected. | 02-25-2016 |
20160056289 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. | 02-25-2016 |
20160056274 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased. | 02-25-2016 |
20160056254 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE - A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate ( | 02-25-2016 |
20160056233 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film. | 02-25-2016 |
20160056154 | SEMICONDUCTOR DEVICE - The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation. | 02-25-2016 |
20160056145 | SEMICONDUCTOR DEVICE - Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. | 02-25-2016 |
20160056124 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. | 02-25-2016 |
20160056115 | OPTICAL SEMICONDUCTOR DEVICE - A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. | 02-25-2016 |
20160055047 | PROCESSOR SYSTEM, ENGINE CONTROL SYSTEM AND CONTROL METHOD - A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system. | 02-25-2016 |
20160055009 | INFORMATION PROCESSING DEVICE, PERIPHERAL DEVICE CONTROL METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING FILTER DRIVER - In an information processing device, if the power state of a peripheral device changed by a class driver is the low-power state, in which the peripheral device consumes less power than in its normal state but its operation is limited, a filter driver below the class driver suspends controlling the peripheral device in accordance with a control request from an application program without passing through the class driver until the power state of the peripheral device returns to the normal state. | 02-25-2016 |
20160054521 | OPTICAL SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING THE SAME - Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region. | 02-25-2016 |
20160049947 | SPREAD SPECTRUM CLOCK GENERATOR - A spread spectrum clock generator includes: a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal; a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal; a delta-sigma modulator that receives a waveform signal for controlling spreading of a spectrum of the output clock signal, and outputs bits larger than 1 bit based on the waveform signal; a control circuit that controls a multiplication number according to an output signal of the delta-signal modulator; and a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit. | 02-18-2016 |
20160049466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased. | 02-18-2016 |
20160049415 | SEMICONDUCTOR DEVICE - In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be superimposed on a dummy element formation region in a two-dimensional view. In a first interlayer insulating film and a second interlayer insulating film covering the memory cell transistor, a contact plug is formed to penetrate the first interlayer insulating film and a via is formed to penetrate a second interlayer insulating film. | 02-18-2016 |
20160049395 | SEMICONDUCTOR DEVICE - An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured. | 02-18-2016 |
20160049368 | SEMICONDUCTOR DEVICE - To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed. | 02-18-2016 |
20160049315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals. | 02-18-2016 |
20160043811 | PHOTOCOUPLING DEVICE MANUFACTURING METHOD, PHOTOCOUPLING DEVICE, AND POWER CONVERSION SYSTEM - The alignment accuracy between light emitting elements, light receiving elements, and an insulating film is improved. A photocoupling device manufacturing method includes preparing a first lead frame having a first frame part supporting light receiving elements and a second lead frame having a second frame part supporting light emitting elements. The method also includes superposing the first and the second lead frame such that the light receiving elements and the light emitting elements mutually oppose via a first light-transmissive resin covering the light receiving elements, a second light-transmissive resin covering the light emitting elements, and an insulating film sheet positioned between the first and the second light-transmissive resin. The insulating film sheet includes body parts positioned between the light receiving elements and the light emitting elements, joining parts joined to the body parts, and a third frame part fixed between the first and the second frame part. | 02-11-2016 |
20160043721 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA TRANSMITTING AND RECEIVING CIRCUITS - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data. | 02-11-2016 |
20160043639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a voltage hold circuit that raises a second boosted voltage with rise of an output voltage of a booster circuit that generates a first boosted voltage and then maintains the second boosted voltage at a point when the output voltage reaches a hold voltage level after that, and a first switch that short-circuits a first output terminal through which the first boosted voltage is output and a second output terminal through which the second boosted voltage is output until the output voltage reaches the hold voltage level. | 02-11-2016 |
20160043131 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region. | 02-11-2016 |
20160043098 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming n | 02-11-2016 |
20160043080 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH. | 02-11-2016 |
20160042099 | BEHAVIORAL SYNTHESIS APPARATUS, BEHAVIORAL SYNTHESIS METHOD, DATA PROCESSING SYSTEM INCLUDING BEHAVIORAL SYNTHESIS APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM - A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline. | 02-11-2016 |
20160041912 | DATA PROCESSING DEVICE - The disclosed invention enables the operation of an MIMD type, an SIMD type, or coexistence thereof in a multiprocessor system including a plurality of CPUs and reduces power consumption for instruction fetch by CPUs operating in the SIMD type. A plurality of CPUs and a plurality of memories corresponding thereto are provided. When the CPUs fetch instruction codes of different addresses from the corresponding memories, the CPUs operate independently (operation of the MIMD type). On the other hand, when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, that is, operate in the SIMD type, the instruction code read from one of the memories by one access is parallelly supplied to the CPUs. | 02-11-2016 |
20160035844 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film. | 02-04-2016 |
20160035787 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To protect a plurality of semiconductor chips of a sawn wafer housed in a shipping case. | 02-04-2016 |
20160035734 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed. | 02-04-2016 |
20160035636 | Manufacturing Method of Semiconductor Device - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 02-04-2016 |
20160034368 | SEMICONDUCTOR DEVICE - Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core | 02-04-2016 |
20160027736 | SEMICONDUCTOR DEVICE - A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP. | 01-28-2016 |
20160027651 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method. | 01-28-2016 |
20160027502 | SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT - A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor. | 01-28-2016 |
20160027355 | DATA DRIVER FOR PANEL DISPLAY APPARATUSES - A data driver including an output circuit configured to output an output signal, and a driver output terminal configured to be connected with a display panel and provide the output signal to the display panel. The output circuit includes a buffer having an output coupled with an input of a first switch and an input of a second switch, an output protective resistor coupled between the driver output terminal and an output of the second switch, and a compensation resistor coupled in series with the first switch and between the output of the buffer and the output protective resistor. | 01-28-2016 |
20160021323 | SEMICONDUCTOR DEVICE, RAMP SIGNAL CONTROL METHOD, IMAGE DATA GENERATING METHOD, AND CAMERA SYSTEM - Conventional semiconductor devices disadvantageously failed to sufficiently enlarge a dynamic range. A semiconductor device according to an embodiment includes a plurality of registers | 01-21-2016 |
20160019913 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND SIGNAL PROCESSING PROGRAM - Disclosed is a signal processing apparatus that processes an input signal to accurately detect an abrupt change in the input signal in accordance with the degree of linear change of a phase component in a frequency domain. The signal processing apparatus includes a converter that converts the input signal into the phase component and an amplitude component in the frequency domain, a linearity calculator that calculates the linearity of the phase component in the frequency domain, and a determiner that determines presence of the abrupt change in the input signal based on the linearity calculated by the linearity calculator. | 01-21-2016 |
20160006542 | SEMICONDUCTOR DEVICE AND DATA TRANSMISSION METHOD - In a semiconductor device, a transmitting circuit generates a delayed data signal and a first delayed retransmission request signal by delaying a data signal and a first retransmission request signal, respectively, and outputs a pulse signal at an edge of the delayed data signal and the first delayed retransmission request signal and prohibits output of the pulse signal at an edge of the first delayed retransmission request signal during a specified period across an edge of the delayed data signal. | 01-07-2016 |
20160006386 | MOTOR DRIVE CONTROLLER AND METHOD FOR OPERATING THE SAME - A motor driver controller including a difference control section; a driver output section; a drive current detection amplifier; and a load short-circuit detection circuit. A motor and sensing resistor is coupled in series and coupled to an output terminal of the driver output section. The difference control section generates a drive voltage command signal in response to a drive current command value and a drive current detection signal. The driver output section drives the motor and sensing resistor, in response to the drive voltage command signal, and a drive current detection amplifier generates a signal fed to the difference control section, in response to a drive current of the sensing resistor. The load short-circuit detection circuit detects an abnormal oscillation waveform signal caused by a short-circuit state between the both ends of the motor. | 01-07-2016 |
20160005819 | SEMICONDUCTOR DEVICE - Contact resistance between a SiC substrate and an electrode is decreased. When a silicide layer is analyzed by Auger Electron Spectroscopy (AES) sputter in a direction from a titanium layer side to a SiC substrate side, sputtering time corresponding to a depth profile of the silicide layer is defined as t | 01-07-2016 |
20160005665 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Reading reliability of a code formed in a semiconductor device is improved. | 01-07-2016 |
20160005640 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. | 01-07-2016 |
20160003887 | ISOLATOR, SEMICONDUCTOR DEVICE, AND METHOD FOR CONTROLLING ISOLATOR - An isolator includes: a transmission circuit that generates an alternating current transmission signal in which a first potential is set to be a reference potential; a first insulating element to which the alternating current transmission signal is supplied; a second insulating element that generates an alternating current reception signal in which a second potential is set to be a reference potential by being alternating current-coupled to the first insulating element through an insulating film; a reception circuit that reproduces reception data based on the alternating current reception signal; an impedance control unit that controls an impedance of the first or the second insulating element to be higher than an impedance before the control; and a leakage current detection unit that detects a leakage current flowing between the first and the second insulating elements through the first or the second insulating element in which the impedance has been controlled. | 01-07-2016 |
20150381347 | DATA PROCESSOR AND DECRYPTION METHOD - There is a need to perform recalculation against a fault attack on any public key e within a time period required for one-time modulo exponentiation. | 12-31-2015 |
20150380507 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line. | 12-31-2015 |
20150380487 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends. | 12-31-2015 |
20150380425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode. | 12-31-2015 |
20150374250 | MAGNETIC MEASUREMENT APPARATUS - High-accuracy magnetic measurement is performed by efficiently using nitrogen-vacancy pairs in all orientations. A magnetic measurement apparatus includes a diamond crystal and an image sensor. The diamond crystal has nitrogen-vacancy pairs. The image sensor detects the intensities of fluorescence generated by an exciting light applied to the diamond crystal by using a plurality of pixels. The nitrogen-vacancy pairs of the diamond crystal are made to one-to-one correspond to the pixels. The fluorescence generated by one nitrogen-vacancy pair is received by one pixel made to correspond to the nitrogen-vacancy pair. | 12-31-2015 |
20150372102 | SEMICONDUCTOR DEVICE - The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced. | 12-24-2015 |
20150372044 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a semiconductor integrated circuit device having pixel regions in a photodiode array region and having, in each of the pixel regions, a waveguide holding hole having a substantially perpendicular sidewall above the photodiode and embedded with a silicon oxide-based sidewall insulating film reaching the bottom surface of the hole and two or more silicon nitride-based insulating films having a higher refractive index on the inner side of the hole. This structure makes it possible to prevent deterioration of pixel characteristics of an imaging device, such as CMOS sensor, which is rapidly decreasing in size. | 12-24-2015 |
20150371958 | IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - In an imaging device having a waveguide, a surface of an insulating film covering a seal ring is prevented from getting rough. A pixel region, a peripheral circuit region, and a seal region are defined over a semiconductor substrate. After formation of a pad electrode in the peripheral circuit region and a seal ring in the seal ring region, a TEOS film is so formed as to cover the pad electrode and the seal ring. A pattern of a photoresist for exposing a portion of the TEOS film covering the pad electrode and the seal ring, respectively, is formed and etching treatment is subjected to the exposed TEOS film. Then, after the pattern of the photoresist has been formed, a second waveguide holding hole is formed in the pixel region by performing etching treatment. | 12-24-2015 |
20150371945 | SEMICONDUCTOR DEVICE WITH CONTACTS AND METAL INTERCONNECTS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact. | 12-24-2015 |
20150370755 | SIMD PROCESSOR AND CONTROL PROCESSOR, AND PROCESSING ELEMENT WITH ADDRESS CALCULATING UNIT - To improve processing efficiency of a SIMD processor that divides two-dimensional data into blocks, each having a width of PE number N, to store the data in a local memory of each of PEs by a lateral direction priority method. | 12-24-2015 |
20150364490 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode. | 12-17-2015 |
20150364392 | SEMICONDUCTOR DEVICE WITH COVERING MEMBER THAT PARTIALLY COVERS WIRING SUBSTRATE - An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other. | 12-17-2015 |
20150364099 | DATA DRIVER, DISPLAY PANEL DRIVING DEVICE, AND DISPLAY DEVICE - To reduce current noise by reducing the current peak value and the current rise slope, a data driver includes a delay unit and a plurality of output circuits. The delay unit sequentially delays a control signal and outputs delay control signals. The output circuits start outputting in response to the delay control signals. The delay unit generates the delay control signals to be output to the output circuits. | 12-17-2015 |
20150358170 | COMMUNICATION SYSTEM, VEHICLE-MOUNTED TERMINAL, ROADSIDE DEVICE - A communication system ( | 12-10-2015 |
20150358048 | FREQUENCY CORRECTION CIRCUIT, RADIO RECEIVING APPARATUS, AND FREQUENCY CORRECTION METHOD - A frequency correction circuit used in a radio receiving apparatus that receives a preamble signal through one frequency band and also detects a periodic symbol timing in a receiving period of a part of a symbol that composes the preamble signal, the frequency correction circuit includes a generating unit that generates a detection window of a predetermined time width including each of a first symbol timing and a second symbol timing in the receiving period of a remaining symbol that composes the preamble signal, the first and the second symbol timing being previously determined among periodic symbol timings, a detecting unit that sequentially receives a correlation value between the preamble signal and a reference signal and detects a maximum value from the correlation value input during a period when the detection window is opened, and a correction unit that corrects a frequency deviation of the one frequency band. | 12-10-2015 |
20150357980 | SIGNAL PROCESSING CIRCUIT, RESOLVER DIGITAL CONVERTER, AND MULTIPATH NESTED MIRROR AMPLIFIER - A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period. | 12-10-2015 |
20150357370 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to improve the performance of a semiconductor device. | 12-10-2015 |
20150357368 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The performance of a solid state image sensor which is formed by performing divided exposure that exposes the entire chip by a plurality of times of exposure and in which each of a plurality of pixels arranged in a pixel array portion has a plurality of photodiodes is improved. | 12-10-2015 |
20150357365 | SEMICONDUCTOR DEVICE - A semiconductor device is reduced in power consumption, the semiconductor device including a solid-state imaging device that includes pixels each having a plurality of light receiving elements. A pixel having first and second photodiodes is provided with a first transfer transistor that transfers charge in the first photodiode to a floating diffusion capacitance section, and a second transfer transistor that combines charge in the first photodiode and charge in the second photodiode, and transfers the combined charge to the floating diffusion capacitance section. Consequently, the semiconductor device is reduced in power required for activation of each transfer transistor in operation such as imaging with the solid-state imaging device. | 12-10-2015 |
20150357335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films). | 12-10-2015 |
20150357293 | SEMICONDUCTOR DEVICE - A semiconductor device is a semiconductor device in which one chip region is formed through divided exposure. An interlayer insulating film has a via and an interconnection trench in an element formation region and has a guard ring hole in a guard ring region. An interconnection conductive layer is formed in the via and the interconnection trench. A guard ring conductive layer is formed in the guard ring hole. A minimum dimension of a width of the guard ring conductive layer is greater than a minimum dimension of a width of the interconnection conductive layer in the via. | 12-10-2015 |
20150356941 | OPERATIONAL AMPLIFYING CIRCUIT AND LIQUID CRYSTAL PANEL DRIVE DEVICE USING THE SAME - An operational amplifier circuit includes: a first differential amplifier section containing a P-type differential pair of P-type transistors; a second differential amplifier section containing an N-type differential pair of N-type transistors; an intermediate stage connected with outputs of the first and second differential amplifier sections and containing a first current mirror circuit of P-type transistors, and a second current mirror circuit of N-type transistors; and an output stage configured to amplify an output of the intermediate stage in power. The first differential amplifier section includes a first current source and a first capacitance between sources of the P-type transistors of the P-type differential pair and a positive side power supply voltage. The second differential amplifier section includes a second current source and a second capacitance between sources of the N-type transistors of the N-type differential pair and a negative side power supply voltage. | 12-10-2015 |
20150349496 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor laser that suppresses end face destruction due to catastrophic optical damage (COD) to a light emission end face and has high output characteristics. | 12-03-2015 |
20150349143 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film. | 12-03-2015 |
20150349055 | SEMICONDUCTOR DEVICE - An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired. | 12-03-2015 |
20150348641 | SEMICONDUCTOR MEMORY DEVICE WITH POWER INTERRUPTION DETECTION AND RESET CIRCUIT - A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential. | 12-03-2015 |
20150347475 | PROCESSOR AND DATA GATHERING METHOD - An object of the present invention is to efficiently perform a data load process or a data store process between a memory and a storage unit in a processor. The processor includes: a plurality of storage units associated with a plurality of data elements included in a data set; and a control unit that reads the plurality of data elements stored in adjacent storage areas from a memory, in which a plurality of the data sets is stored, collectively for respective data sets, sorts the respective read data elements to a storage unit corresponding to the data element among the plurality of storage units, and writes the data elements to the respective data sets. | 12-03-2015 |
20150340479 | SEMICONDUCTOR DEVICE - The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. | 11-26-2015 |
20150340315 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect. | 11-26-2015 |
20150339222 | CONTENT ADDRESSABLE MEMORY AND SEMICONDUCTOR DEVICE - In a memory, multiple pieces of entry data sorted in ascending or descending order are stored associated with addresses. With whole addresses for storing the multiple pieces of entry data as an initial search area, the search circuit repeatedly performs a search operation for comparing entry data stored in a central address of the search area with the search data, outputting the address as a search result in the case of a match, and narrowing the search area for the next search based on a magnitude comparison result in the case of a mismatch. | 11-26-2015 |
20150339201 | MICROCONTROLLER AND ELECTRONIC CONTROL DEVICE USING THE SAME - The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part. | 11-26-2015 |
20150333841 | OPTICAL COUPLING CIRCUIT, LIGHT-RECEIVING APPARATUS OF OPTICAL COUPLING CIRCUIT AND SIGNAL PROCESSING DEVICE - A light-emitting unit outputs an optical signal corresponding to an input electric signal. A light-receiving unit is electrically insulated from the light-emitting unit and outputs an electric signal according to the received optical signal as an output signal. In the light-receiving unit, a first light-receiving device outputs an optical current according to the optical signal. A second light-receiving device is provided not to receive the optical signal. A current duplication circuit duplicates a current flowing through the second light-receiving device. A current-voltage conversion circuit converts a current, which is generated by subtracting the current duplicated by the current duplication circuit from a current flowing through the first light-receiving device, into a voltage signal. A comparator output a result of a comparison between the voltage signal converted by the current-voltage conversion circuit and a threshold voltage as the output signal. | 11-19-2015 |
20150333674 | SEMICONDUCTOR DEVICE AND DRIVING SYSTEM - An output MOS transistor has a drain connected with a power supply and a source connected with an output terminal. The short-circuit MOS transistor has a source connected with the output terminal. The short-circuit MOS transistor is formed in a semiconductor substrate connected with the power supply. A switching device is formed in a semiconductor region which is formed in the semiconductor substrate, and contains a first diffusion layer connected with the gate of the output MOS transistor and a second diffusion layer formed in the semiconductor region and connected with the drain of the short-circuit MOS transistor. | 11-19-2015 |
20150333139 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers. | 11-19-2015 |
20150332752 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device | 11-19-2015 |
20150326209 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode. | 11-12-2015 |
20150325696 | SEMICONDUCTOR DEVICE - A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film. | 11-12-2015 |
20150325673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer. | 11-12-2015 |
20150325583 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode. | 11-12-2015 |
20150325528 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate. An alignment mark formed over the wiring substrate is aligned with an alignment mark formed on a front surface of the logic chip, whereby the logic chip is mounted over the wiring substrate. An alignment mark formed on a back surface of the logic chip is aligned with an alignment mark formed on a front surface of the laminated body, whereby the laminated body is mounted over the back surface of the logic chip LG. | 11-12-2015 |
20150325502 | SEMICONDUCTOR DEVICE WITH STEP PORTION HAVING SHEAR SURFACES - A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion. | 11-12-2015 |
20150325486 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer. | 11-12-2015 |
20150324310 | BUS CONNECTION CIRCUIT, SEMICONDUCTOR DEVICE AND OPERATION METHOD OF BUS CONNECTION CIRCUIT FOR MAKING PROCEDURE FOR SWITCHING BETWEEN A 1-CYCLE TRANSFER AND A 2-CYCLE TRANSFER UNNECESSARY - A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a minor area access detecting circuit and a processing circuit. The minor area access detecting circuit detects that the bus master accesses a minor area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result. | 11-12-2015 |
20150324225 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM SELECTIVELY OPERATING AS ONE OF A BIG ENDIAN OR LITTLE ENDIAN SYSTEM - The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status. | 11-12-2015 |
20150319019 | DECISION FEEDBACK EQUALIZER - A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder | 11-05-2015 |
20150317943 | DIFFERENTIAL AMPLIFIER AND CONTROL METHOD FOR THE SAME - A liquid crystal display apparatus includes a signal generating circuit configured to generate a first control signal and a second control signal; and a differential amplifier. The differential amplifier includes: a first differential pair of transistors configured to receive a differential input signal; a first constant current source connected with said first differential pair of transistors; and a first switch connected in parallel with said first constant current source and configured to increase current which flows through said first differential pair of transistors, in response to said first control signal which is active for a first time period in a level transition of said differential input signal. | 11-05-2015 |
20150317261 | SEMICONDUCTOR DEVICE - There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels. | 11-05-2015 |
20150317258 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD - A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition. | 11-05-2015 |
20150311677 | SEMICONDUCTOR DEVICE - The characteristics of a semiconductor laser are improved. In a semiconductor laser having an n type cladding layer, an active layer, and a p type cladding layer, a current block layer is provided. For example, the current block layer is arranged partially between the p type cladding layer and the active layer, and in the overlapping region of the p type cladding layer and the active layer. Thus, in a current narrowing region of the overlapping region of the p type cladding layer and the active layer, the current block layer is arranged, thereby to suppress the current injected into a part of the active layer. This results in the formation of a saturable absorbing region, which causes a difference in intensity of the optical output of the semiconductor laser. This can implement self-pulsation. | 10-29-2015 |
20150311216 | OTP MEMORY - The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high. | 10-29-2015 |
20150311133 | SEMICONDUCTOR DEVICE - A first photosensitive organic insulating film (PO | 10-29-2015 |
20150303924 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. | 10-22-2015 |
20150303230 | METHOD FOR MANUFACTURING IMAGE CAPTURING DEVICE AND IMAGE CAPTURING DEVICE - An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask. | 10-22-2015 |
20150303182 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes: a MOSFET having a gate electrode formed via a gate insulating film over a semiconductor layer and source and drain regions formed in the semiconductor layer on both sides of the gate electrode; and a diode. The diode has an n | 10-22-2015 |
20150303143 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an oscillator and a manufacturing method thereof, in which cost is low and design flexibility is high. The semiconductor device includes a wiring structure region and an oscillator region. The semiconductor device also includes, in the oscillator region, a metal resistive element as the same layer as a conducting film over uppermost metal wiring in the wiring structure region. | 10-22-2015 |
20150301935 | MICROCOMPUTER AND NONVOLATILE SEMICONDUCTOR DEVICE - A program counter ( | 10-22-2015 |
20150295572 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 10-15-2015 |
20150295166 | MAGNETIC MEMORY - A magnetic memory includes: a base layer; a magnetization free layer; a barrier layer; and a magnetization reference layer. The magnetization free layer, with which the base layer is covered, has invertible magnetization and is magnetized approximately uniformly. The barrier layer, with which the magnetization free layer is covered, is composed of material different from material of the base layer. The magnetization reference layer is arranged on the barrier layer and has a fixed magnetization. When the magnetization of the magnetization free layer is inverted, a first writing current is made to flow from one end to the other end of the magnetization free layer in an in-plane direction without through the magnetization reference layer. | 10-15-2015 |
20150294947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film. | 10-15-2015 |
20150293850 | SEMICONDUCTOR DEVICE AND METHOD FOR PREFETCHING TO CACHE MEMORY - A microcontroller includes multiple ways each including only one tag. When a first access and a second access are accesses performed in succession to consecutive addresses, and when the second access is the access through a first way, a cache controller performs the following operations: prefetching to the way whose tag value is smaller by 1 than the tag value corresponding to the first way when the second access is the access in the direction in which the address is incremented with respect to the first access; and prefetching to the way whose tag value is greater by 1 than the tag value corresponding to the first way when the access is in the direction in which the address is decremented. | 10-15-2015 |
20150292924 | ROTATION NUMBER MEASUREMENT DEVICE, ROTATION NUMBER MEASUREMENT METHOD, AND FLOW RATE MEASUREMENT DEVICE - A rotation number measurement device includes a detection circuit for generating a signal that differs depending on whether a first area is near or a second area is near by rotation of a rotating plate, a determination circuit which receives the signal of the detection circuit and a reference value and determines the signal based on the reference value, a counting circuit for obtaining a count indicating that a determination of the determination circuit with a first period during a first duration is a signal corresponding to the first area, and a reference circuit for generating the reference value so that a ratio between a count indicating that a determination of the determination circuit with the first period during the first duration is a signal corresponding to the second area and the count of the counting circuit becomes equal to a ratio between the second area and the first area. | 10-15-2015 |
20150288904 | SOLID-STATE IMAGE PICKUP DEVICE WITH PLURALITY OF CONVERTERS - A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range. | 10-08-2015 |
20150288377 | DATA PROCESSING SYSTEM - The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a conversion range and is small in conversion error. The data processing system, which obtains an A/D conversion result after an n (where n: positive integer)-bit extension made to the resolution of an A/D converter, divides the input range of the A/D converter by m ( | 10-08-2015 |
20150287832 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via. | 10-08-2015 |
20150287778 | POWER SUPERJUNCTION MOSFET DEVICE WITH RESURF REGIONS - A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. | 10-08-2015 |
20150287736 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region. | 10-08-2015 |
20150287684 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. Further, miniaturization of the semiconductor device is attained. A sealring is formed in a wiring structure provided over a semiconductor substrate. The sealring has a structure in which sealring wirings respectively formed in a plurality of wiring layers included in the wiring structure are laminated. The position of a side surface on the inner peripheral side of a sealring wiring formed in the wiring layer at the uppermost layer in the wiring layers is located more outside than the position of a side surface on the inner peripheral side of a sealring wiring formed in the wiring layer located one layer lower than the wiring layer at the uppermost layer. The width of the sealring wiring at the uppermost layer is smaller than the width of the sealring wiring located one layer lower than the wiring layer at the uppermost layer. | 10-08-2015 |
20150286583 | PROCESSOR SYSTEM AND CONTROL METHOD THEREOF - A processor system according to the present invention includes a storage unit ( | 10-08-2015 |
20150281541 | IMAGE PICKUP APPARATUS - A first control unit ( | 10-01-2015 |
20150279923 | SEMICONDUCTOR DEVICE - To provide a semiconductor device having less variation in characteristics. The semiconductor device is equipped with a plug formed in an interlayer insulating film, a lower electrode provided on the plug and to be coupled to the plug, a middle layer provided on the lower electrode and made of a metal oxide, and an upper electrode provided on the middle layer. The middle layer has a layered region contiguous to the lower electrode and the upper electrode. At least a portion of the layered region does not overlap with the plug. At least a portion of the plug does not overlap with the layered region. | 10-01-2015 |
20150279454 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring. | 10-01-2015 |
20150270727 | SEMICONDUCTOR DEVICE AND BATTERY VOLTAGE MONITORING DEVICE - In battery voltage monitoring ICs for measuring voltages of unit cells of an assembled battery, communication with a system control unit is realized in consideration of fail-safe. The system control unit and the battery voltage monitoring ICs are coupled to each other by a communication path using a daisy chain. Each battery voltage monitoring IC has a placement setting pin designating, by a binary code, a unit cell group to which the IC is coupled, in the unit cell groups. When it is detected that the Hamming distance between the code indicative of coupling to a group of the highest potential or a group of the lowest potential and a state actually set in the placement setting pin is 1, some failure such as line disconnection, short-circuit, or the like in the placement setting pins is detected, and the communication path is interrupted. | 09-24-2015 |
20150270279 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films. | 09-24-2015 |
20150263851 | SEMICONDUCTOR DEVICE - A frequency tracking loop receives a result from a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal, and conducts a control to reduce a frequency deviation between the input data and the extracted clock signal. A phase interpolator adjusts a phase of the clock signal subjected to spread-spectrum frequency modulation on the basis result of the frequency deviation in the frequency tracking loop, and outputs the extracted clock signal. In the frequency tracking loop, the frequency deviation between the data signal and the clock signal is corrected to offset a variation of the frequency of the clock signal, on the basis of the frequency modulation information related to the clock signal subjected to the spread-spectrum frequency modulation which is input to the phase interpolator. The frequency of the clock signal seemingly follows the frequency of the data signal. | 09-17-2015 |
20150263752 | SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL DEVICE - To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage. | 09-17-2015 |
20150263002 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends. | 09-17-2015 |
20150262599 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD FOR THE SAME - The present invention realizes a calibration operation for detecting a motor speed, without employing digital correcting by an external CPU. The calibration operation calculates a comparison reference value corresponding to aback EMF detection signal of a back EMF detector circuit when a zero current flows through a motor and when an arm is fixed. Accordingly, the back EMF detection signal of the back EMF detector circuit is set as the first value and the second value responding to the non-zero current flowing through the motor, and the semiconductor integrated circuit calculates the comparison reference value from the first value and the second value. The difference between the comparison reference value and the comparison input value as the back EMF detection signal of the back EMF detector circuit is reduced by adjusting the gain of an internal amplifier of the back EMF detector circuit by an adjustment unit. | 09-17-2015 |
20150261712 | CONTROLLER AND TRANSFER SPEED CONTROL METHOD - A USB 3 host controller according to the present invention includes a transfer speed switching unit besides a transfer data converting unit that mutually converts transfer data from a USB device and transfer data from a PCI Express bus. The transfer speed switching unit receives transfer information regarding data transfer from the USB device via a USB 3 interface when the USB device is connected, and identifies a transfer speed used by a PC side according to the transfer information or a result of analyzing the transfer information. Then, when a current transfer speed of the PC side is different from the identified transfer speed, the transfer speed switching unit transmits a speed switching signal indicating switch to the identified transfer speed to a PCI master via a PCI express interface. | 09-17-2015 |
20150256230 | INDUCTIVE-COUPLING SYSTEM AND METHOD WITH COMPENSATION TO PREVENT INTERFERENCE - In a related transmitting circuit employing electromagnetic induction that is used in a communication system, there is a problem in that, because only one inductor is used in the transmitting circuit, it is impossible to perform communication at a data rate higher than the self-resonant frequency of the inductor. A transmitting circuit according to an embodiment of the present invention is a transmitting circuit that drives an inductor to transmit data to a semiconductor chip insulated from a semiconductor chip on which the transmitting circuit is mounted, and includes a driving circuit that receives outgoing data transmitted at a data rate higher than the self-resonant frequency of the inductor and outputs an outgoing signal that drives the inductor at the data rate of the outgoing data. | 09-10-2015 |
20150255572 | IGBT AND DIODE - In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N | 09-10-2015 |
20150254148 | SEMICONDUCTOR DEVICE - A semiconductor device in which unwanted change in the secondary data which must be reliable is suppressed and the need for a considerable increase in the capacity of a memory unit can be avoided. Also it ensures efficient data processing by asymmetric access to the memory unit. It includes a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the memories. A plurality of buses is coupled to the access nodes and a plurality of data processing modules can asymmetrically access the memory unit through the buses. The first memory stores primary data before data processing by the data processing modules, and the second memory stores secondary data after data processing by the data processing modules. | 09-10-2015 |
20150253658 | METHOD OF INSPECTING MASK, MASK INSPECTION DEVICE, AND METHOD OF MANUFACTURING MASK - There is provided a method of high-sensitively detecting both of a phase defect existing in a mask blank and a phase defect remaining after manufacturing an EUVL mask. When the mask blank is inspected, EUV light having illumination NA to be within an inner NA but a larger value is irradiated. When the EUVL mask is inspected, by using a dark-field imaging optical system including a center shielding portion for shielding EUV light and a linear shielding portion for shielding the EUV light whose width is smaller than a diameter of the center shielding portion, the center shielding portion and the linear shielding portion being included in a pupil plane, the EUV light having illumination NA as large as or smaller than the width of the linear shielding portion is irradiated. | 09-10-2015 |
20150249145 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode. | 09-03-2015 |
20150249126 | SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n | 09-03-2015 |
20150248929 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit. | 09-03-2015 |
20150243735 | SEMICONDUCTOR DEVICE - A gate interconnection portion (GHB) includes a first gate interconnection portion (GHB | 08-27-2015 |
20150243731 | SEMICONDUCTOR DEVICE - An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion. | 08-27-2015 |
20150243614 | SEMICONDUCTOR DEVICE - A semiconductor chip and a wiring board are coupled to each other through conductor posts. The centers of conductor posts situated above openings at the outermost periphery shift from the centers of the openings in a direction away from the center of the semiconductor chip. When a region where each of the conductor posts and an insulating layer are overlapped with each other is designated as an overlapped region, the width of the overlapped region more on the inner side than the opening is smaller than the width of the overlapped region more on the outer side than the opening. Thus, while stress applied to the conductor posts is relaxed, coupling reliability between the semiconductor chip and the wiring board is retained. | 08-27-2015 |
20150236530 | SEMICONDUCTOR DEVICE FOR BATTERY CONTROL AND BATTERY PACK - A semiconductor device for battery control includes a CPU, a first bus coupled to the CPU, a second bus not coupled to the CPU, and a protective function circuit for protecting a battery from stress applied thereto. The semiconductor device also includes a non-volatile memory storing trimming data, a trimming circuit to perform trimming required to allow the protective function circuit to exert a protective function, and a bus control circuit capable of selectively coupling the first bus and the second bus to the non-volatile memory. The semiconductor device further includes a transfer logic circuit which causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU. | 08-20-2015 |
20150236170 | SEMICONDUCTOR DEVICE - The performances of a semiconductor device are improved. Between a memory gate electrode and a p type well, and between a control gate electrode and the memory gate electrode of a split gate type nonvolatile memory, an insulation film having a charge accumulation layer therein is formed. The insulation film includes a lamination film of a silicon oxide film, a silicon nitride film formed thereover, another silicon oxide film formed thereover, and an insulation film formed thereover, and thinner than the upper silicon oxide film. The insulation film is in contact with the memory gate electrode including polysilicon. The insulation film is formed of a metal compound containing at least one of Hf, Zr, Al, Ta, and La, and hence can cause Fermi pinning, and has a high dielectric constant. | 08-20-2015 |
20150236057 | SEMICONDUCTOR DEVICE - A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region. The electric field shield film is positioned below the wiring, and has a cutout portion in an overlapping region which overlaps the wiring. By forming the cutout portion, end portions of the electric field shield film is arranged to be shifted. Therefore, formation of a deep concave portion which is based on a concave portion on the silicon oxide film and a step of the electric field shield film over the entire width of the wiring can be prevented, and the disconnection of the wiring can be prevented. | 08-20-2015 |