PROMOS TECHNOLOGIES INC. Patent applications |
Patent application number | Title | Published |
20100213432 | PHASE CHANGE MEMORY DEVICE AND FABRICATION THEREOF - A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer. | 08-26-2010 |
20100165720 | VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY - A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state | 07-01-2010 |
20100163828 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer. | 07-01-2010 |
20100117050 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 05-13-2010 |
20100062593 | METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY DEVICES - A method for preparing a multi-level flash memory device comprises forming a dielectric stack including a charge-trapping layer on a semiconductor substrate, forming an insulation structure having a depression on the charge-trapping layer, removing a portion of the charge-trapping layer from the depression such that the charge-trapping layer is segmented to form a plurality of storage nodes, forming a gate oxide layer isolating the storage nodes and forming a damascene gate including a polysilicon layer filling the depression. | 03-11-2010 |
20100050939 | METHOD FOR DETERMINING THE PERFORMANCE OF IMPLANTING APPARATUS - A method for determining the performance of an implanting apparatus comprises the steps of forming a dopant barrier layer on a substrate, forming a target layer on the dopant barrier layer, performing an implanting process by using the implanting apparatus to implant dopants into the target layer such that the target layer becomes conductive, measuring at least one electrical property of the target layer, and determining the performance of the implanting apparatus by taking the electrical property into consideration. In one embodiment of the present invention, the dopant barrier layer is silicon nitride layer, the target layer is a polysilicon layer, and the electrical property is the sheet resistance of the conductive polysilicon layer. | 03-04-2010 |
20100041192 | Method For Preparing Multi-Level Flash Memory Structure - A method for preparing a multi-level flash memory structure comprises the steps of forming a protrusion in a semiconductor substrate, forming a plurality of storage structures at the sides of the protrusion, forming a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, forming a gate structure on the dielectric layer, and forming a plurality of diffusion regions at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate. | 02-18-2010 |
20100038745 | INTEGRATED CIRCUIT STRUCTURE HAVING BOTTLE-SHAPED ISOLATION - An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region. | 02-18-2010 |
20100022058 | METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY - A method for preparing a multi-level flash memory comprising the steps of forming a recess in a semiconductor substrate, forming a plurality of storage structures at the sides of the recess, and forming a gate structure having a lower block in the recess and an upper block on the lower block. The storage structures are separated by the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site. | 01-28-2010 |
20100020599 | MULTI-LEVEL FLASH MEMORY - A multi-level flash memory comprises a semiconductor substrate, a gate structure having a lower block positioned in the semiconductor substrate and an upper block positioned on the semiconductor substrate, and a plurality of storage structures separated by the gate structure. The upper block connects to the lower block of the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site. | 01-28-2010 |
20100019309 | MULTI-LEVEL FLASH MEMORY STRUCTURE - A multi-level flash memory structure comprises a semiconductor substrate having a protrusion, a plurality of storage structures separated by the protrusion, a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, a gate structure positioned on the dielectric layer, and several diffusion regions positioned at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate. | 01-28-2010 |
20100013004 | RECESSED CHANNEL TRANSISTOR AND METHOD FOR PREPARING THE SAME - A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor. | 01-21-2010 |
20100012996 | DYNAMIC RANDOM ACCESS MEMORY STRUCTURE - A dynamic random access memory structure comprises a substrate having a first diffusion region and a second diffusion region, a dielectric structure overlaying the substrate, a capacitor contact plug disposed in the dielectric structure and connected to the first diffusion region, a bit-line contact plug disposed in the dielectric structure and connected to the second diffusion region, a metal silicide disposed on the capacitor contact plug, and a capacitive structure disposed on the dielectric structure and connected to the metal silicide. | 01-21-2010 |
20100006814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer. | 01-14-2010 |
20100001394 | CHIP PACKAGE WITH ESD PROTECTION STRUCTURE - A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced. | 01-07-2010 |
20090323433 | DATA SENSING METHOD FOR DYNAMIC RANDOM ACCESS MEMORY - A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line. | 12-31-2009 |
20090317982 | ATOMIC LAYER DEPOSITION APPARATUS AND METHOD FOR PREPARING METAL OXIDE LAYER - An atomic layer deposition apparatus comprises a reaction chamber, a heater configured to heat a semiconductor wafer positioned on the heater, an oxidant supply configured to deliver oxidant-containing precursors having different oxidant concentrations to the reaction chamber, and a metal supply configured to deliver a metal-containing precursor to the reaction chamber. The present application also discloses a method for preparing a dielectric structure comprising the steps of placing a substrate in a reaction chamber, performing a first atomic layer deposition process including feeding an oxidant-containing precursor having a relatively lower oxidant concentration and a metal-containing precursor to form an thinner interfacial layer on the substrate, and performing a second atomic layer deposition process including feeding the oxidant-containing precursor having an oxidant concentration higher than that used to grow the first metal oxide layer and the metal-containing precursor into the reaction chamber. | 12-24-2009 |
20090303817 | LEAKAGE TESTING METHOD FOR DYNAMIC RANDOM ACCESS MEMORY HAVING A RECESS GATE - A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines extending through the memory cells; then determining whether the DRAM is acceptable or not. When another one of the word lines extending through the memory cells is caused with a reading error by disturbing the one of the word lines extending through the memory cells, a failure is determined as occurred, and the failure is attributed to a leakage type of extended depletion region. When the another one of the word lines extending through the memory cells is not caused with a reading error by disturbing the one of the word lines extending through the memory cells, the DRAM is determined as acceptable. | 12-10-2009 |
20090298284 | METHOD FOR PREPARING INTEGRATED CIRCUIT STRUCTURE WITH POLYMORPHOUS MATERIAL - A method for preparing an integrated circuit structure performs a deposition process to form a precursor layer on a substrate, and the precursor layer has a phase transition property in a transition temperature region. Subsequently, a first thermal treating process is performed at a first temperature to transform the precursor layer into a polymorphous layer possessing a predetermined crystalline phase, and the first temperature is higher than an upper limit of the temperature of the transition temperature region. | 12-03-2009 |
20090296450 | Memory And Writing Method Thereof - A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level. | 12-03-2009 |
20090294750 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively. | 12-03-2009 |
20090291548 | METHOD FOR PREPARING P-TYPE POLYSILICON GATE STRUCTURE - A method for preparing a P-type polysilicon gate structure comprises the steps of forming a gate oxide layer on a substrate, forming an N-type polysilicon layer on the gate oxide layer, performing a first implanting process to convert the N-type polysilicon layer into a P-type polysilicon layer, performing a second implanting process to implant P-type dopants into a portion of the P-type polysilicon layer near the interface between the gate oxide layer and the P-type polysilicon layer, and performing a thermal treating process at a predetermined temperature for a predetermined period to complete the P-type polysilicon gate structure. | 11-26-2009 |
20090283822 | NON-VOLATILE MEMORY STRUCTURE AND METHOD FOR PREPARING THE SAME - A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure formed by performing a first thermal oxidation process to form a high-k dielectric layer on a substrate, forming a metal-containing semiconductor layer including silicon or germanium on the high-k dielectric layer, forming a silicon layer on the metal-containing semiconductor layer, and performing a second thermal oxidation process to convert the metal-containing semiconductor layer to a silicon-oxy-nitride layer with embedded metallic nano-dots, wherein at least one of the first thermal oxidation process and the second thermal oxidation process is performed in a nitrogen-containing atmosphere. | 11-19-2009 |
20090276750 | METHOD FOR ESTABLISHING SCATTERING BAR RULE - A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern. | 11-05-2009 |
20090250691 | PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME - A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate. | 10-08-2009 |
20090239315 | METHOD AND SYSTEM FOR PROCESSING TEST WAFER IN PHOTOLITHOGRAPHY PROCESS - A method and a system for processing a test wafer in a photolithography process are provided for processing an i | 09-24-2009 |
20090212794 | TEST KEY FOR SEMICONDUCTOR STRUCTURE - A test key for a semiconductor structure is provided for in-line defecting defects of the contact. The test key is disposed on a scribe line of a wafer substrate, and includes conductive structures and contacts under test. The conductive structures are electrically connected with the substrate and the contacts under test are not electrically connected with the substrate. The conductive structures and the contacts under test are regularly arranged in array. When an electronic beam is utilized to perform in-line monitoring, the normal contacts under test will be shown as bright dots and the bright dots are regularly arranged in the array; any contact under test with defect will be shown as a dark dot which results in an irregular arrangement of the bright dots. | 08-27-2009 |
20090191686 | Method for Preparing Doped Polysilicon Conductor and Method for Preparing Trench Capacitor Structure Using the Same - A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor. | 07-30-2009 |
20090191367 | MEMORY DEVICES, STYLUS-SHAPED STRUCTURES, ELECTRONIC APPARATUSES, AND METHODS FOR FABRICATING THE SAME - An exemplary hollow stylus-shaped structure is disclosed, including a hollow column spacer formed over a base layer and a hollow cone spacer stacked over the hollow column spacer, wherein the hollow cone spacer, the hollow column spacer, and the base layer form a space, and sidewalls of the hollow cone spacer and the hollow column spacer are made of silicon-containing organic or inorganic materials. | 07-30-2009 |
20090189142 | Phase-Change Memory - A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. | 07-30-2009 |
20090189140 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal. | 07-30-2009 |
20090148980 | METHOD FOR FORMING PHASE-CHANGE MEMORY ELEMENT - A method for forming a phase-change memory element. The method includes providing a substrate with an electrode formed thereon; sequentially forming a conductive layer and a first dielectric layer on the substrate; forming a patterned photoresist layer on the first dielectric layer; subjecting the patterned photoresist layer to a trimming process, remaining a photoresist pillar; etching the first dielectric layer with the photoresist pillar as etching mask, remaining a dielectric pillar; comformally forming a first phase-change material layer on the conductive layer and the dielectric pillar to cover the top surface and side walls of the dielectric pillar; forming a second dielectric layer to cover the first phase-change material layer; subjecting to the second dielectric layer and the first phase-change material layer to a planarization until exposing the top surface of the dielectric pillar; and forming a second phase-change material layer on the second dielectric layer. | 06-11-2009 |
20090147566 | Phase Change Memory And Control Method Thereof - A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein. | 06-11-2009 |
20090146127 | PHASE CHANGE MEMORY - Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the heaters. The bottom electrodes are respectively coupled to the heaters. Regarding the transistors, their first terminals are respectively coupled to the bottom electrodes, their control terminals are used for coupling to word lines, and their second terminals are used for coupling to bit lines. In an embodiment with four heaters, the regions the heaters aimed at the phase change element form a 2×2 storage array. | 06-11-2009 |
20090141548 | MEMORY AND METHOD FOR DISSIPATION CAUSED BY CURRENT LEAKAGE - Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed. | 06-04-2009 |
20090135645 | Data Programming Circuits And Memory Programming Methods - A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data. | 05-28-2009 |
20090130818 | METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR PREPARING RECESSED GATE STRUCTURE USING THE SAME - A method for preparing a recessed gate structure comprises the steps of: forming a shallow trench isolation structure surrounding an active area in a silicon substrate, wherein an etching barrier layer is formed on the surface of the shallow trench isolation structure; forming a plurality of gate trenches in the active area of the silicon substrate by performing an etching process; and forming a recessed gate structure by filling the gate trench with a predetermined height. | 05-21-2009 |
20090127618 | MULTI-FIN FIELD EFFECT TRANSISTOR - A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer. | 05-21-2009 |
20090127535 | PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FABRICATING THE SAME - A phase change memory device is disclosed, including a substrate. The phase change memory also includes a bottom electrode. A conductive structure with a cavity is provided to electrically contact the bottom electrode, wherein the conductive structure includes sidewalls with different thicknesses. A phase change spacer is formed to cross the sidewalls with different thicknesses. A top electrode is electrically contacted to the phase change spacer. | 05-21-2009 |
20090122599 | WRITING SYSTEM AND METHOD FOR PHASE CHANGE MOMORY - An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched. | 05-14-2009 |
20090117699 | METHOD FOR PREPARING A RECESSED TRANSISTOR STRUCTURE - A method for preparing a recessed transistor structure comprises the steps of performing an implanting process to form a doped layer in a substrate, forming a plurality of gate-isolation blocks on the substrate, forming a plurality of first spacers on sidewalls of the gate-isolation blocks, removing a portion of the substrate not covered by the first spacers and the gate-isolation blocks to form a plurality of depressions in the substrate between the first spacers, forming a gate oxide layer on inner sidewalls of the depressions, and forming a gate structure on the gate oxide layer to complete the recessed transistor structure. | 05-07-2009 |
20090101884 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer. | 04-23-2009 |
20090101880 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the first dielectric layer and covered a portion of the first conductive contact and the insulating layer in a first direction, contacting to the first conductive contact and a first side of the PCM. A second electrode is disposed over the first dielectric layer and covered a portion of the insulating layer in a second direction, contacting to a second side of the PCM. A second dielectric layer is disposed over the first dielectric layer to cover the first electrode, the second electrode, the insulating layer and the PCM, including a second conductive contact connected to the second electrode. | 04-23-2009 |
20090096038 | POWER MOSFET ARRAY - A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration. | 04-16-2009 |
20090080243 | DEVICE CONTROLLING PHASE CHANGE STORAGE ELEMENT AND METHOD THEREOF - Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period. | 03-26-2009 |
20090078926 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed. | 03-26-2009 |
20090065758 | PHASE CHANGE MEMORY ARRAY AND FABRICATION THEREOF - A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers. | 03-12-2009 |
20090062954 | METHOD AND SYSTEM FOR AUTO-DISPATCHING LOTS IN PHOTOLITHOGRAPHY PROCESS - A method and a system for auto-dispatching lots in a photolithography process are provided. According to the method, first, a prioritized lot list is established according to the working status of a plurality of photolithography equipments. Then, a processable lot with the highest priority from the lot list is selected and a relative process background information is used for determining a photolithography operation type. Finally, the selected lot is dispatched according to the photolithography operation type. The present invention dispatches the lot with the appropriate dispatching rule according to the process background information of the lot. As a result, the quality of the photolithography process can be ensured so as to increase the throughput, and the labor overhead can be reduced to achieve the purpose of production cost reduction. | 03-05-2009 |
20090061583 | METHOD FOR PREPARING DYNAMIC RANDOM ACCESS MEMORY STRUCTURE - A method for preparing a dynamic random access memory structure, comprising steps of forming a bottom conductive region in a substrate, removing a predetermined portion of the substrate to form a plurality of pillars having a bottom end lower than a bottom surface of the bottom conductive region, forming a first oxide layer on the substrate and below the bottom conductive region in the pillar, forming a conductive block between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars, forming a second oxide layer covering the conductive block, forming a gate oxide layer on a sidewall of the pillar, forming a gate structure on a surface of the gate oxide layer; and forming an upper conductive region on a top portion of the pillar. | 03-05-2009 |
20090057643 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer. | 03-05-2009 |
20090057640 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element and fabrication method thereof is provided. The phase-change memory element comprises an electrode. A first dielectric layer is formed on the substrate. An opening passes through the first dielectric layer exposing the electrode. A heater with an extended part is formed in the opening, wherein the extended part protrudes the opening. A second dielectric layer surrounds the extended part of the heater exposing the top surface of the extended part. A phase-changed material layer is formed on the second dielectric layer to directly contact the top of the extended part. | 03-05-2009 |
20090053870 | METHOD FOR PREPARING FLASH MEMORY STRUCTURES - A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate. | 02-26-2009 |
20090045386 | Phase-change memory element - A phase-change memory element. The phase-change memory element comprises a first electrode and a second electrode. A first phase change layer is electrically coupled to the first electrode. A second phase change layer is electrically coupled to the second electrode. A conductive bridge is formed between and electrically coupled to the first and second phase change layers. | 02-19-2009 |
20090040820 | Phase Change Memory - A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units, is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least, one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result. | 02-12-2009 |
20090039443 | GATE STRUCTURE - A gate structure includes a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate dielectric layer and has an opening. A part of the second conductive layer is disposed in the opening. The second conductive layer has an extrusion that protrudes above the opening of the first conductive layer. The extrusion has a cross-sectional width less than the width of the second conductive layer inside the opening. The cap layer is disposed on the extrusion. The first insulating spacer is disposed on a part of the first conductive layer and covers the sidewalls of the extrusion. The inclusion of the extrusion in the second conductive layer decreases the resistance of the gate structure and promotes the efficiency of the device. | 02-12-2009 |
20090039295 | DETACHABLE INNER SHIELD - A detachable inner shield suitable for an isolation bushing of an ion implanter is provided. The inner shield is mounted on an inside of the isolation bushing and completely fitting the inside of the isolation bushing. | 02-12-2009 |
20090038393 | LIQUID LEVEL SENSING APPARATUS WITH SELF-DIAGNOSIS FUNCTION AND METHOD FOR SELF-DIAGNOSING THEREOF - A liquid level sensing apparatus with self-diagnosis function suitable for sensing liquid level in a storage tank is provided. The liquid level sensing apparatus includes a lifting apparatus, a separated tank, and a liquid level sensor. The separated tank is disposed on the lifting apparatus and communicates with the storage tank. The liquid level sensor is disposed inside the separated tank. | 02-12-2009 |
20090032794 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A first dielectric layer having a sidewall is provided. A bottom electrode is adjacent to the sidewall of the first dielectric layer, wherein the bottom electrode comprises a seed layer and a conductive layer. A second dielectric layer is adjacent to a side of the bottom electrode opposite the sidewall of the first dielectric layer. A top electrode couples the bottom electrode through a phase change layer. | 02-05-2009 |
20090017597 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION - A method for manufacturing semiconductor shallow trench isolation is performed as follows. First, a semiconductor substrate including at least one shallow trench is provided, and the shallow trench is filled with Spin-On-Dielectric (SOD) material, e.g., polysilazane, to form a SOD material layer. Then, the SOD material layer is subjected to a planarization process. Oxygen ions are implanted into the SOD material layer to a predetermined depth, and a high temperature process is performed afterwards to transform the portion of the SOD material layer having oxygen ions into a silicon oxide layer. The oxygen ions can be implanted by plasma doping, immersion doping or ion implantation. | 01-15-2009 |
20090014834 | Contact plug structure - A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced. | 01-15-2009 |
20090014787 | Multi-Layer Semiconductor Structure and Manufacturing Method Thereof - A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively. | 01-15-2009 |
20090014705 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer. | 01-15-2009 |
20090010047 | WRITING CIRCUIT FOR A PHASE CHANGE MEMORY - A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path. | 01-08-2009 |
20090008781 | SEMICONDUCTOR DEVICE - A semiconductor device structure includes a substrate, a first conductive layer over the substrate, a second conductive layer between the first conductive layer and the substrate and extending over the sidewalls of the first conductive layer, a dielectric layer between the second conductive layer and the substrate, a cap layer over the first conductive layer and the second conductive layer, and a liner layer on the sidewalls of the second conductive layer. | 01-08-2009 |
20090008621 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 Å. | 01-08-2009 |
20080318392 | SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming shallow trench isolation structures is provided. The method comprises the following steps: providing a substrate with a “v” shaped trench, forming a first dielectric layer to cover the upper portion of the inner wall of the trench; conducting the first etching process to pull back the uncovered inner wall of the trench; removing the first dielectric layer; and forming a second dielectric layer to cover the trench and form a void inside the trench. | 12-25-2008 |
20080316847 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device. | 12-25-2008 |
20080316803 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device. | 12-25-2008 |
20080311699 | PHASE-CHANGE MEMORY AND FABRICATION METHOD THEREOF - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 12-18-2008 |
20080305640 | METHOD FOR PREPARING TRENCH POWER TRANSISTORS - A method for preparing a trench power transistor comprises the steps of forming a mask layer having a plurality of openings on a semiconductor substrate, removing a portion of the semiconductor substrate under the openings to form a plurality of trenches in the semiconductor substrate in an array manner, coating a photoresist layer covering the surface of the mask layer, patterning the photoresist layer, and removing a portion of the mask layer not covered by the photoresist layer to form a mask block exposing a portion of the semiconductor substrate in the array region. | 12-11-2008 |
20080305594 | METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers. | 12-11-2008 |
20080305592 | MENUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY - A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure. | 12-11-2008 |
20080296554 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device includes an array of phase change memory cells. Each phase change memory cell includes a selecting transistor disposed on a substrate. An upright electrode structure is electrically connected to the selecting transistor. An upright phase change memory layer is stacked on the upright electrode structure with a contact area therebetween, wherein the contact area serves as the location where phase transition takes place. | 12-04-2008 |
20080296552 | PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory cell structures and methods for fabricating the same are provided. An exemplary embodiment of a phase change memory cell structure includes a first electrode formed over a first dielectric layer. A second dielectric layer is formed over the first electrode. A conductive member is formed through the second dielectric layer and electrically contacting the first electrode, wherein the conductive member comprises a lower element and an upper element sequentially stacking over the first electrode, and the lower and upper elements comprises different materials. A phase change material layer is formed over the second dielectric layer, electrically contacting the conductive member. A second electrode is formed over the phase change material layer. | 12-04-2008 |
20080293213 | METHOD FOR PREPARING A SHALLOW TRENCH ISOLATION - A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench. | 11-27-2008 |
20080290335 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers. | 11-27-2008 |
20080286936 | METHOD FOR PREPARING A SHALLOW TRENCH ISOLATION - A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench. | 11-20-2008 |
20080283891 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure comprises a first wafer and a second wafer, between which a glue layer can be used for combination. The first wafer comprises a first semiconductor cell structure, and a surface of the first wafer comprises conductive pads electrically connected to the first semiconductor cell structure. The second wafer comprises a second semiconductor cell structure and is bonded to the surface of the first wafer having the conductive pads. The first and second semiconductor cell structures are electrically connected through the conductive pads, and the conductive pads are formed around each die of the first wafer. The density of the first semiconductor cell structure in the first wafer is larger than the density of the second semiconductor cell structure in the second wafer. | 11-20-2008 |
20080283814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material. | 11-20-2008 |
20080283812 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element. The phase-change memory comprises first and second electrodes. A phase-change material layer is formed between the first and second electrodes. And a carbon-doped oxide dielectric layer is formed to surround the phase-change material layer, wherein the first electrode electrically connects the second electrodes via the phase-change material layer. | 11-20-2008 |
20080275578 | DATA COLLECTOR CONTROL SYSTEM WITH AUTOMATIC COMMUNICATION PORT SWITCH - A data collector control system for semiconductor manufacturing comprises a data collector and a automatic communication port switch control circuit. The control system is placed between an equipment and an equipment automation programming (EAP) system. The data collector processes and transmits communication messages between the equipment and the EAP system while the data collector operates normally. The communication messages between the equipment and the EAP system are transmitted through the control circuit instead of the data collector while the data collector operates abnormally. | 11-06-2008 |
20080272358 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer. | 11-06-2008 |
20080265311 | VERTICAL TRANSISTOR AND METHOD FOR PREPARING THE SAME - A vertical transistor comprises a substrate having a step structure, two doped regions positioned in the substrate at the two sides of the step structure, and a carrier channel positioned in the substrate between the two doped regions, wherein the step structure includes an inclined edge and the width of the carrier channel at the inclined edge is larger than the width of the doped regions. The step structure comprises two non-rectangular surfaces, such as the trapezoid or triangular surfaces, and a rectangular surface. The non-rectangular surfaces connect to the doped regions, and the rectangular surface is perpendicular to the non-rectangular surface. | 10-30-2008 |
20080265238 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto. | 10-30-2008 |
20080251826 | MULTI-LAYER SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a multi-layer semiconductor structure is disclosed. First, a first wafer comprising a first semiconductor device structure and a second wafer comprising a substrate and a single crystal silicon layer are provided, and the first and second wafers are combined in which a surface of the first wafer having the first semiconductor device structure is in contact with a surface of the second wafer having the single crystal silicon layer. A glue layer and a dielectric layer can be employed to combine the first and second wafers. Afterwards, a process for manufacturing a second semiconductor device structure is performed on the single crystal silicon layer. | 10-16-2008 |
20080251498 | PHASE CHANGE MEMORY DEVICE AND FABRICATIONS THEREOF - A method for forming a memory device is disclosed. A dielectric layer is formed on a substrate. A Sn doped phase change layer is formed on the dielectric layer. A patterned mask layer is formed on the Sn doped phase change layer. The Sn doped phase change layer is etched by an etchant comprising fluorine-based etchant added with chlorine using the patterned mask layer as a mask to pattern the Sn doped phase change layer. An electrode is formed, electrically connecting the patterned Sn doped phase change layer. | 10-16-2008 |
20080242096 | METHOD FOR PREPARING BOTTLE-SHAPED DEEP TRENCHES - A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to remove a portion of the substrate under the opening down to the interior of the insulation layer to form a trench, and a thermal treating process is then performed to form a second mask on the inner sidewall of the trench. Subsequently, a second etching process is performed to remove a portion of the substrate under the opening down to the interior of the first epitaxy layer to form a deep trench, and a third etching process is performed to remove a portion of the first epitaxy layer so as to form the bottle-shaped deep trench with an enlarged surface. | 10-02-2008 |
20080242023 | METHOD FOR PREPARING A METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A method for preparing a Metal-Oxide-Semiconductor (MOS) transistor comprises the steps of forming a gate oxide layer on a substrate, forming a gate and a first dielectric layer on the gate oxide layer, forming a second dielectric layer on the sidewall of the gate, forming a third dielectric layer covering the first and the second dielectric layers, performing a first etching process to remove a portion of the third dielectric layer and performing a second etching process to form a spacer on the sidewall of the gate. The etching selectivity of the first etching process to the third dielectric layer and to the second dielectric layer is different from that of the second etching process such that the thickness of the second dielectric layer at the center of the substrate is smaller than the thickness of the second dielectric layer at the edge of the substrate. | 10-02-2008 |
20080241741 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer. | 10-02-2008 |
20080239798 | Compensation circuit and memory with the same - One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal. | 10-02-2008 |
20080237562 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSi | 10-02-2008 |
20080233706 | MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY - A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench. | 09-25-2008 |
20080232670 | METHOD FOR CALCULATING A BAD-LOT CONTINUITY AND A METHOD FOR FINDING A DEFECTIVE MACHINE USING THE SAME - A method for finding a defective machine comprises the steps of selecting a searching period in which a plurality of wafer lots including good wafer lots and bad wafer lots passes through machines, acquiring a lot-passing information related to the passing sequence of the wafer lots through the machines, calculating a bad-lot continuity by taking the lot-passing information into account, and determining a defective machine by taking the bad-lot continuity into account. The bad-lot continuity is calculated by the steps of determining an impact period based on the aggregation degree of the bad wafer lots, calculating a bad-lot distribution probability in the impact period, and calculating the bad-lot continuity by taking the bad-lot distribution probability into account. | 09-25-2008 |
20080231636 | METHOD OF RECOGNIZING WAVEFORMS AND DYNAMIC FAULT DETECTION METHOD USING THE SAME - A dynamic fault detection method comprises the steps of acquiring a data curve from a machine, performing a waveform-recognition process to check if the data curve includes an effective waveform, performing a data-diagnosing process to check if the value of the effective waveform in an effective region falls outside a predetermined range, and generating an alarm signal if the value of the effective waveform in the effective region falls outside the predetermined range. The waveform-recognition process comprises the steps of checking if the data curve includes a first segment, a second segment and a third segment sandwiched between the first segment and the second segment, and checking if the length of the third segment is larger than a predetermined value. The waveform is determined to include the effective waveform if the checking results are true. | 09-25-2008 |
20080219046 | Writing method and system for a phase change memory - A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature. | 09-11-2008 |
20080213968 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes firstly providing a substrate. A doped first dielectric layer and an undoped second dielectric layer are then formed on the substrate sequentially. Next, many trenches are formed in the first and the second dielectric layers. Afterwards, an ion implantation process is performed in the largest space between the adjacent trenches to form an ion-implanted region in a portion of the second dielectric layer in upper parts of the trenches. A wet etching process is then performed to remove a portion of the second dielectric layer in the ion-implanted region and a portion of the first dielectric layer at bottoms of the trenches. Thereafter, a first conductive layer and a capacitor dielectric layer are formed sequentially on surfaces of the trenches. Finally, a second conductive layer is formed in the trenches. | 09-04-2008 |
20080203374 | Phase-change memory and fabrication method thereof - A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material. | 08-28-2008 |
20080197335 | Semiconductor device and fabrications thereof - A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure. | 08-21-2008 |