Princo Middle East FZE Patent applications |
Patent application number | Title | Published |
20160091864 | WRISTWATCH STRUCTURE WITH PHYSICAL HANDS AND METHOD FOR OFFERING COMMUNICATION FUNCTION TO WRISTWATCH - The present invention provides a wristwatch structure with physical hands and a method for offering a communication function to a wristwatch, which uses remaining room in a traditional wristwatch (such as a mechanical watch and a quartz watch) to dispose an electronic module. By way of wireless transmission, the electronic module is utilized to receive wireless signals transmitted from a device (such as a smart phone) near a wristwatch user, and to provide a prompt message (such as vibration or an audio sound) based on the wireless signals. The present invention gives a new function to the traditional wristwatch, and is also capable of solving the problem of prompt function not working in large-scale cell phone. | 03-31-2016 |
20150205361 | TIME ADJUSTING METHOD AND SYSTEM FOR WRISTWATCH - The present invention provides a time adjusting method and system for a time piece (such as a wristwatch), which utilizes a motion sensor disposed on the wristwatch to detect a hand gesture made by a user in the front of the wristwatch. In such a manner, adjusting the position of an indicator on the wristwatch is realized, and thereby carrying out the time adjustment. | 07-23-2015 |
20140328148 | WRISTWATCH STRUCTURE, ELECTRONIC CORE FOR WRISTWATCH, AND METHOD FOR MANUFACTURING WRISTWATCH - The present invention provides a wristwatch structure, an electronic core for a wristwatch, and a method for manufacturing the wristwatch. The wristwatch structure comprises: a dial; an indicator designed with the dial; an electric driving component connected to the indicator, for driving the indicator and actuating it; and an electronic core having an integrated circuit unit packaged therein, the electronic core also having a plurality of two-dimensional joints distributed on an external surface thereof, wherein the electric driving component is electrically connected to the integrated circuit unit of the electronic core via one set of joints among the two-dimensional joints. The present invention can improve compatibility for various designs, thereby shortening the product development cycle. | 11-06-2014 |
20140328147 | WRISTWATCH STRUCTURE, ELECTRONIC CROWN FOR WRISTWATCH, AND WRISTWATCH HAVING DISPLAY - The present invention provides a wristwatch structure, an electronic crown for wristwatch, and a wristwatch having a display. The wristwatch structure comprises an electric driving component; an electronic core having a plurality of two-dimensional joints; and an electronic crown comprising a rotating portion and a fixed detecting portion, the detecting portion detecting electronic signals according to a rotation of the rotating portion; wherein the detecting portion of the electronic crown exports the electronic signals to the electronic core via one of the joints, and the electric driving component is electrically connected to one set of joints among the two-dimensional joints. The present invention can improve compatibility for various designs, thereby shortening product development cycle. Also, the present invention is suitable for developing a product with appearance similar to a mechanical watch. | 11-06-2014 |
20140312490 | ELECTRICAL SYSTEM AND CORE MODULE THEREOF - Disclosed is a core module, comprising: a package substrate, having a plurality of pads; a first component, connected to the pads of the package substrate corresponding to the first component with a plurality of first joint parts; a second component, connected to the pads of the package substrate corresponding to the first component with a plurality of second joint parts; and a third component, connected to the pads of the package substrate corresponding to the third component with a plurality of third joint parts, wherein the first component is positioned above the second component relative to the lower package substrate, and the first component, the second component and the third component are all electrically connected via the package substrate, and a main molding material is molding the first component, the second component and the third component. | 10-23-2014 |
20140167803 | TESTING DEVICE AND TESTING METHOD THEREOF - Disclosed are a testing device and a testing method thereof. The testing device includes a frame, a flexible multi-layer substrate and at least one electrical testing point. The frame is positioned corresponding to a chip. At least one electrical connecting point is formed on a surface of the chip. The flexible multi-layer substrate is fixed in the frame. The electrical testing point is corresponding to the electrical connecting point and formed on an upper surface of the flexible multi-layer substrate for contacting the electrical connecting point and performing an electrical test to the chip. Furthermore, the electrical connecting point or the electrical testing point is a bump. | 06-19-2014 |
20140167255 | PACKAGE STRUCTURE AND PACKAGE METHOD - Disclosed are a package structure and a package method. The package structure comprises an IC bare die, having bare die pads formed on a surface; a flexible packaging substrate, having first pads formed on a first surface and second pads formed on a second surface; and a plurality of bumps, previously formed on the first surface of the flexible packaging substrate. The bumps have different heights, and correspond to the first pads and contact the bare die pads respectively. Pressing or heating is implemented to package the IC bare die. The package structure further comprises a printed circuit board, having a plurality of contact pads. The second pads of the flexible packaging substrate respectively contact with the contact pads via solders. Connection is implemented by pressing or heating. Extremely low stress is generated to the packaging substrate and the printed circuit board. | 06-19-2014 |
20140167244 | CHIP THERMAL DISSIPATION STRUCTURE - Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board. | 06-19-2014 |
20140162382 | PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, including: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate including at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced. | 06-12-2014 |
20130171751 | PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced. | 07-04-2013 |
20130171750 | PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced. | 07-04-2013 |
20130171749 | PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE - Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced. | 07-04-2013 |