MICRON TECHNOLOGY, INC. Patent applications |
Patent application number | Title | Published |
20160141495 | Memory Device Constructions, Memory Cell Forming Methods, and Semiconductor Construction Forming Methods - Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode. | 05-19-2016 |
20160141028 | REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS - Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing. | 05-19-2016 |
20160139813 | RE-BUILDING MAPPING INFORMATION FOR MEMORY DEVICES - Devices and methods storing user data along with a plurality of addresses corresponding to physical pages storing valid data corresponding to a logical data block are useful in re-building mapping information for the logical data block. | 05-19-2016 |
20160133717 | Transistors, Memory Cells and Semiconductor Constructions - Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate. | 05-12-2016 |
20160133670 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise a STT stack including: a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positioned between a ferromagnetic storage material and the pinned ferromagnetic material; a multiferroic material in contact with the ferromagnetic storage material; and a first electrode and a second electrode, wherein the antiferromagnetic material, the pinned ferromagnetic material, and the ferromagnetic storage material are located between the first electrode and the second electrode. The STT memory cell structure can include a third electrode and a fourth electrode, wherein at least a first portion of the multiferroic material is located between the third and the fourth electrode. | 05-12-2016 |
20160133327 | MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES - Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell. | 05-12-2016 |
20160118937 | APPARATUSES AND METHODS FOR PROVIDING OSCILLATION SIGNALS - Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a capacitance circuit is configured to be charged and discharged. Charging and discharging circuits are coupled to the capacitance circuit and configured to charge and discharge, respectively, the capacitance circuit by charging and discharging currents responsive to charge and discharge signals. A control circuit is coupled to the charging circuit and the discharging circuit, and is configured to provide the charge and discharge signals responsive to a voltage of the capacitance circuit, and is further configured to provide an oscillation signal responsive to the voltage of the capacitance circuit. The charging current, the discharging current, or both the charging and discharging currents are proportional to a difference between a first reference voltage and a second reference voltage. | 04-28-2016 |
20160118441 | Switching Components and Memory Units - Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior. | 04-28-2016 |
20160118119 | Memory Programming Methods and Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described. | 04-28-2016 |
20160118096 | APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES - Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition. | 04-28-2016 |
20160118087 | Memory Devices, Memory Device Operational Methods, and Memory Device Implementation Methods - Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data. | 04-28-2016 |
20160104716 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES - Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures. | 04-14-2016 |
20160093803 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells. | 03-31-2016 |
20160093708 | METHODS OF FORMING MEMORY CELLS - Memory cells having conductive nanodots between a charge storage material and a control gate are useful in non-volatile memory devices and electronic systems. | 03-31-2016 |
20160087071 | Methods of Forming Diodes - Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer. | 03-24-2016 |
20160087010 | Semiconductor Constructions, and Methods of Forming Cross-Point Memory Arrays - Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode. | 03-24-2016 |
20160087007 | Diode/Superionic Conductor/Polymer Memory Structure - A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode. | 03-24-2016 |
20160086672 | ACCESS LINE MANAGEMENT IN A MEMORY DEVICE - Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device. | 03-24-2016 |
20160071878 | Methods of Forming Semiconductor Constructions - Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions. | 03-10-2016 |
20160071842 | TRANSISTORS HAVING ONE OR MORE DUMMY LINES WITH DIFFERENT COLLECTIVE WIDTHS COUPLED THERETO - In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines. | 03-10-2016 |
20160071619 | METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY - Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array. | 03-10-2016 |
20160071605 | CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING DIFFERENT PAGE ADDRESSES - In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells. | 03-10-2016 |
20160071584 | OPERATIONAL SIGNALS GENERATED FROM CAPACITIVE STORED CHARGE - Methods, a memory device, and a system are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell. | 03-10-2016 |
20160070663 | SEQUENTIAL MEMORY ACCESS OPERATIONS - Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation. | 03-10-2016 |
20160070476 | OPERATION MANAGEMENT IN A MEMORY DEVICE - Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation. | 03-10-2016 |
20160064085 | MEMORY DEVICE HAVING A DIFFERENT SOURCE LINE COUPLED TO EACH OF A PLURALITY OF LAYERS OF MEMORY CELL ARRAYS - A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer. | 03-03-2016 |
20160062695 | NON-VOLATILE MEMORY WITH LPDRAM - Low power DRAM (LPDRAM) memory devices for communication with a non-volatile memory coupled to the LPDRAM memory device, and systems containing such LPDRAM and non-volatile memory facilitate configuring the LPDRAM memory device using routines stored on the non-volatile memory. | 03-03-2016 |
20160062683 | SUB-SECTOR WEAR LEVELING IN MEMORIES - Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. Transferring data from the third block to the first block excludes a sub-sector of the third block that is to be erased. | 03-03-2016 |
20160056073 | Semiconductor Constructions; and Methods for Providing Electrically Conductive Material Within Openings - Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner. | 02-25-2016 |
20160048338 | MEMORY BLOCK QUALITY IDENTIFICATION IN A MEMORY - Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in which a memory defect has been detected, wherein a value of the indication of memory block quality stored in a respective memory block of the plurality of memory blocks indicates a type of memory defect detected in the respective memory block, and, in response to the values of the indications of memory block quality, deeming a first portion of memory blocks of the plurality of memory blocks as usable, allocating a second portion of memory blocks of the plurality of memory blocks for storing only data of a particular type, and indicating a third portion of memory blocks of the plurality of memory blocks as defective. | 02-18-2016 |
20160048074 | METHODS OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a second photosensitive resist material, exposing portions of the first and second photosensitive resist materials to radiation, and removing the deprotected outer portion of the first photosensitive resist material and the exposed portions of the first and second photosensitive resist materials. Additional methods include forming a first resist material over a substrate to include a first portion and a relatively thicker second portion, deprotecting substantially the entire first portion and an outer portion of the second portion while leaving an inner portion of the second portion protected, and forming a second resist material over the substrate. A portion of the second resist material is exposed to radiation, and deprotected and exposed portions of the first and second resist materials are removed. | 02-18-2016 |
20160042995 | INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS AND THEIR FORMATION - An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass. | 02-11-2016 |
20160042799 | METHODS AND APPARATUS FOR SENSING A MEMORY CELL - Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line while a voltage level of the sense node is greater than a voltage level of the data line, and inhibiting discharging of the data line to the sense node while the voltage level of the data line is greater than the voltage level of the sense node. Sense circuits include a path between an input node and a sense node facilitating current flow from the sense node to the input node when a voltage level of the sense node is greater than a voltage level of the input node and inhibiting current flow from the input node to the sense node when the voltage level of the sense node is less than the voltage level of the input node. | 02-11-2016 |
20160027883 | Methods of Forming Charge-Trapping Regions - Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells. | 01-28-2016 |
20160027863 | Integrated Circuitry, Methods of Forming Capacitors, and Methods of Forming Integrated Circuitry Comprising an Array of Capacitors and Circuitry Peripheral to the Array - A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture. | 01-28-2016 |
20160027642 | Methods of Forming Capacitors - A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO | 01-28-2016 |
20160026564 | DETERMINING A LOCATION OF A MEMORY DEVICE IN A SOLID STATE DEVICE - A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation, configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices, and configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, the location in the memory device table identified by a remainder of the second division operation. | 01-28-2016 |
20160019949 | PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL - Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal. | 01-21-2016 |
20160005968 | Memory Structures and Arrays, and Methods of Forming Memory Structures and Arrays - Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures. | 01-07-2016 |
20160005815 | Semiconductor Constructions - Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X. | 01-07-2016 |
20160005742 | Semiconductor Constructions, and Semiconductor Processing Methods - Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions. | 01-07-2016 |
20160005474 | MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF - An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line. | 01-07-2016 |
20160005473 | PROGRAMMING OF MEMORY DEVICES - Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage. | 01-07-2016 |
20160005467 | COMMAND SIGNAL MANAGEMENT IN INTEGRATED CIRCUIT DEVICES - Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal. | 01-07-2016 |
20160005442 | Memory Programming Methods and Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described. | 01-07-2016 |
20150380091 | METHODS OF PROGRAMMING MEMORIES - Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation. | 12-31-2015 |
20150372227 | MEMORY CELLS - Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the second electrode. The second electrode comprises a plurality of portions of material, each portion having a respective distance from the surface of the phase change material and each portion having a respective resistivity. A portion of the plurality of portions of material farthest from the surface of the phase change material has a lowest resistivity and a portion of the plurality of portions of material closest to the surface of the phase change material has a highest resistivity. The resistivity of each individual portion is lower than the resistivity of each portion located closer to the surface of the phase change material, and higher than the resistivity of each portion located farther from the surface of the phase change material. | 12-24-2015 |
20150371706 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state. | 12-24-2015 |
20150364557 | GETTERING AGENTS IN MEMORY CHARGE STORAGE STRUCTURES - Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material. | 12-17-2015 |
20150364483 | CONDUCTORS HAVING A VARIABLE CONCENTRATION OF GERMANIUM FOR GOVERNING REMOVAL RATES OF THE CONDUCTOR DURING CONTROL GATE FORMATION - An embodiment of a method of forming a control gate includes forming a conductor having a concentration of germanium that varies with a thickness of the conductor, and removing portions of the conductor at a variable rate that is governed, at least in part, by the concentration of the germanium. | 12-17-2015 |
20150364214 | RECLAIMABLE SEMICONDUCTOR DEVICE PACKAGE AND ASSOCIATED SYSTEMS AND METHODS - Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly ( | 12-17-2015 |
20150364213 | PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS - Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current. | 12-17-2015 |
20150363313 | SENSE OPERATION FLAGS IN A MEMORY DEVICE - Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page. | 12-17-2015 |
20150363120 | ON DEMAND BLOCK MANAGEMENT - Methods and memories for embedded systems, and systems with managed memories, are provided. In one such method, a managed memory determines when housekeeping operations are indicated, conveys that information to a host, and the host initiates the housekeeping operation at a time determined by the host not to affect real-time system operation. | 12-17-2015 |
20150357380 | Memory Arrays With Polygonal Memory Cells Having Specific Sidewall Orientations - Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays. | 12-10-2015 |
20150357049 | SHORT-CHECKING METHODS - In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage. | 12-10-2015 |
20150357031 | PROGRAMMING MEMORIES WITH STEPPED PROGRAMMING PULSES - Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level. | 12-10-2015 |
20150355849 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 12-10-2015 |
20150355844 | REMAPPING IN A MEMORY DEVICE - Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device. | 12-10-2015 |
20150349255 | Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells - An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed. | 12-03-2015 |
20150349126 | FIELD EFFECT TRANSISTORS HAVING A FIN - An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions. | 12-03-2015 |
20150348989 | MEMORY ARRAY WITH A PAIR OF MEMORY-CELL STRINGS TO A SINGLE CONDUCTIVE PILLAR - An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory cell has a respective portion of a first charge trap adjacent to the conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap. Each second memory cell has a respective portion of a second charge trap adjacent to the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap. Each first control gate is electrically isolated from each second control gate. A single select transistor may selectively couple the plurality of first memory cells and the plurality of second memory cells to one of a source line and a data line. | 12-03-2015 |
20150348954 | INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. | 12-03-2015 |
20150348647 | VIA STACK FAULT DETECTION - A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack. | 12-03-2015 |
20150348643 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE - A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window. | 12-03-2015 |
20150348599 | PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY - The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information. | 12-03-2015 |
20150347307 | CACHE ARCHITECTURE - The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request. | 12-03-2015 |
20150347038 | APPARATUSES AND METHODS FOR PERFORMING WEAR LEVELING OPERATIONS - Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation. | 12-03-2015 |
20150341021 | APPARATUSES, METHODS, AND CIRCUITS INCLUDING A DUTY CYCLE ADJUSTMENT CIRCUIT - Apparatuses, methods, and duty cycle correction circuits are described. An example apparatus includes a duty cycle correction (DCC) adjustment circuit configured to receive an input signal, and to adjust a duty cycle of the input signal to provide an output signal. The DCC circuit including a coarse adjust control circuit configured to adjust the duty cycle of the input signal by a first amount that is equal to one or more unit adjustments, and a fine adjust control circuit that is configured to adjust the duty cycle of the input signal responsive to a pulse signal by a second amount that is less than the unit adjustment. | 11-26-2015 |
20150340408 | PHASE CHANGE MEMORY APPARATUSES AND METHODS OF FORMING SUCH APPARATUSES - Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between the memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses. | 11-26-2015 |
20150340372 | POLAR, CHIRAL, AND NON-CENTRO-SYMMETRIC FERROELECTRIC MATERIALS, MEMORY CELLS INCLUDING SUCH MATERIALS, AND RELATED DEVICES AND METHODS - A ferroelectric memory device includes a plurality of memory cells. Each of the memory cells comprises at least one electrode and a ferroelectric crystalline material disposed proximate the at least one electrode. The ferroelectric crystalline material is polarizable by an electric field capable of being generated by electrically charging the at least one electrode. The ferroelectric crystalline material comprises a polar and chiral crystal structure without inversion symmetry through an inversion center. The ferroelectric crystalline material does not consist essentially of an oxide of at least one of hafnium (Hf) and zirconium (Zr). | 11-26-2015 |
20150340328 | METHODS OF FORMING SEMICONDUCTOR DEVICE ASSEMBLIES AND INTERCONNECT STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE ASSEMBLIES AND INTERCONNECT STRUCTURES - A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described. | 11-26-2015 |
20150340311 | SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED ON SUBSTRATE - A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. The first pitch is determined to be larger than the second pitch. | 11-26-2015 |
20150340209 | FOCUS RING REPLACEMENT METHOD FOR A PLASMA REACTOR, AND ASSOCIATED SYSTEMS AND METHODS - A focus ring replacement method for a plasma reactor, and associated systems and methods are disclosed herein. In one embodiment, a plasma processing system includes a plasma reactor and a wafer handler. The plasma reactor includes a processing chamber defining an enclosure and having a chamber opening accessible to the enclosure. A wafer holder assembly is positioned within the enclosure and configured to hold a semiconductor wafer and a focus ring that surrounds the semiconductor wafer. The wafer handler is configured to transport the focus ring through the chamber opening, and the wafer holder assembly is further configured to transfer the focus ring between the wafer handler and the wafer holder assembly. | 11-26-2015 |
20150340086 | THRESHOLD VOLTAGE ANALYSIS - Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells. | 11-26-2015 |
20150340072 | APPARATUSES AND METHODS FOR TIMING PROVISION OF A COMMAND TO INPUT CIRCUITRY - Apparatuses and methods for providing a command to a data block are described. An example apparatus includes a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain. The example apparatus further includes a command path delay configured to delay the command signal. The example apparatus further includes a data strobe generator circuit configured to receive the command signal and a data strobe signal. A plurality of clock edges of the data strobe signal correspond to received data bits associated with the memory access command. The data strobe generator circuit is configured to control input circuitry to capture the data associated with the memory access command based at least in part on the data strobe signal and the command signal. | 11-26-2015 |
20150340069 | DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS - An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit. | 11-26-2015 |
20150339064 | READ CACHE MEMORY - The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array. | 11-26-2015 |
20150333143 | Memory Arrays - Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures. | 11-19-2015 |
20150333026 | INTERCONNECT STRUCTURE WITH IMPROVED CONDUCTIVE PROPERTIES AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member. | 11-19-2015 |
20150333014 | SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT - Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device. | 11-19-2015 |
20150332913 | Semiconductor Processing Methods, and Methods for Forming Silicon Dioxide - Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region laterally outward of said inner region, and may have a deposition surface that extends across the inner and outer regions. The semiconductor substrate may be heated by radiating thermal energy from the outer region to the inner region. The heating may eventually achieve thermal equilibrium. However, before thermal equilibrium of the outer and inner regions is reached, and while the outer region is warmer than the inner region, at least two reactants are sequentially introduced into the reaction chamber. The reactants may together form a single composition on the deposition surface through a quasi-ALD process. | 11-19-2015 |
20150332740 | APPARATUSES AND METHODS FOR ACCESSING MEMORY INCLUDING SENSE AMPLIFIER SECTIONS AND COUPLED SOURCES - Apparatuses and methods for accessing memory are described. An example method includes accessing memory cells of a memory section, and sharing a source of an inactive sense amplifier section with an active sense amplifier section coupled to the memory cells of the memory section during a memory access operation to the memory section coupled to the active sense amplifier section. An example apparatus includes a memory section and a first sense amplifier section associated with the memory section. The first sense amplifier section includes a sense amplifier and includes a read/write circuit coupled to a first source associated with the first sense amplifier section. The source associated with the first sense amplifier section is coupled to a source associated with a second sense amplifier section. The second sense amplifier section is configured to be inactive during a memory access operation to the memory section. | 11-19-2015 |
20150331811 | SECURE COMPACT FLASH - Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area configured to store a user password and a serial number in encrypted form. The card is configured to grant access to the secure area when the card receives a password that matches the stored user password and the card is coupled to a system having the serial number. | 11-19-2015 |
20150331792 | MEMORY DEVICES WITH REGISTER BANKS STORING ACTUATORS THAT CAUSE OPERATIONS TO BE PERFORMED ON A MEMORY CORE - A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit. | 11-19-2015 |
20150325589 | Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures - Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures. | 11-12-2015 |
20150325289 | APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS - The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase. | 11-12-2015 |
20150325288 | APPARATUSES AND METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS - The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array. | 11-12-2015 |
20150318468 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner. | 11-05-2015 |
20150318467 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner. | 11-05-2015 |
20150318047 | MEMORY DEVICES CONFIGURED TO APPLY DIFFERENT WEIGHTS TO DIFFERENT STRINGS OF MEMORY CELLS COUPLED TO A DATA LINE AND METHODS - Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells. | 11-05-2015 |
20150318038 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall. | 11-05-2015 |
20150316969 | APPARATUSES SUPPORTING MULTIPLE INTERFACE TYPES AND METHODS OF OPERATING THE SAME - Apparatuses supporting multiple interface types and methods operating the same are described. One such method can include providing, to a memory device, a first input/output (I/O) supply voltage corresponding to a first interface type and subsequently determining whether the memory device supports a second interface type having a second I/O supply voltage corresponding thereto. In response to a determination that the memory device supports the second interface type, the method can include adjusting the I/O supply voltage provided to the memory device from the first I/O supply voltage to the second I/O supply voltage. | 11-05-2015 |
20150311437 | METHODS OF FORMING A MEMORY CELL MATERIAL, AND RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE, MEMORY CELL MATERIALS, AND SEMICONDUCTOR DEVICE STRUCTURES - A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described. | 10-29-2015 |
20150311349 | Ferroelectric Field Effect Transistors, Pluralities Of Ferroelectric Field Effect Transistors Arrayed In Row Lines And Column Lines, And Methods Of Forming A Plurality Of Ferroelectric Field Effect Transistors - A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed. | 10-29-2015 |
20150311217 | FERROELECTRIC MEMORY AND METHODS OF FORMING THE SAME - Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD. | 10-29-2015 |
20150311186 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH DIE SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die. | 10-29-2015 |
20150311185 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH SUPPORT MEMBERS AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die. | 10-29-2015 |
20150311115 | Methods of Forming Memory Arrays - Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry. | 10-29-2015 |
20150310905 | Field Effect Transistor Constructions And Methods Of Programming Field Effect Transistors To One Of At Least Three Different Programmed States - A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed. | 10-29-2015 |
20150309741 | APPARATUSES AND METHODS FOR MEMORY MANAGEMENT - Some embodiments include apparatuses and methods to select a target memory portion in a first memory location to store information. One such method can conditionally store the information in a second memory location when the information is stored in the target memory portion. Other embodiments are described. | 10-29-2015 |
20150303372 | MEMORY CELLS, METHODS OF FABRICATION, AND SEMICONDUCTOR DEVICES - A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. In some embodiments, the seed material is formed adjacent to an amorphous foundation material that enables the seed material to be formed at the hexagonal crystal structure. In some embodiments, the magnetic cell includes hexagonal cobalt (h-Co) free and fixed regions and a hexagonal boron nitride (h-BN) tunnel barrier region with a hexagonal zinc (h-Zn) seed region adjacent the h-Co. The structure of the magnetic cell enables high tunnel magnetoresistance, high magnetic anisotropy strength, and low damping. Methods of fabrication and semiconductor devices are also disclosed. | 10-22-2015 |
20150303206 | Methods Of Forming Ferroelectric Capacitors - A method of forming a ferroelectric capacitor includes forming inner conductive capacitor electrode material over a substrate. After forming the inner electrode material, an outermost region of the inner electrode material is treated to increase carbon content in the outermost region from what it was prior to the treating. After the treating, ferroelectric capacitor dielectric material is formed over the treated outermost region of the inner electrode material. Outer conductive capacitor electrode material is formed over the ferroelectric capacitor dielectric material. | 10-22-2015 |
20150302907 | APPARATUSES AND METHODS FOR IMPLEMENTING MASKED WRITE COMMANDS - Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein. | 10-22-2015 |
20150302898 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region. | 10-22-2015 |
20150301937 | WEAR LEVELING FOR A MEMORY DEVICE - Methods of operating a memory device are useful in managing wear leveling operations. Such methods include receiving an instruction from a host device in communication with the memory device, wherein the instruction comprises a command portion indicating a desire to identify portions of the memory device to be excluded from wear leveling operations and an argument portion comprising information identifying a particular group of one or more blocks of the plurality of blocks; storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operation | 10-22-2015 |
20150301283 | METHOD AND APPARATUS PROVIDING COMPENSATION FOR WAVELENGTH DRIFT IN PHOTONIC STRUCTURES - A method and apparatus are described which provide for wavelength drift compensation in a photonic waveguide by application of an electric field to a waveguide having a strained waveguide core. | 10-22-2015 |
20150295173 | Integrated Memory and Methods of Forming Repeating Structures - Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. Some embodiments include methods of forming repeating structures. A pattern is formed which includes a lattice of intersecting wavy lines and a box surrounding the lattice. The pattern has a plurality of openings extending therethrough. A liner material is along sidewalls of the openings. The liner material and the pattern are sliced along a row direction and a column direction substantially orthogonal to the row direction. Such slicing subdivides the liner material into a plurality of plates. The plates are within an array comprising columns and rows. The plates along individual columns and individual rows alternate between two orientations which are substantially orthogonal to one another. | 10-15-2015 |
20150295164 | MEMORY CELLS, SEMICONDUCTOR STRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF FABRICATION - A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attracter species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed. | 10-15-2015 |
20150294940 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING SEMICONDUCTOR DEVICES - Semiconductor devices may include a substrate and a semiconductor die on the substrate. The semiconductor die may include an active surface and a lateral edge at a periphery of the active surface. An electrically insulating material may be located on the active surface proximate the lateral edge. The electrically insulating material may be distinct from any other material located on the active surface. A wire bond may extend from the active surface, over the electrically insulating material, to the substrate. Methods of making semiconductor devices may involve positioning an electrically insulating material on an active surface of a semiconductor die proximate a lateral edge at a periphery of an active surface. After positioning the electrically insulating material on the active surface, a wire bond extending from the active surface, over the electrically insulating material, to the substrate may be formed. | 10-15-2015 |
20150294727 | SENSING MEMORY CELLS COUPLED TO DIFFERENT ACCESS LINES IN DIFFERENT BLOCKS OF MEMORY CELLS - In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells. | 10-15-2015 |
20150294716 | APPARATUSES AND METHODS OF READING MEMORY CELLS - The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse. | 10-15-2015 |
20150287916 | SEMICONDUCTOR STRUCTURES INCLUDING MULTI-PORTION LINERS AND RELATED METHODS - A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion. | 10-08-2015 |
20150287825 | Transistors - Some embodiments include a construction having a second semiconductor material over a first semiconductor material. A region of the second semiconductor material proximate the first semiconductor material has strain due to different lattice characteristics of the first and second semiconductor materials. A transistor gate extends downwardly into the second semiconductor material. Gate dielectric material is along sidewalls and a bottom of the transistor gate. Source/drain regions are along the sidewalls of the transistor gate, and the gate dielectric material is between the source/drain regions and the transistor gate. A channel region extends between the source/drain regions and is under the bottom of the transistor gate. At least some of the channel region is within the strained region. | 10-08-2015 |
20150287687 | SEMICONDUCTOR STRUCTURES INCLUDING CARRIER WAFERS AND METHODS OF USING SUCH SEMICONDUCTOR STRUCTURES - A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed. | 10-08-2015 |
20150287480 | SOFT POST PACKAGE REPAIR OF MEMORY DEVICES - Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus. | 10-08-2015 |
20150286593 | APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS - Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition. | 10-08-2015 |
20150283563 | Device for Controlling Placement of Nanoparticles - The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target. | 10-08-2015 |
20150280118 | REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY - Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material. | 10-01-2015 |
20150280117 | Memory Arrays and Methods of Forming Memory Arrays - Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays. | 10-01-2015 |
20150279906 | Memory Arrays - Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays. | 10-01-2015 |
20150279828 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate. | 10-01-2015 |
20150279694 | DRAM Cells and Methods of Forming Silicon Dioxide - Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells. | 10-01-2015 |
20150279432 | MEMORY DEVICES WITH LOCAL AND GLOBAL DEVICES AT SUBSTANTIALLY THE SAME LEVEL ABOVE STACKED TIERS OF MEMORY CELLS AND METHODS - In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices. | 10-01-2015 |
20150279431 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies. | 10-01-2015 |
20150270851 | LOW DENSITY PARITY CHECK CIRCUIT - Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration. | 09-24-2015 |
20150270480 | MEMORY CELLS HAVING A SELF-ALIGNING POLARIZER - Spin torque transfer memory cells and methods of forming the same are described herein. As an example, spin torque transfer memory cells may include a self-aligning polarizer, a pinned polarizer, and a storage material formed between the self-aligning polarizer and the pinned polarizer. | 09-24-2015 |
20150270015 | MEMORY MAPPING - The present disclosure includes apparatuses, electronic device readable media, and methods for memory mapping. One example method can include testing a memory identifier against an indication corresponding to a set of mapped memory identifiers, and determining a memory location corresponding to the memory identifier responsive to testing. | 09-24-2015 |
20150268875 | APPARATUSES AND METHODS HAVING MEMORY TIER STRUCTURE - Some embodiments include apparatuses and methods having a memory unit and a controller device. The controller device can be configured to receive a request from a host device and access a data structure in the memory unit to determine whether information associated with the request is in the data structure. The controller device can be configured such that if a fault related to accessing the data structure occurs, the controller device continues searching for the information associated with the request without notifying the host device of the fault. | 09-24-2015 |
20150262716 | METHODS OF OPERATING MEMORY INVOLVING IDENTIFIERS INDICATING REPAIR OF A MEMORY CELL - Method of operating memory including storing and/or using an identifier indicating repair of a memory cell. | 09-17-2015 |
20150262657 | TWO-PART PROGRAMMING METHODS - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used. | 09-17-2015 |
20150255478 | APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES - Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge. | 09-10-2015 |
20150249383 | CHARGE PUMP - One charge pump includes at least one delay element, a number of inverters, and a flip flop coupled in series, with an output of one inverter coupled in a feedback loop to one of the delay elements. The charge pump monitors a first supply voltage level, and turns off an oscillator of the charge pump when the first supply voltage drops below a certain level. This is accomplished in one embodiment by monitoring a first supply voltage level supplied to a charge pump, and turning off an oscillator of the charge pump when the first supply voltage drops below a certain level. | 09-03-2015 |
20150249202 | MEMORY CELLS, METHODS OF FABRICATION, AND SEMICONDUCTOR DEVICES - A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusible species and at least one other species. An oxide region is disposed between the magnetic region and another magnetic region, and an amorphous region is proximate to the magnetic region. The amorphous region comprises an attracter material that has a chemical affinity for the diffusible species that is higher than a chemical affinity of the at least one other species for the diffusible species. Thus, the diffusible species is transferred from the precursor magnetic material to the attracter material, forming a depleted magnetic material. The removal of the diffusible species and the amorphous nature of the region of the attracter material promotes crystallization of the depleted magnetic material, which enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed. | 09-03-2015 |
20150249092 | MEMORY ARRAYS WITH A MEMORY CELL ADJACENT TO A SMALLER SIZE OF A PILLAR HAVING A GREATER CHANNEL LENGTH THAN A MEMORY CELL ADJACENT TO A LARGER SIZE OF THE PILLAR AND METHODS - The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size. | 09-03-2015 |
20150243885 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls. | 08-27-2015 |
20150243782 | Transistor-Containing Constructions and Memory Arrays - Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays. | 08-27-2015 |
20150243734 | Methods of Forming Transistors - Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate. | 08-27-2015 |
20150243709 | SEMICONDUCTOR STRUCTURES INCLUDING LINERS COMPRISING ALUCONE AND RELATED METHODS - A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed. | 08-27-2015 |
20150243708 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials. | 08-27-2015 |
20150243583 | INTERCONNECT ASSEMBLIES WITH THROUGH-SILICON VIAS AND STRESS-RELIEF FEATURES - A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap. | 08-27-2015 |
20150236259 | Switching Components and Memory Units - Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior. | 08-20-2015 |
20150235841 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING ALUMINUM OXIDE - A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. The aluminum oxide overlies the dielectric material in a first region of the structure. A second region of the structure includes a first titanium nitride portion overlying the dielectric material, magnesium over the first titanium nitride portion, and a second titanium nitride portion over the magnesium. Methods of forming the semiconductor structure including aluminum oxide are also disclosed. | 08-20-2015 |
20150235691 | METHODS AND APPARATUSES FOR CONTROLLING TIMING PATHS AND LATENCY BASED ON A LOOP DELAY - Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command. | 08-20-2015 |
20150235677 | POWER MANAGEMENT - Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include providing a clock signal, counting primary clock cycles of the clock signal in a counter, monitoring an indication of high current demand for each die of the multi-die package, and determining a total unit consumption of current. The method may further include pausing an access operation for a particular die of the multi-die package at a designated point, and resuming the access operation if a value of the total unit consumption is less than or equal to a unit limit when a count value of the counter matches an assigned counter value of the particular die | 08-20-2015 |
20150234601 | COMMAND QUEUING - The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host. | 08-20-2015 |
20150228659 | DATA LINE ARRANGEMENT AND PILLAR ARRANGEMENT IN APPARATUSES - Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). | 08-13-2015 |
20150228317 | APPARATUSES, MEMORIES, AND METHODS FOR FACILITATING SPLITTING OF INTERNAL COMMANDS USING A SHARED SIGNAL PATH - Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a command circuit is configured to receive a command and an indicator signal. A lockout circuit is coupled to the command circuit and configured to give precedence to a chosen command type by masking the indicator signal. In another example, a counter circuit is coupled to the lockout circuit and configured to force the lockout circuit to sample the indicator signal at regular intervals. | 08-13-2015 |
20150227441 | CORRECTING RECURRING ERRORS IN MEMORY - The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first subset of a group of memory cells has a recurring error associated therewith using a second subset of the group of memory cells, and responsive to a determination that the first subset of the group of memory cells has a recurring error associated therewith, correcting the recurring error using the second subset of the group of memory cells. | 08-13-2015 |
20150221612 | THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS - Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. | 08-06-2015 |
20150221540 | DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING - Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates. | 08-06-2015 |
20150221384 | METHODS OF OPERATING MEMORY DEVICES - Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells. | 08-06-2015 |
20150221378 | PROGRAM AND READ TRIM SETTING - A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability. | 08-06-2015 |
20150221355 | APPARATUSES AND METHODS TO DELAY MEMORY COMMANDS AND CLOCK SIGNALS - An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals. | 08-06-2015 |
20150221347 | METHODS AND APPARATUSES INCLUDING AN ASYMMETRIC ASSIST DEVICE - Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection. | 08-06-2015 |
20150220386 | DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS - The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface. | 08-06-2015 |
20150220344 | Memory Systems and Memory Control Methods - Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction. | 08-06-2015 |
20150213872 | APPARATUSES AND METHODS FOR ADDRESS DETECTION - Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count. | 07-30-2015 |
20150213862 | MEMORY DECODING - Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. The sense circuitry is configured to selectively activate the gate responsive to a third control signal. | 07-30-2015 |
20150213848 | METHODS AND APPARATUSES FOR PROVIDING A PROGRAM VOLTAGE RESPONSIVE TO A VOLTAGE DETERMINATION - Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage. | 07-30-2015 |
20150206906 | MEMORIES AND METHODS OF FORMING THIN-FILM TRANSISTORS USING HYDROGEN PLASMA DOPING - Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled. | 07-23-2015 |
20150206813 | METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES - Methods of processing a semiconductor device include attaching a semiconductor substrate to a carrier substrate, forming a silane material over an exposed portion of the carrier substrate, and curing the silane material to form a hydrophobic coating over the carrier substrate. The hydrophobic coating may reduce or prevent undercut of the semiconductor substrate due to wicking of adhesive from between the semiconductor substrate and the carrier substrate during processing. The silane material includes a compound having a chemical formula of (XO) | 07-23-2015 |
20150206592 | METHODS OF OPERATING A MEMORY DEVICE HAVING A BURIED BOOSTING PLATE - Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed. | 07-23-2015 |
20150206587 | METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY - Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors. | 07-23-2015 |
20150203754 | COMPOSITIONS FOR ETCHING POLYSILICON - Compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride. | 07-23-2015 |
20150202566 | METHODS AND APPARATUS FOR TREATING FLUORINATED GREENHOUSE GASES IN GAS STREAMS - A method for removing fluorinated greenhouse gas from a gas stream comprises reacting at least one fluorinated greenhouse gas in a gas stream with at least one of a silane-based and a borane-based compound to provide an abated gas stream. An apparatus for removing fluorinated greenhouse gases from a gas stream comprises a fluorinated gas decomposer unit configured to decompose fluorinated greenhouse gases in a gas stream. The apparatus further comprises a silane-based or a borane-based compound introduction unit configured to introduce at least one of a silane-based and a borane-based compound into the fluorinated gas decomposer unit. | 07-23-2015 |
20150200202 | FIELD EFFECT TRANSISTOR CONSTRUCTIONS AND MEMORY ARRAYS - A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed. | 07-16-2015 |
20150194983 | READ THRESHOLD CALIBRATION FOR LDPC - Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified. | 07-09-2015 |
20150194961 | Level Shifters, Memory Systems, and Level Shifting Methods - Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices. | 07-09-2015 |
20150194478 | Capacitors and Methods of Forming Capacitors - A method of forming a capacitor includes forming an elevationally elongated and elevationally inner capacitor electrode that comprises different composition laterally-outermost and laterally-innermost conductive portions that have different respective intrinsic residual mechanical stress. The innermost conductive portion is formed to have greater mechanical stress in the compressive direction than the outermost conductive portion. A capacitor dielectric is formed over the inner capacitor electrode and an elevationally outer capacitor electrode is formed over the capacitor dielectric. A capacitor construction independent of the method formed is disclosed. | 07-09-2015 |
20150194430 | SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACCESS DEVICE AND METHODS OF FORMING SAME - A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides. | 07-09-2015 |
20150194321 | Methods of Processing Polysilicon-Comprising Compositions - A method of processing a polysilicon-comprising composition comprises forming a first wall comprising at least one recess in polysilicon. A second wall comprising polysilicon is formed. Material other than polysilicon is deposited within the at least one recess and over the polysilicon of the second wall. The material is etched selectively relative to polysilicon to expose polysilicon of the second wall and to leave the material within the at least one recess in the first wall. The exposed polysilicon of the second wall is etched selectively relative to the material within the at least one recess in the first wall. Other methods are disclosed. | 07-09-2015 |
20150194316 | NANOSTRUCTURES HAVING LOW DEFECT DENSITY AND METHODS OF FORMING THEREOF - A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm. | 07-09-2015 |
20150194212 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic. | 07-09-2015 |
20150194191 | Memory Devices, Memory Device Operational Methods, and Memory Device Implementation Methods - Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data. | 07-09-2015 |
20150192514 | Scatterometry Metrology Methods And Methods Of Modeling Formation Of A Vertical Region Of A Multilayer Semiconductor Substrate To Comprise A Scatterometry Target - A scatterometry target formed relative to an elevationally outermost surface of a substrate includes features having an optical property that is different from that of spaces between the features. The substrate has spaced-apart parallel elongated blocking lines having an optical property different from that of spaces between the blocking lines. The blocking lines are elevationally inward of the target features. The target features and the blocking lines overlap within a same vertical region of the substrate. Polarized electromagnetic radiation having multiple wavelengths is impinged onto the scatterometry target. Pitch of the blocking lines is less than the smallest wavelength of the impinged radiation. The blocking lines reduce spectrum variation to below a detectable level for any polarized electromagnetic radiation passing to elevationally inward of the blocking lines. Electromagnetic radiation that is reflected from the scatterometry target from the impinging is detected, and therefrom a property associated with the target features and/or spaces between the target features is determined. | 07-09-2015 |
20150179493 | METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES - Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass-transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater. | 06-25-2015 |
20150179467 | Methods of Forming Patterns - Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material. | 06-25-2015 |
20150179256 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline. | 06-25-2015 |
20150179255 | VOLTAGE STABILIZING FOR A MEMORY CELL ARRAY - Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled to a row of a memory array to provide voltage to the row of the memory array, activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, and activating a driving node coupled to a column of the memory array, wherein activating the driving node deactivates the stabilizing transistor once the column reaches a particular voltage potential. | 06-25-2015 |
20150179253 | APPARATUSES, MEMORIES, AND METHODS FOR ADDRESS DECODING AND SELECTING AN ACCESS LINE - Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level. | 06-25-2015 |
20150162090 | SENSING MEMORY CELLS COUPLED TO DIFFERENT ACCESS LINES IN DIFFERENT BLOCKS OF MEMORY CELLS - In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells. | 06-11-2015 |
20150160874 | INTEGRITY OF AN ADDRESS BUS - A memory device has a controller, an address integrity feature, and an address register. The controller is configured to store error correction data in the address register when the address integrity feature is enabled. | 06-11-2015 |
20150155855 | APPARATUSES AND METHODS FOR DUTY CYCLE ADJUSTMENTS - Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be coupled to a node between two adjacent gates of the plurality of gates and controlled responsive to a first control signal. A second pull-down circuit can be coupled to an output of one of the gates and controlled responsive to a second control signal. A duty cycle of a signal provided by the plurality of gates can be increased responsive to the first control signal and can be decreased responsive to the second control signal. The plurality of gates and the first and second pull-down circuits can make up a duty cycle adjuster circuit that can adjust the duty cycle of the signal by adjusting only a single type of edges of the signal. | 06-04-2015 |
20150155285 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region. | 06-04-2015 |
20150153963 | METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY - A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device. | 06-04-2015 |
20150149712 | TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication. | 05-28-2015 |
20150146494 | PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY - Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2 | 05-28-2015 |
20150146472 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state. | 05-28-2015 |
20150140753 | Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells - Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening. | 05-21-2015 |
20150137365 | SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES AND METHODS - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. | 05-21-2015 |
20150137353 | UNDER-BUMP METAL STRUCTURES FOR INTERCONNECTING SEMICONDUCTOR DIES OR PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die. | 05-21-2015 |
20150137061 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction. | 05-21-2015 |
20150135038 | POST PACKAGE REPAIR OF MEMORY DEVICES - Apparatuses and methods for post package repair are disclosed. An apparatus can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells. | 05-14-2015 |
20150135027 | DETERMINING AN AGE OF DATA STORED IN MEMORY - The present disclosure includes apparatuses and methods for determining an age of data stored in memory. A number of embodiments include determining a sensing voltage that results in a particular error rate being associated with a sense operation performed on a memory using the sensing voltage, determining a difference between the determined sensing voltage and a program verify voltage associated with the memory, and determining an age of data stored in the memory based on the determined difference. | 05-14-2015 |
20150134927 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L. | 05-14-2015 |
20150134713 | DIVSION OPERATIONS FOR MEMORY - Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells. | 05-14-2015 |
20150129955 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME - A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed. | 05-14-2015 |
20150123189 | METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL - Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material. | 05-07-2015 |
20150123188 | METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS INCLUDING A METAL SOURCE - Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material. | 05-07-2015 |