International Businesss Machines Corporation Patent applications |
Patent application number | Title | Published |
20130339917 | AUTOMATING CURRENT-AWARE INTEGRATED CIRCUIT AND PACKAGE DESIGN AND OPTIMIZATION - A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 12-19-2013 |
20120230654 | LABELING A VIDEO, FOR MODIFYING A VIDEO, AND FOR VIDEO PROCESSING - A computer program product for processing a video having a plurality of objects is provided. The computer program product includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code is configured for labeling at least one object among the plurality of objects with a property selected from the group consisting of: whether the object can be modified; whether the object can be replaced; and at least one of: name, color, size, and content. The computer readable program code is configured for replacing the at least one object with another object having a property matching therewith if the object has been labeled as one that can be replaced. The computer readable program code is configured for modifying the at least one object to obtain a new object if the object has been labeled as one that can be modified. | 09-13-2012 |
20100028801 | LITHOGRAPHY FOR PITCH REDUCTION - In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch. | 02-04-2010 |
20080209296 | Clock and Data Recovery System and Method for Clock and Data Recovery Based on a Forward Error Correction - The forward error correction based clock and data recovery system includes a data latch for intermediately storing received data, which is triggered by a sampling clock. The system further includes an error determination unit for determining whether which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal. Furthermore, the system includes a clock generator for generating the sampling clock depending on the correction signal. | 08-28-2008 |