INTERNATIONAL BUSINESS CORPORATION Patent applications |
Patent application number | Title | Published |
20150145010 | DYNAMIC RANDOM ACCESS MEMORY CELL EMPLOYING TRENCHES LOCATED BETWEEN LENGTHWISE EDGES OF SEMICONDUCTOR FINS - After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor. | 05-28-2015 |
20140337111 | REWARDING ONLINE ADVOCATES - A method and associated systems for rewarding online advocates. The invention identifies a primary advocate as a person or entity that endorses or advocates a product or service. The invention then automatically detects, tracks, and analyzes characteristics of the advocate's act of advocating the product or service to recipients. The invention also tracks the primary advocate's conversions, which occur when the primary advocate's act of advocating influences a recipient into advocating a product or service. The invention then automatically rewards the primary advocate as a function of characteristics of the primary advocate's influence and of the primary advocate's ability to convert recipients. | 11-13-2014 |
20140318962 | NANOPORE DEVICE FOR DRUG-LIKE MOLECULE SCREENING OR LEAD OPTIMIZATION TO A TARGETED PROTEIN - A nanosensor for detecting molecule characteristics includes a membrane having an opening configured to permit a charged molecule to pass but to block a protein molecule attached to a ligand connecting to the charged molecule, the opening being filled with an electrolytic solution. An electric field generator is configured to generate an electric field relative to the opening to drive the charged molecule through the opening. A sensor circuit is coupled to the electric field generator to sense current changes due to charged molecules passing into the opening. The current changes are employed to trigger a bias field increase to cause separation between the ligand and the protein to infer an interaction strength. | 10-30-2014 |
20140101481 | PER-RANK CHANNEL MARKING IN A MEMORY SYSTEM - Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel. | 04-10-2014 |
20140082127 | SYSTEM FOR ACCESSING SHARED DATA USING MULTIPLE APPLICATION SERVERS - A system including multiple application servers for accessing shared data and a centralized control unit for centrally controlling a lock applied to the shared data by each of the application servers. Each application server includes a distributed control unit for controlling a lock applied to the shared data by the application server and a selection unit for selecting any one of distributed mode in which a lock is acquired from the distributed control unit or a centralized mode in which a lock is acquired from the centralized control unit. | 03-20-2014 |
20130191698 | HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM - Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic. | 07-25-2013 |
20130111103 | HIGH-SPEED SYNCHRONOUS WRITES TO PERSISTENT STORAGE | 05-02-2013 |
20120331130 | Selecting A Network Connection For Data Communications With A Networked Device - Selecting a network connection for data communications with a networked device, including: identifying a plurality of networks available for data communications with the networked device, each network having network connection attributes; and selecting one of the plurality of networks in dependence upon the network connection attributes and the direction of data transfer. | 12-27-2012 |
20120239387 | VOICE TRANSFORMATION WITH ENCODED INFORMATION - Method, system, and computer program product for voice transformation are provided. The method includes transforming a source speech using transformation parameters, and encoding information on the transformation parameters in an output speech using steganography, wherein the source speech can be reconstructed using the output speech and the information on the transformation parameters. A method for reconstructing voice transformation is also provided including: receiving an output speech of a voice transformation system wherein the output speech is transformed speech which has encoded information on the transformation parameters using steganography; extracting the information on the transformation parameters; and carrying out an inverse transformation of the output speech to obtain an approximation of an original source speech. | 09-20-2012 |
20120221984 | METHOD OF OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT - A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns. | 08-30-2012 |
20120151172 | PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY - A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero. | 06-14-2012 |
20120144209 | METHODS FOR PROCESS KEY ROLLOVER/RE-ENCRYPTION AND SYSTEMS THEREOF - A method according to one embodiment includes defining a new encryption band with a length that is consistent with a redundant array of inexpensive disks (RAID) parity strip; freeing a working extent in a working stride on the RAID. In an iterative process until each stride in a source band is depleted of data: marking a source extent in a source stride from which to gather data to be re-encrypted; marking parity inconsistent in the working stride in the new encryption band; performing a second iterative process; and freeing the working extent. The second iterative process is performed until each extent in a source stride is depleted of data. Additional systems, methods and computer program products are also presented. | 06-07-2012 |
20110042862 | Stabilizers for Vinyl Ether Resist Formulations for Imprint Lithography - Coating compositions suitable for UV imprint lithographic applications include at least one vinyl ether crosslinker having at least two vinyl ether groups; at least one diluent comprising a monofunctional vinyl ether compound; at least one photoacid generator soluble in a selected one or both of the at least one monofunctional vinyl ether compound and the at least one vinyl ether crosslinker having the at least two vinyl ether groups; and at least one stabilizer comprising an ester compound selectively substituted with a substituent at an ester position or an alpha and the ester positions. Also disclosed are imprint processes. | 02-24-2011 |
20100281154 | Methods and Apparatus for Remote Monitoring - Provided are methods, apparatus and computer programs for remote monitoring of data. Log data output by an application program running on a storage-constrained apparatus is saved to local system memory—either as an in-memory data file or as output from one application piped to the input of another, or as a named pipe that passes data to a local publisher program—and then captured by the local publisher program. The local publisher program sends the data to a publish/subscribe broker, which can retain the most recent publications for analysis by one or more subscribers. This avoids the need to save large amounts of data to disk storage on the storage-constrained apparatus, and ensures that console output data and log data that is often discarded by headless, storage-constrained systems is available for analysis. The combination of the retain feature and publishing of output data in response to failure of a monitoring application ensures the availability of the data that was output just before the failure, which is generally the most useful data for problem diagnosis. | 11-04-2010 |
20100161391 | VARIABLE RATE TRANSPORT FEES BASED ON VEHICLE EXHAUST EMISSIONS - This invention provides a system and method of detecting and responding to individual vehicle exhaust emissions such that a vehicle producing exhaust emissions containing pollutants in excess of required standards is assessed a higher toll or other fees than non-offending vehicles. Upon correction of the problem when emissions are determined to be within acceptable ranges, the fees are re-adjusted. Vehicle fees can be assessed on a sliding scale regardless of “acceptable thresholds” whereupon a higher levels of pollution emitted by the vehicle require payment of a higher fee than that paid by a vehicle with a lower level. Sensors may be installed within individual vehicles, or may be externally mounted to detect emissions. The use of a computer program and program code may be used for collecting and quantifying the level of pollution in the emissions and for assessing a suitable fee based on the level. | 06-24-2010 |
20100153193 | VARIABLE-RATE TRANSPORT FEES BASED ON HAZARDOUS TRAVEL CONDITIONS - A system and method are responsive to actual or anticipated weather changes that are likely to have an adverse effect on roadway driving conditions in a given vehicle use area. Based on the anticipated severity of the weather condition, transport-related road and/or parking tolls and fees are increased in order to discourage unnecessary vehicle travel. Using a communication system such as a transponder network, changes in the tolls and fees can be transmitted to toll collection agencies, public parking facilities and other governmental and private enterprises responsible for the collection of vehicle transport fees. Rate change information and details of weather changes can also be transmitted to vehicles likely to be affected by the adverse condition and the consequent change in these fees. | 06-17-2010 |
20090106709 | System for Improving a Logic Circuit and Associated Methods - A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net. | 04-23-2009 |
20090039522 | BIPOLAR AND CMOS INTEGRATION WITH REDUCED CONTACT HEIGHT - Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer. | 02-12-2009 |