Intermolecular, Inc. Patent applications |
Patent application number | Title | Published |
20160133819 | Fluorine Containing Low Loss Dielectric Layers for Superconducting Circuits - Provided are superconducting circuits and methods of forming such circuits. A circuit may include a silicon containing low loss dielectric (LLD) layer formed by fluorine passivation of dangling bonds of silicon atoms in the layer. The LLD layer may be formed from silicon nitride or silicon oxide. For uniform passivation (e.g., uniform distribution of fluorine within the LLD layer), fluorine may be introduced while forming the LLD layer. For example, a fluorine containing precursor may be supplied into a deposition chamber together with a silicon containing precursor. Alternatively, the LLD layer may be formed as a stack of many thin sublayers, and each sublayer may be subjected to individual fluorine passivation. For example, low power plasma treatment or annealing in a fluorine containing environment may be used for this purpose. The concentration of fluorine in the LLD layer may be between about 0.5% atomic and 5% atomic. | 05-12-2016 |
20160035631 | Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices | 02-04-2016 |
20150345005 | Seed layer for low-e applications - Methods, and coated panels fabricated from the methods, are disclosed to form multiple coatings, (e.g., one or more infrared reflective layers), with minimal color change before and after heat treatments. For example, by adding appropriate seed layers between the IR reflective layers and the base oxide layers, the color performance can be maintained regardless of high temperature processes. The optical filler layers can include a metal oxide layer. In some embodiments, the seed layer can include nickel, titanium, and niobium, forming a nickel titanium niobium alloy such as NiTiNb. | 12-03-2015 |
20150338362 | Combinatorial screening of metallic diffusion barriers - Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper. | 11-26-2015 |
20150318446 | Low-Temperature Fabrication of Transparent Conductive Contacts for p-GaN and n-GaN - A ternary transparent conductive oxide, indium zinc oxide (IZO), is formed as a thin film by co-sputtering zinc oxide with indium oxide at a deposition temperature between 25 and 200 C. Optionally, up to 1-2% Al may be added by various methods. The layers may be annealed at temperatures between 200 and 400 C. Measurements of IZO with 75-85 wt % In | 11-05-2015 |
20150313046 | Superconducting Circuits with Reduced Microwave Absorption - Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption. | 10-29-2015 |
20150311397 | Zinc Stannate Ohmic Contacts for P-Type Gallium Nitride - Transparent ohmic contacts to p-GaN and other high-work-function (≧4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO | 10-29-2015 |
20150311257 | Resistive Random Access Memory Cells Having Shared Electrodes with Transistor Devices - Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped. | 10-29-2015 |
20150303057 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FLUORINE INCORPORATION - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer. | 10-22-2015 |
20150291812 | Low Emissivity Glass Incorporating Phosphorescent Rare Earth Compounds - Methods, and coated panels fabricated from the methods, are disclosed to form multiple coatings, (e.g., one or more infrared reflective layers), with minimal color change before and after heat treatments. The optical properties of the coating (e.g. the transmissivity and the IR emissivity) are generally coupled. In some embodiments, silicate materials are doped with rare earth elements. These doped silicate materials are able to absorb ultra-violet (UV) photons and emit photons in the visible range. This allows the transmissivity to be at least partially decoupled from the IR emissivity of the coated panel, resulting in a larger range of performance. | 10-15-2015 |
20150255340 | METHOD TO ETCH CU/TA/TAN SELECTIVELY USING DILUTE AQUEOUS HF/HCL SOLUTION - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm. | 09-10-2015 |
20150228710 | Methods to Improve Electrical Performance of ZrO2 Based High-K Dielectric Materials for DRAM Applications - A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (≧30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack. | 08-13-2015 |
20150228595 | METHODS FOR ETCHING COPPER DURING THE FABRICATION OF INTEGRATED CIRCUITS - Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H | 08-13-2015 |
20150188492 | Voltage Controlling Assemblies Including Variable Resistance Devices - Provided are voltage controlling assemblies that may be operable as clocks and/or oscillators. A voltage controlling assembly may include a comparator and a variable resistance device connected to one differential signal node of the comparator. The other node may be connected to a capacitor. Alternatively, no capacitors may be used in the assembly. During operation of the voltage controlling assembly, the variable resistance device changes its resistance between two different resistive states. The change from a low to a high resistive state may be associated with a voltage spike at the differential signal node of the comparator and trigger a response from the comparator. This resistance change may have a delay determining an operating frequency of the voltage controlling assembly. Specifically, the variable resistance device in the low resistive state may be kept for a period of time at a certain voltage before it switches into the high resistive state. | 07-02-2015 |
20150188046 | METHODS, SYSTEMS, AND APPARATUS FOR IMPROVING THIN FILM RESISTOR RELIABILITY - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof The ReRAM cells may include a first layer operable as a bottom electrode. The ReRAM cells may also include a second layer operable as a variable resistance layer configured to switch between at least a first resistive state and a second resistive state. The ReRAM cells may further include a third layer formed over the second layer. The third layer may have a substantially constant electrical resistivity. Moreover, the third layer may include a ternary metal-silicon nitride having a ratio of metal to silicon that is between about 1:1 and 1:4. Furthermore, the ternary metal-silicon nitride may include a metal that has an atomic weight that is greater than 90. The ReRAM cells may further include a fourth layer operable as a top electrode. | 07-02-2015 |
20150188045 | Stacked Bi-layer as the low power switchable RRAM - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode. | 07-02-2015 |
20150188044 | Embedded Resistors for Resistive Random Access Memory Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer formed on a substrate. The first layer may be operable as a bottom electrode. The ReRAM cells may also include a second layer formed over the first layer. The second layer may be operable as a variable resistance layer configured to switch reversibly between at least a first resistive state and a second resistive state. The ReRAM cells may further include a third layer formed over the second layer. The third layer may have an electrical resistivity that is substantially constant. Moreover, the third layer may include a ternary metal carbide. The ReRAM cells may also include a fourth layer formed over the third layer. The fourth layer may be operable as a top electrode. | 07-02-2015 |
20150188043 | Embedded Resistors for Resistive Random Access Memory Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode and a second layer operable to switch between a first resistive state and a second resistive state. The ReRAM cells may include a third layer that includes a material having a lower breakdown voltage than the second layer and further includes a conductive path created by electrical breakdown. The third layer may include any of tantalum oxide, titanium oxide, and zirconium oxide. Moreover, the third layer may include a binary nitride or a ternary nitride. The binary nitrides may include any of tantalum, titanium, tungsten, and molybdenum. The ternary nitrides may include silicon or aluminum and any of tantalum, titanium, tungsten, and molybdenum. The ReRAM cells may further include a fourth layer operable as a top electrode. | 07-02-2015 |
20150188039 | Embedded Resistors with Oxygen Gettering Layers - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode and a second layer operable to switch between at least a first resistive state and a second resistive state. The ReRAM cells may include a third layer including a first oxygen getter material and a fourth layer including a metal silicon nitride. The ReRAM cells may further include a fifth layer including a second oxygen getter material. The first oxygen getter material and the second oxygen getter material may be more reactive with oxygen than the metal silicon nitride. A work function of the first oxygen getter material and a work function of the second oxygen getter material may be substantially lower than a work function of the metal silicon nitride. The ReRAM cells may include a sixth layer operable as a top electrode. | 07-02-2015 |
20150187982 | Zinc Blende Cadmium-Manganese-Telluride with Reduced Hole Compensation Effects and Methods for Forming the Same - Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blende crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT. | 07-02-2015 |
20150187958 | IGZO Devices with Reduced Electrode Contact Resistivity and Methods for Forming the Same - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. A contact layer is formed above the IGZO channel layer. The contact layer includes arsenic. A source electrode and a drain electrode are formed above the contact layer. | 07-02-2015 |
20150187956 | IGZO Devices with Increased Drive Current and Methods for Forming the Same - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. The gate dielectric layer includes titanium. An interface layer is formed above the gate dielectric layer. The interface layer includes silicon. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. | 07-02-2015 |
20150187865 | Capacitors Including Inner and Outer Electrodes - Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide. | 07-02-2015 |
20150187841 | Method of forming current-programmable inline resistor - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a variable resistance layer that are interconnected in series by, for example, stacking the two. The embedded resistor prevents excessive electrical currents through the variable resistance layer thereby preventing its over-programming. The embedded resistor is configured to maintain a constant resistance during the operation of the ReRAM cell, such as applying switching currents and changing the resistance of the variable resistance layer. Specifically, the embedded resistor may be electrically broken down during fabrication of the ReRAM cell to improve the subsequent stability of the embedded resistance to electrical fields during operation of the ReRAM cell. The embedded resistor may be made from materials that allow this initial breakdown and to avoid future breakdowns, such metal silicon nitrides, metal aluminum nitrides, and metal boron nitrides. | 07-02-2015 |
20150187664 | High Productivity Combinatorial Testing of Multiple Work Function Materials on the Same Semiconductor Substrate - Provided are methods of high productivity combinatorial (HPC) screening of work function materials. Multiple test materials may be deposited as separate blanket layers on the same substrate while still forming individual interfaces with a common base layer. The thickness of each test material layer ensures that its work function properties are not impacted when other layers are deposited over that layer. A method may involve depositing a blocking layer over the base layer and selectively removing the blocking layer from a first site isolated region. A first test material is then deposited as a blanket layer and forms an interface with the base layer in that first region only. The first test material layer and the blocking layer are selectively removed from a second site isolated region followed by depositing a second test material layer as another blanket layer, which forms an interface with the base layer in the second region only. | 07-02-2015 |
20150187596 | Wet Etching of Silicon Containing Antireflective Coatings - Provided are methods for processing semiconductor substrates or, more specifically, etching silicon containing antireflective coatings (SiARCs) from the substrates while preserving silicon oxides layers disposed on the same substrates. An etching solution including sulfuric acid and hydrofluoric acid may be used for these purposes. In some embodiments, the weight ratio of sulfuric acid to hydrofluoric acid in the etching solution is between about 15:1 and 100:1 (e.g., about 60:1). The temperature of the etching solution may be between about 30° C. and 50° C. (e.g., about 40° C., during etching). It has been found that such processing conditions provide a SiARC etching rate of at least about 50 nanometers per minute and selectivity of SiARC over silicon oxide of greater than about 10:1 or even greater than about 50:1. The same etching solution may be also used to remove photoresist, organic dielectric, and titanium nitride. | 07-02-2015 |
20150187574 | IGZO with Intra-Layer Variations and Methods for Forming the Same - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO) with intra-layer variations and methods for forming such IGZO. At least a portion of a substrate is positioned in a processing chamber. A first sub-layer of an IGZO layer is formed above the at least a portion of the substrate while the at least a portion of the substrate is in the processing chamber. The first sub-layer of the IGZO layer is formed using a first set of processing conditions. A second sub-layer of the IGZO layer is formed above the first sub-layer of the IGZO layer while the at least a portion of the substrate is in the processing chamber. The second sub-layer of the IGZO layer is formed using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions. | 07-02-2015 |
20150185170 | X-ray fluorescence analysis of thin-film coverage defects - X-ray fluorescence (XRF) monitoring of characteristic peaks while etching thin-film layers can reveal coverage defects and thickness nonuniformity in the top film. To measure coverage and uniformity while screening candidate layer materials and processes, the candidate layers may be formed above an underlayer of a different composition. A wet etchant that selectively etches the underlayer faster than the candidate layer is applied to the candidate layer, and the XRF spectrum is monitored. Pinholes, cracks, islands, and nonuniform thickness in the candidate layer produce characteristic features in the time-dependent behavior of XRF peaks from the underlayer and/or the candidate layer. “Etch/XRF” tests can be used to rapidly and objectively identify the most uniform contiguous candidate layers to advance to further screening or production. XRF may also be calibrated against a known thickness indicator to detect the approach of a desired endpoint in an etch process. | 07-02-2015 |
20150184287 | Systems and Methods for Parallel Combinatorial Vapor Deposition Processing - Embodiments described herein provide systems and methods for performing vapor deposition processes on substrates. A housing defining a processing chamber is provided. A substrate support is positioned within the processing chamber and configured to support a substrate. A fluid supply system including a plurality precursor sources is included. A fluid conduit assembly is coupled to the fluid supply system and configurable to selectively expose a first site-isolated region defined on the substrate to the respective precursors of a first and a second of the plurality of precursor sources and selectively expose a second site-isolated region defined on the substrate to the respective precursors of a third and a fourth of the plurality of precursor sources. | 07-02-2015 |
20150184286 | Hydrogenated Amorphous Silicon Dielectric for Superconducting Devices - Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential. | 07-02-2015 |
20150184283 | Ternary metal nitride formation by annealing constituent layers - Ternary metal nitride layers suitable for thin-film resistors are fabricated by forming constituent layers of complementary components (e.g., binary nitrides of the different metals, or a binary nitride of one metal and a metallic form of the other metal), then annealing the constituent layers to interdiffuse the materials, thus forming the ternary metal nitride. The constituent layers (e.g., 2-5 nm thick) may be sputtered from binary metal nitride targets, from metal targets in a nitrogen-containing ambient, or from metal targets in an inert ambient. Optionally, a nitrogen-containing ambient may also be used for the annealing. The annealing may be 10 seconds to 10 minutes at 500-1000° C. and may also process another component on the same substrate (e.g., activate a diode). | 07-02-2015 |
20150179937 | Metal Organic Chemical Vapor Deposition of Embedded Resistors for ReRAM Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating them using metal organic chemical vapor deposition (MOCVD). Specifically, MOCVD is used to form an embedded resistor that includes two different nitrides. The first nitride may be more conductive than the second nitride. The concentrations of these nitrides may vary throughout the thickness of the embedded resistor. This variability may be achieved by changing flow rates of MOCVD precursors during formation of the embedded resistor. The second nitride may be concentrated in the middle of the embedded resistor, while the first nitride may be present at interface surfaces of the embedded resistor. As such, the first nitride protects the second nitride from exposure to other components and/or environments and prevents oxidation of the second nitride. Controlling the distribution of the two nitrides within the embedded resistor allows using new materials and achieving consistent performance of the embedded resistor. | 06-25-2015 |
20150179934 | ZrOx/STO/ZrOx Based Selector Element - Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a zirconium oxide-strontium-titanium oxide-zirconium oxide multilayer stack. The zirconium oxide can be replaced by at least one of hafnium oxide, aluminum oxide, magnesium oxide, or one of the lanthanide oxides. | 06-25-2015 |
20150179933 | TiOx Based Selector Element - Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack. | 06-25-2015 |
20150179930 | Schottky Barriers for Resistive Random Access Memory Cells - Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through the variable resistance layer in one direction and the other barrier limiting a current in the opposite direction. This combination of the two Schottky barriers provides current compliance during set operations and limits undesirable current overshoots during reset operations. The Schottky barriers' heights are configured to match the resistive switching characteristics of the cell. Conductive layers of the ReRAM cells operable as electrodes may be used to form these Schottky barriers together with semiconductor layers. These semiconductor layers may be different components from a variable resistance layer and, in some embodiments, may be separated by intermediate conductive layers from the variable resistance layers. | 06-25-2015 |
20150179918 | Plasma cleaning of superconducting layers - In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H | 06-25-2015 |
20150179917 | Atomic layer deposition of metal-oxide tunnel barriers using optimized oxidants - Metal oxide tunnel barrier layers for superconducting tunnel junctions are formed by atomic layer deposition. Both precursors include a metal (which may be the same metal or may be different). The first precursor is a metal alkoxide with oxygen bonded to the metal, and the second precursor is an oxygen-free metal precursor with an alkyl-reactive ligand such as a halogen or methyl group. The alkyl-reactive ligand reacts with the alkyl group of the alkoxide, forming a detached by-product and leaving a metal oxide monolayer. The temperature is selected to promote the reaction without causing the metal alkoxide to self-decompose. The oxygen in the alkoxide precursor is bonded to a metal before entering the chamber and remains bonded throughout the reaction that forms the monolayer. Therefore, the oxygen used in this process has no opportunity to oxidize the underlying superconducting electrode. | 06-25-2015 |
20150179916 | Catalytic Growth of Josephson Junction Tunnel Barrier - A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (<100 C, e.g., 20-30 C) that does not facilitate oxidation or silicide formation at the superconducting electrode interface. The tunnel barrier begins as a silicon layer deposited on a superconducting electrode and covered by a thin, oxygen-permeable catalytic layer. Oxygen gas is dissociated on contact with the catalytic layer, and the resulting oxygen atoms pass through the catalytic layer to oxidize the underlying silicon. The reaction self-limits when all the silicon is converted to silicon dioxide. | 06-25-2015 |
20150179915 | Fluorine Passivation During Deposition of Dielectrics for Superconducting Electronics - A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane. | 06-25-2015 |
20150179914 | Annealed dielectrics and heat-tolerant conductors for superconducting electronics - A interconnect structure for superconducting devices uses a material with a high melting point for the superconductive wiring; examples include refractory metals such as niobium. Because the wiring is tolerant of high temperatures, the interlayer dielectric (e.g., amorphous silicon with or without small amounts of passivants such as hydrogen or fluorine) may be subjected to rapid thermal annealing to reduce defects by driving off excess hydrogen, and optionally partially crystallizing the material. | 06-25-2015 |
20150179913 | Fluorine Passivation of Dielectric for Superconducting Electronics - An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (<350 C, e.g. ˜200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., <350 C) or impact to passivate defects such as dangling bonds. | 06-25-2015 |
20150179839 | CONTACT LAYERS FOR PHOTOVOLTAIC DEVICES - Solar cells and methods for forming a back contact layer for a solar cell are disclosed. The methods comprise depositing a first layer comprising a conductor on a substrate, depositing a second layer on the first layer, the second layer comprising between about 1 nm and about 25 nm of a metal chalcogenide, and forming a third layer operable as an absorber layer on the second layer. The absorber layer can comprise a photoactive semiconductor layer. In some embodiments, the absorber layer comprises a chalcogenide of copper-indium-gallium. In some embodiments, the absorber layer comprises a chalcogenide of copper-zinc-tin. In some embodiments, the absorber layer comprises CdTe. In some embodiments, the metal comprises Mo, W or Ta. In some embodiments, the metal comprises Mo. In some embodiments, the chalcogenide comprises S or Se or a combination thereof. | 06-25-2015 |
20150179815 | Quantum Well IGZO Devices and Methods for Forming the Same - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. The IGZO channel layer has a first sub-layer including crystalline IGZO, a second sub-layer including amorphous IGZO, and a third sub-layer including magnesium and zinc. A source electrode and a drain electrode are formed above the IGZO channel layer. | 06-25-2015 |
20150179773 | IGZO DEVICES WITH REDUCED THRESHHOLD VOLTAGE SHIFT AND METHODS FOR FORMING THE SAME - Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. An interface layer is formed above the gate dielectric material. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. The interface layer includes a material different than that of the gate dielectric layer and the IGZO channel layer. | 06-25-2015 |
20150179743 | Graphene as a Ge Surface Passivation Layer to Control Metal-Semiconductor Junction Resistivity - In some embodiments, a “channel last” device architecture is implemented wherein an amorphous carbon layer is formed between the channel and the source and drain layers. Subsequent heating of the structure allows the metal materials in the source and drain layers to convert the amorphous carbon materials into graphene. This forms an ohmic contact between the source and drain layers and the channel layers and lowers the contact resistance. | 06-25-2015 |
20150179730 | ZrO-Based High K Dielectric Stack for Logic Decoupling Capacitor or Embedded DRAM - A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide. | 06-25-2015 |
20150179684 | High Productivity Combinatorial Material Screening for Stable, High-Mobility Non-Silicon Thin Film Transistors - Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate. | 06-25-2015 |
20150179683 | High Productivity Combinatorial Material Screening for Metal Oxide Films - Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnO | 06-25-2015 |
20150179509 | Plasma Treatment of Low-K Surface to Improve Barrier Deposition - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated species. The activated species can be used to treat the surfaces of low-k and/or ultra low-k dielectric materials to facilitate improved deposition of diffusion barrier materials. | 06-25-2015 |
20150179508 | Tantalum-Based Copper Barriers and Methods for Forming the Same - Embodiments described herein provide tantalum-based copper barriers and methods for forming such barriers. A dielectric body is provided. A first layer is formed above the dielectric body. The first layer includes tantalum. A second layer is formed above the first layer. The second layer includes manganese. A third layer is formed above the second layer. The third layer includes copper. | 06-25-2015 |
20150179487 | Multipurpose Combinatorial Vapor Phase Deposition Chamber - In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility. | 06-25-2015 |
20150179448 | Methods for Forming Crystalline IGZO Through Annealing - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. An IGZO layer is formed above the substrate. The IGZO layer is annealed in an environment consisting essentially of nitrogen gas. | 06-25-2015 |
20150179446 | Methods for Forming Crystalline IGZO Through Processing Condition Optimization - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A layer is formed above the substrate using a PVD process. The layer includes indium, gallium, zinc, or a combination thereof. The PVD process is performed in a gaseous environment having a pressure of between about 1 mT and about 5 mT and including between about 20% and about 100% oxygen gas. The PVD process may be performed at a processing temperature between about 25° C. and about 400° C. The duty cycle of the PVD process may be between about 70% and about 100%. | 06-25-2015 |
20150179444 | Methods for Forming Crystalline IGZO Through Power Supply Mode Optimization - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is positioned relative to at least one target. The at least one target includes indium, gallium, zinc, or a combination thereof. A substantially constant voltage is provided across the substrate and the at least one target to cause a plasma species to impact the at least one target. The impacting of the plasma species on the at least one target causes material to be ejected from the at least one target to form an IGZO layer above the substrate. | 06-25-2015 |
20150179442 | Methods for Forming Crystalline IGZO with a Seed Layer - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed. | 06-25-2015 |
20150179438 | GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES - SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer. | 06-25-2015 |
20150179436 | Plasma densification of dielectrics for improved dielectric loss tangent - Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H | 06-25-2015 |
20150179316 | Methods of forming nitrides at low substrate temperatures - Provided are methods of forming nitrides at low substrate temperatures, such as less than 500° C. or even less than 400° C. The nitrides can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), and other like techniques. The low substrate temperatures allow using various temperature sensitive precursors, such as Tetrakis(DiMethylAmino)Hafnium (i.e., TDMAHf) or TertiaryButylimido-Tris(DiEthylamino)Tantalum (i.e., TBTDET), to form nitrides of components provided by these precursors. Furthermore, the low temperatures preserve other structures present on the substrate prior to forming the nitride layers. Nitrogen-containing precursors with low dissociation energy are used in these methods. Some examples of such nitrogen-containing precursors include hydrazine (N | 06-25-2015 |
20150177585 | Systems, Methods, and Apparatus for Integrated Glass Units Having Adjustable Transmissivities - Disclosed herein are systems, methods, and apparatus for forming adjustable windows may include a substrate and a first conducting oxide layer formed over the substrate. The adjustable windows may further include a spectral tuning layer formed over the first conducting oxide layer and an ion conductor layer formed over the spectral tuning layer. The adjustable windows may also include an ion storage layer formed over the ion conductor layer and a second conducting oxide layer formed over the ion storage layer. In some embodiments, the spectral tuning layer may be configured to change an infrared transmissivity of the adjustable window. Furthermore, the spectral tuning layer may be configured to toggle a solar heat gain ratio coefficient of the adjustable window between two or more solar heat gain ratio coefficients. | 06-25-2015 |
20150177583 | SYSTEMS, METHODS, AND APPARATUS FOR INTEGRATED GLASS UNITS HAVING ADJUSTABLE SOLAR HEAT GAINS - Disclosed herein are systems, methods, and apparatus for forming windows that may include a substrate, a bottom dielectric layer formed over the substrate, and a reflective layer formed over the bottom dielectric layer. The windows may also include a conducting barrier layer formed over the reflective layer, an electrochromic layer formed over the conducting barrier layer, and an ion conductor layer formed over the electrochromic layer. The windows may further include an ion storage layer formed over the ion conductor layer and a conducting oxide layer formed over the ion storage layer. The electrochromic layer may be configured to change a transmissivity of the windows in response to a voltage being applied to the window. The windows may have an emissivity of between about 0.01 and 0.08. | 06-25-2015 |
20150177311 | Methods and Systems for Evaluating IGZO with Respect to NBIS - Embodiments described herein provide methods and systems for evaluating indium-gallium-zinc oxide (IGZO) with respect to negative bias illumination stress (NBIS). A plurality of IGZO devices is formed. Each of the plurality of IGZO devices includes a semiconductor substrate and an IGZO layer formed above the semiconductor substrate. A processing condition used to form at least two of the plurality of IGZO devices is varied in a combinatorial manner. A bias is applied to the semiconductor substrate of each of the plurality of IGZO devices. A current flow through each of the plurality of IGZO devices while the bias is applied is measured. | 06-25-2015 |
20150176124 | Methods for Rapid Generation of ALD Saturation Curves Using Segmented Spatial ALD - Systems and methods for rapid generation of ALD saturation curves using segmented spatial ALD are disclosed. Methods include introducing a substrate, having a plurality of substrate segment regions, into a processing chamber. The substrate may be disposed upon a pedestal within the chamber. Sequentially exposing the plurality of segment regions to a precursor within the chamber at a first processing temperature. Afterwards, purging the precursor from the chamber and then sequentially exposing each plurality of segment regions to a reactant within the chamber at the first processing temperature. Afterwards, purging the reactant from the chamber. Repeat sequentially exposing the plurality of segment regions to the precursor and the reactant for a plurality of cycles. Each segment region may be sequentially exposed to the precursor for a unique processing time. The pedestal may be rotated prior to exposing each next segment region to the precursor and the reactant. | 06-25-2015 |
20150176122 | Low-temperature growth of complex compound films - Ternary oxides, nitrides and oxynitrides of the form (a)(b)O | 06-25-2015 |
20150176117 | Interchangeable Sputter Gun Head - In some embodiments, apparatus are provided that provide for flexible processing in both high productivity combinatorial (HPC) and full wafer modes. The apparatus allow for interchangeable functionality that includes deposition with different sizes of targets, plasma treatment, ion beam treatment, and in-situ metrology. The functional modules are designed so that the modules may be interchanged with minimal effort and reduced system downtime. | 06-25-2015 |
20150162111 | Transparent Conductive Films and Methods for Forming the Same - Embodiments provided herein describe transparent conductive films and methods for forming transparent conductive films. A transparent substrate is provided. A first layer is formed above the transparent substrate. The first layer includes nickel. A second layer is formed above the first layer. The second layer includes silver and palladium. A third layer is formed above the second layer. The third layer comprises nickel. | 06-11-2015 |
20150158762 | Simplified Protection Layer for Abrasion Resistant Glass Coatings and Methods for Forming the Same - Embodiments provided herein describe abrasion resistant glass coatings and methods for forming abrasion resistant glass coatings. A glass body is provided. An abrasion resistant layer is formed above the glass body. The abrasion resistant layer includes an amorphous carbon. A pull-up layer is formed above the abrasion resistant layer. A protective layer is formed above the pull-up layer. The protective layer may include a titanium-based nitride. The pull-up lay may include tungsten oxide, zirconium oxide, manganese oxide, molybdenum oxide, titanium oxide, or a combination thereof. | 06-11-2015 |
20150155368 | Amorphous Silicon Thin-Film Transistors with Reduced Electrode Contact Resistivity and Methods for Forming the Same - Embodiments described herein provide amorphous silicon thin-film transistors (a-Si TFTs) and methods for forming a-Si TFTs. A substrate is provided. A gate electrode is formed above the substrate. An a-Si channel layer is formed above the gate electrode. A contact layer is formed above the a-Si channel layer. The contact layer includes titanium, zinc, arsenic, or a combination thereof. A source electrode and a drain electrode are formed above the contact layer. | 06-04-2015 |
20150140838 | Two Step Deposition of High-k Gate Dielectric Materials - Methods and apparatus for forming a dielectric layer for use as a gate dielectric are provided. A high-k layer is formed with first ALD process using a halogen-based precursor. The metal in the halogen-based precursor may be at least one of hafnium, zirconium, or titanium. The halogen in the halogen-based precursor may be at least one of fluorine, chlorine, or iodine. In some embodiments, the halogen-based metal precursor includes hafnium chloride. The remainder of the high-k layer is formed with second ALD process using a metal organic-based precursor. The metal in the metal organic-based precursor may be at least one of hafnium, zirconium, or titanium. The organic ligands in the metal organic-based precursor may be at least one of β-diketonate precursors, alkoxide precursors, amino precursors. In some embodiments, the metal organic-based precursor includes amino precursors. | 05-21-2015 |
20150140836 | Methods to Control SiO2 Etching During Fluorine Doping of Si/SiO2 Interface - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. Methods are disclosed that discuss the use of blocking species that bind to the surface of the dielectric and retard the etching of the dielectric surface by a doping/passivating species. The surface of the dielectric may be exposed to the blocking species a plurality of times during the process to ensure that the surface is well protected. | 05-21-2015 |
20150140834 | al2o3 surface nucleation preparation with remote oxygen plasma - Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface. | 05-21-2015 |
20150140696 | Combinatorial Method for Solid Source Doping Process Development - One or more small spot showerhead apparatus are used to provide dopant exposure and/or to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner. Anneal processes where the area of the process can be controlled such as laser annealing or site-isolated rapid thermal processing (RTP) can be used to vary the annealing conditions in a combinatorial manner. | 05-21-2015 |
20150132953 | Etching of semiconductor structures that include titanium-based layers - Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH | 05-14-2015 |
20150132938 | Methods and Systems for Forming Reliable Gate Stack on Semiconductors - Methods are provided for the deposition of high-k gate dielectric materials which are doped with fluorine and/or nitrogen to improve the performance and reliability. The high-k dielectric materials may include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, titanium oxide, titanium silicon oxide, or titanium aluminum oxide. The fluorine dopant is provided from a layer including titanium nitride or amorphous silicon, where the layer is doped with at least one of fluorine or nitrogen. The dopants diffuse into the high-k dielectric material during a subsequent anneal process. | 05-14-2015 |
20150130065 | method to etch cu/Ta/TaN selectively using dilute aqueous Hf/h2so4 solution - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H | 05-14-2015 |
20150129826 | Flexible Non-Volatile Memory - A flexible and/or transparent nonvolatile memory device can be fabricated on flexible substrates, together with ductile materials or transparent conductive oxide materials, and layers with thicknesses that allow flexibility and transparency. The ductile materials can include Ti, Ni, Nb, or Zr. The transparent conductive materials can include indium tin oxide, zinc oxide or aluminum doped zinc oxide. The nonvolatile memory devices can include resistive switching memory, phase change memory, magnetoresistive random access memory, or spin-transfer torque random access memory. | 05-14-2015 |
20150118828 | Reduction of native oxides by annealing in reducing gas or plasma - Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 Å thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat). | 04-30-2015 |
20150093500 | Corrosion-Resistant Silver Coatings with Improved Adhesion to III-V Materials - The electrical and optical performance of silver LED reflective contacts in III-V devices such as GaN LEDs is limited by silver's tendency to agglomerate during annealing processes and to corrode on contact with silver-reactive materials elsewhere in the device (for example, gallium or aluminum). Agglomeration and reaction are prevented, and crystalline morphology of the silver layer may be optimized, by forming a diffusion-resistant transparent conductive layer between the silver and the source of silver-reacting metal, (2) doping the silver or the diffusion-resistant transparent conductive layer for improved adhesion to adjacent layers, or (3) doping the silver with titanium, which in some embodiments prevents agglomeration and promotes crystallization of the silver in the preferred <111> orientation. | 04-02-2015 |
20150091105 | CONTINUOUS TUNING OF ERBIUM SILICIDE METAL GATE EFFECTIVE WORK FUNCTION VIA A PVD NANOLAMINATE APPROACH FOR MOSFET APPLICATIONS - Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nano-laminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack. | 04-02-2015 |
20150091032 | Nickel-Titanium and Related Alloys as Silver Diffusion Barriers - Diffusion of silver from LED reflector layers is blocked by 10-50 nm barrier layers of nickel-titanium (NiTi) alloys. Optionally, the alloys also include one or more of tungsten (W), niobium (Nb), aluminum (Al), vanadium (V), tantalum (Ta), or chromium (Cr). These barriers may omit the noble-metal (e.g., platinum or gold) cap used with silver barriers based on other materials. | 04-02-2015 |
20150087130 | DRAM MIM Capacitor Using Non-Noble Electrodes - A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material. | 03-26-2015 |
20150079727 | Amorphous IGZO Devices and Methods for Forming the Same - Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers. | 03-19-2015 |
20150064361 | UV treatment for ALD film densification - Irradiation with ultraviolet (UV) light during atomic layer deposition (ALD) can be used to cleave unwanted bonds on the layer being formed (e.g., trapped precursor ligands or process-gas molecules). Alternatively, the UV irradiation can be used to excite the targeted bonds so they may be more easily cleaved by other means. The use of UV may enable the formation of low-defect-density films at lower deposition temperatures (e.g., <250 C), or reduce the need for a high-temperature post-deposition anneal, improving the quality of devices formed on heat-sensitive materials such as germanium. | 03-05-2015 |
20150060910 | Conductive Transparent Reflector - Methods to improve the reflection of light emitting devices are disclosed. A method consistent with the present disclosure includes forming a light generating layer over a site-isolated region of a substrate. Next, forming a first transparent conductive layer over the light generating layer. Forming a low refractive index material over the first transparent conductive layer, and in time, forming a second transparent conductive layer over the low refractive index material. Subsequently, forming a reflective material layer thereon. Accordingly, methods consistent with the present disclosure may form a plurality of light emitting devices in various site-isolated regions on a substrate. | 03-05-2015 |
20150041912 | Gate Stacks Including TaXSiYO for MOSFETS - Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation. | 02-12-2015 |
20150035085 | Doped High-k Dielectrics and Methods for Forming the Same - Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen. | 02-05-2015 |
20150016178 | All around electrode for novel 3D RRAM applications - A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer. | 01-15-2015 |
20140353566 | ReRAM materials stack for low-operating-power and high-density applications - A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode. | 12-04-2014 |
20140322884 | Nonvolatile resistive memory element with a silicon-based switching layer - A nonvolatile resistive memory element includes a novel switching layer and methods of forming the same. The switching layer includes a material having bistable resistance properties and formed by bonding silicon to oxygen or nitrogen. The switching layer may include at least one of SiO | 10-30-2014 |
20140322507 | SYSTEMS, METHODS, AND APPARATUS FOR PRODUCTION COATINGS OF LOW-EMISSIVITY GLASS - Disclosed herein are systems, methods, and apparatus for forming low emissivity panels. In some embodiments, a partially fabricated panel may be provided that includes a substrate, a reflective layer formed over the substrate, and a barrier layer formed over the reflective layer such that the reflective layer is formed between the substrate and the barrier layer. The barrier layer may include a partially oxidized alloy of three or more metals. A first interface layer may be formed over the barrier layer. A top dielectric layer may be formed over the first interface layer. The top dielectric layer may be formed using reactive sputtering in an oxygen containing environment. The first interface layer may prevent further oxidation of the partially oxidized alloy of the three or more metals when forming the top dielectric layer. A second interface layer may be formed over the top dielectric layer. | 10-30-2014 |
20140315331 | Screening of Surface Passivation Processes for Germanium Channels - Candidate wet processes for native oxide removal from, and passivation of, germanium surfaces can be screened by high-productivity combinatorial variation of different process parameters on different site-isolated regions of a single substrate. Variable process parameters include the choice of hydrohalic acid used to remove the native oxide, the concentration of the acid in the solution, the exposure time, and the use of an optional sulfur passivation step. Measurements to compare the results of the process variations include attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR), contact angle, atomic force microscopy (AFM), scanning electron microscopy (SEM), and X-ray fluorescence (XRF). A sample screening experiment indicated somewhat less native oxide regrowth using HCl or HBr without sulfur passivation, compared to using HF with sulfur passivation. | 10-23-2014 |
20140308528 | SYSTEMS, METHODS, AND APPARATUS FOR PRODUCTION COATINGS OF LOW-EMISSIVITY GLASS - Disclosed herein are systems, methods, and apparatus for forming a low emissivity panel. In various embodiments, a partially fabricated panel may be provided. The partially fabricated panel may include a substrate, a reflective layer formed over the substrate, and a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the substrate and the top dielectric layer. The top dielectric layer may include tin having an oxidation state of +4. An interface layer may be formed over the top dielectric layer. A top diffusion layer may be formed over the interface layer. The top diffusion layer may be formed in a nitrogen plasma environment. The interface layer may substantially prevent nitrogen from the nitrogen plasma environment from reaching the top dielectric layer and changing the oxidation state of tin included in the top dielectric layer. | 10-16-2014 |
20140302671 | Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition - Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures. | 10-09-2014 |
20140299834 | Memory Device Having An Integrated Two-Terminal Current Limiting Resistor - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 10-09-2014 |
20140284545 | In-Situ Nitride Initiation Layer For RRAM Metal Oxide Switching Material - A resistive memory device having an in-situ nitride initiation layer is disclosed. The nitride initiation layer is formed above the first electrode, and the metal oxide switching layer is formed above the nitride initiation layer to prevent oxidation of the first electrode. The nitride initiation layer may be a metal nitride layer that is formed by atomic layer deposition in the same chamber in which the metal oxide switching layer is formed. The nitride initiation layer and metal oxide switching layer may alternatively be formed in a chemical vapor deposition (CVD) chamber or a physical vapor deposition (PVD) chamber. | 09-25-2014 |
20140273525 | Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films - Metal-oxide films (e.g., aluminum oxide) with low leakage current suitable for high-k gate dielectrics are deposited by atomic layer deposition (ALD). The purge time after the metal-deposition phase is 5-15 seconds, and the purge time after the oxidation phase is prolonged beyond 60 seconds. Prolonging the post-oxidation purge produced an order-of-magnitude reduction of leakage current in 30 Å-thick Al | 09-18-2014 |
20140273497 | Wet Processing Systems and Methods with Replenishment - Embodiments provided herein describe systems and methods for processing substrates. A substrate having a plurality of site-isolated regions defined thereon is provided. A plurality of wet processes is simultaneously performed. Each of the plurality of wet processes is performed on one of the plurality of site-isolated regions defined on the substrate. The simultaneously performing includes exposing each of the plurality of site-isolated regions to one of a plurality of wet processing formulations. Each of the plurality of wet processing formulations includes a component. The respective component is added to at least some of the plurality of wet processing formulations during the exposing. A processing condition is varied between at least two of the plurality of wet processes in a combinatorial manner. | 09-18-2014 |
20140273493 | Hydrogen Plasma Cleaning of Germanium Oxide Surfaces - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide. | 09-18-2014 |
20140273467 | Polycrystalline-silicon etch with low-peroxide apm - Polycrystalline silicon (poly-Si) can be thoroughly removed without significant effect on adjacent oxides by an aqueous solution of ammonium hydroxide with smaller concentrations of hydrogen peroxide than are normally used in ammonia-peroxide mixture (APM) formulations used for cleaning. The etching selectivity of poly-Si relative to oxides can be widely tuned by varying the hydrogen-peroxide concentration. Compared to other formulations used to remove poly-Si dummy gates in logic-node fabrication, such as TMAH, these aqueous solutions are less hazardous to workers and the environment. | 09-18-2014 |
20140273427 | Electrode for Low-Leakage Devices - A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer. | 09-18-2014 |
20140273404 | Advanced Targeted Microwave Degas System - In some embodiments, methods are described that allow the processing of a substrate using microwave-based degas systems. The methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated. In some embodiments, apparatus are described that allow the investigation of process variables used in microwave-based degas systems to remove adsorbed species from the surface of a substrate. The apparatus allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated. | 09-18-2014 |
20140273341 | Methods for Forming Back-Channel-Etch Devices with Copper-Based Electrodes - Embodiments described herein provide methods for forming indium-gallium-zinc oxide (IGZO) devices. A substrate is provided. An IGZO layer is formed above the substrate. A copper-containing layer is formed above the IGZO layer. A wet etch process is performed on the copper-containing layer to form a source region and a drain region above the IGZO layer. The performing of the wet etch process on the copper-containing layer includes exposing the copper-containing layer to an etching solution including a peroxide compound and one of citric acid, formic acid, malonic acid, lactic acid, etidronic acid, phosphonic acid, or a combination thereof. | 09-18-2014 |
20140273340 | High Productivity Combinatorial Screening for Stable Metal Oxide TFTs - Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate. | 09-18-2014 |
20140273333 | Methods for fabricating ZnOSe alloys - Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium. | 09-18-2014 |
20140273314 | High Productivity Combinatorial Workflow to Screen and Design Chalcogenide Materials as Non Volatile Memory Current Selector - Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes. | 09-18-2014 |
20140273311 | Optical Absorbers - Optical absorbers and methods are disclosed. The methods comprise depositing a plurality of precursor layers comprising one or more of Cu, Ga, and In on a substrate, and heating the layers in a chalcogenizing atmosphere. The plurality of precursor layers can be one or more sets of layers comprising at least two layers, wherein each layer in each set of layers comprises one or more of Cu, Ga, and In exhibiting a single phase. The layers can be deposited using two or three targets selected from Ag and In containing less than 21% In by weight, Cu and Ga where the Cu and Ga target comprises less than 45% Ga by weight, Cu(In,Ga), wherein the Cu(In,Ga) target has an atomic ratio of Cu to (In+Ga) greater than 2 and an atomic ratio of Ga to (Ga+In) greater than 0.5, elemental In, elemental Cu, and In | 09-18-2014 |
20140273309 | Controlling Radical Lifetimes in a Remote Plasma Chamber - Remote-plasma treatments of surfaces, for example in semiconductor manufacture, can be improved by preferentially exposing the surface to only a selected subset of the plasma species generated by the plasma source. The probability that a selected species reaches the surface, or that an unselected species is quenched or otherwise converted or diverted before reaching the surface, can be manipulated by introducing additional gases with selected properties either at the plasma source or in the process chamber, varying chamber pressure or flow rate to increase or decrease collisions, or changing the dimensions or geometry of the injection ports, conduits and other passages traversed by the species. Some example processes treat surfaces preferentially with relatively low-energy radicals, vary the concentration of radicals at the surface in real time, or clean and passivate in the same unit process. | 09-18-2014 |
20140273300 | Method for Forming ReRAM Chips Operating at Low Operating Temperatures - Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging. | 09-18-2014 |
20140272455 | Titanium nickel niobium alloy barrier for low-emissivity coatings - A method for making low emissivity panels, including control the composition of a barrier layer formed on a thin conductive silver layer. The barrier structure can include a ternary alloy of titanium, nickel and niobium, which showed improvements in overall performance than those from binary barrier results. The percentage of titanium can be between 5 and 15 wt %. The percentage of nickel can be between 30 and 50 wt %. The percentage of niobium can be between 40 and 60 wt %. | 09-18-2014 |
20140272454 | Barrier Layers for Silver Reflective Coatings and HPC Workflows for Rapid Screening of Materials for Such Barrier Layers - Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer. | 09-18-2014 |
20140272395 | LOW-EMISSIVITY GLASS INCLUDING SPACER LAYERS COMPATIBLE WITH HEAT TREATMENT - Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first reflective layer, a second reflective layer, and a spacer layer disposed between the first reflective layer and the second reflective layer. In some embodiments, the spacer layer may have a thickness of between about 20 nm and 90 nm. The spacer layer may include a bi-metal oxide that may include tin, and may further include one of zinc, aluminum, or magnesium. The spacer layer may have a substantially amorphous structure. Moreover, the spacer layer may have a substantially uniform composition throughout the thickness of the spacer layer. The low emissivity panel may be configured to have a color change as determined by Rg ΔE (i.e. as determined on the glass side) that is less than about 1.7 in response to an application of a heat treatment to the low emissivity panel. | 09-18-2014 |
20140272390 | Low-E Panel with Improved Barrier Layer Process Window and Method for Forming the Same - Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A barrier layer is formed above the reflective layer. A nitride-containing layer is formed above the barrier layer. The nitride-containing layer has a thickness that is 1 nm or less. A over-coating layer is formed above the nitride-containing layer. The over-coating layer includes a different material than that of the nitride-containing layer. | 09-18-2014 |
20140272387 | Anti-Glare Coatings with Aqueous Particle Dispersions and Methods for Forming the Same - Embodiments provided herein describe optical coatings, panels having optical coatings thereon, and methods for forming optical coatings and panels. A substrate is provided. A coating formulation is applied to the substrate. The coating formulation includes an aqueous-based suspension of particles. The particles have a sheet-like morphology and a thickness of less than about 100 nanometers (nm). The coating formulation is cured to form an anti-glare coating above the substrate. The anti-glare coating has a thickness of between 1 micrometer (μm) and 100 μm. | 09-18-2014 |
20140272384 | Anti-Reflection Coatings with Aqueous Particle Dispersions and Methods for Forming the Same - Embodiments provided herein describe coating formulations, such as those used to form optical coatings, panels having optical coatings thereon, and methods for forming optical coatings and panels. The coating formulation includes an aqueous-based suspension of particles. The particles have a sheet-like morphology and a thickness of less than about 10 nm. The coating also includes a polysiloxane or silane emulsion, a polysiloxane or silane solution, or a combination thereof. | 09-18-2014 |
20140272354 | Method to generate high LSG low-emissivity coating with same color after heat treatment - Low emissivity panels can include a separation layer of Zn | 09-18-2014 |
20140272353 | Color shift of high LSG low emissivity coating after heat treatment - Low emissivity panels can include a protection layer of silicon nitride on a layer of ZnO on a layer of Zn | 09-18-2014 |
20140272335 | Low-E Glazing Performance by Seed Structure Optimization - A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111). | 09-18-2014 |
20140272290 | Polymer Anti-glare Coatings and Methods for Forming the Same - Embodiments provided herein describe anti-glare coatings and panels and methods for forming anti-glare coatings and panels. A transparent substrate is provided. A polymer is sputtered onto the transparent substrate to form an anti-glare coating on the transparent substrate. | 09-18-2014 |
20140272127 | Anti-Glare Coatings with Sacrificial Surface Roughening Agents and Methods for Forming the Same - Embodiments provided herein describe optical coatings, panels having optical coatings thereon, and methods for forming optical coatings and panels. A sol-gel matrix is formed above a surface of a substrate. Organic micro-particles are embedded in a surface of the sol-gel matrix. A heat treatment is applied to the sol-gel matrix and the embedded plurality of organic micro-particles. Substantially all of the organic micro-particles are removed during the heat treatment, and after the heat treatment, the sol-gel matrix has a surface roughness suitable to provide anti-glare properties. | 09-18-2014 |
20140272112 | Combinatorial Methods and Systems for Developing Electrochromic Materials and Devices - Embodiments provided herein describe methods and systems for evaluating electrochromic material processing conditions. A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions. | 09-18-2014 |
20140269004 | Method for Improving Data Retention of ReRAM Chips Operating at Low Operating Temperatures - Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations. | 09-18-2014 |
20140268993 | Nonvolatile resistive memory element with an oxygen-gettering layer - A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO | 09-18-2014 |
20140268377 | Ultrathin Coating for One Way Mirror Applications - Systems and methods for improving the performance of one way mirror applications are disclosed. Methods consistent with the present disclosure include introducing a glass substrate into a processing chamber. The processing chamber comprises a sputter target assembly disposed over the substrate. Next, depositing metal silicide material within a plurality of site-isolated regions on the substrate to form a metal silicide coating within each region. Notably, each metal silicide coating has a thickness between 0.001 and 0.5 microns. Finally, evaluating results of the metal silicide coating formed within the plurality of site-isolated regions. | 09-18-2014 |
20140268349 | Optical Coatings with Plate-Shaped Particles and Methods for Forming the Same - Embodiments provided herein describe optical coatings, panels having optical coatings thereon, and methods for forming optical coatings and panels. A transparent substrate is provided. An optical coating is formed on the transparent substrate. The optical coating includes a plurality of plate-shaped silicon dioxide particles. | 09-18-2014 |
20140268348 | Anti-Reflective Coatings with Porosity Gradient and Methods for Forming the Same - Embodiments provided herein provide anti-reflective coatings with porosity gradients and methods for forming such anti-reflective coatings. A transparent substrate is provided. A primary material and a sacrificial material are simultaneously deposited above the transparent substrate to form a coating above the transparent substrate. At least some of the sacrificial material is removed from the coating to form a plurality of pores in the coating. | 09-18-2014 |
20140268317 | High Solar Gain Low-E Panel and Method for Forming the Same - Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. An over-coating layer is formed above the reflective layer. The over-coating layer includes first, second, and third sub-layers. The second sub-layer is between the first and third sub-layers, and the first and third sub-layers include the same material | 09-18-2014 |
20140268316 | SYSTEMS, METHODS, AND APPARATUS FOR PRODUCTION COATINGS OF LOW-EMISSIVITY GLASS INCLUDING A TERNARY ALLOY - Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a substrate and a reflective layer formed over the substrate. The low emissivity panels may further include a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the top dielectric layer and the substrate. The top dielectric layer may include a ternary metal oxide, such as zinc tin aluminum oxide. The top dielectric layer may also include aluminum. The concentration of aluminum may be between about 1 atomic % and 15 atomic % or between about 2 atomic % and 10 atomic %. An atomic ratio of zinc to tin in the top dielectric layer may be between about 0.67 and about 1.5 or between about 0.9 and about 1.1. | 09-18-2014 |
20140268301 | LOW-EMISSIVITY PANELS INCLUDING MAGNETIC LAYERS - Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first substrate. The first substrate may have a first side and a second side. The low emissivity panels may also include a magnetic fluid layer deposited over the first side of the first substrate and a reflective layer deposited over the second side of the first substrate. The magnetic fluid layer may include magnetic particles. The reflective layer may include a conductive material configured to conduct an electrical current and generate a magnetic field. The magnetic field may be configured to change an orientation of the magnetic particles in the magnetic fluid layer and a transmissivity of the magnetic fluid layer within a visible spectrum. The low emissivity panels may also include a first bus and a second bus deposited along opposite edges of the reflective layer and electrically connected to the reflective layer. | 09-18-2014 |
20140264871 | Method to Increase Interconnect Reliability - Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material. | 09-18-2014 |
20140264825 | Ultra-Low Resistivity Contacts - Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10 | 09-18-2014 |
20140264747 | Deposition of Anisotropic Dielectric Layers Orientationally Matched to the Physically Separated Substrate - A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant. | 09-18-2014 |
20140264708 | Optical Absorbers - Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements. | 09-18-2014 |
20140264634 | FINFET FOR RF AND ANALOG INTEGRATED CIRCUITS - Methods for making a FinFET having reduced device mismatch and low-frequency noise are disclosed for RF/analog IC designs. A semiconductor fin is formed having a height between 2 and 6 times its width, atomically smooth sidewalls, and rounded active corners to minimize device variability. The fin is operable as a channel between a source and a drain. A first layer of SiO | 09-18-2014 |
20140264507 | Fluorine Passivation in CMOS Image Sensors - CMOS imaging sensors having fluorine-passivated structures to reduce dark current are disclosed together with methods of making thereof. The CIS comprises an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. Methods of preparing a CIS comprise providing a source of fluorine (F) atoms, and annealing in the presence of the source of F atoms. After the annealing, at least one silicon-containing surface or region in the CIS comprises Si—F bonds and is fluorine passivated. | 09-18-2014 |
20140264492 | COUNTER-DOPED LOW-POWER FINFET - FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally doped region of counter-doped semiconductor is formed on the fin using methods such as monolayer doping, sacrificial oxide doping, or low energy plasma doping. Halo-doped regions are formed by angled ion implantation. The halo-doped regions are disposed in the lower portion of the source and drain and adjacent to the fin. Energy band barrier regions can be formed at the edges of the halo-doped regions by angled ion implantation. | 09-18-2014 |
20140264321 | Method of Fabricating IGZO by Sputtering in Oxidizing Gas - In some embodiments, oxidants such as ozone (O | 09-18-2014 |
20140264320 | Compositional Graded IGZO Thin Film Transistor - A gradient in the composition of at least one of the elements of a metal-based semiconductor layer is introduced as a function of depth through the layer. The gradient(s) influence the current density response of the device at different gate voltages. In some embodiments, the composition of an element (e.g. Ga) is greater at the interface between the metal-based semiconductor layer and the source/drain layers. The shape of the gradient profile is one of linear, stepped, parabolic, exponential, and the like. | 09-18-2014 |
20140264281 | Channel-Last Methods for Making FETS - Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts. | 09-18-2014 |
20140264252 | Current Selector for Non-Volatile Memory in a Cross Bar Array Based on Defect and Band Engineering Metal-Dielectric-Metal Stacks - Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages. | 09-18-2014 |
20140264241 | ZnTe on TiN or Pt Electrodes as a Resistive Switching Element for ReRAM Applications - Resistive random access memory (ReRAM) cells can include a ZnTe switching layer and TiN or Pt electrodes. The combination of the switching layer of ZnTe and the electrodes of TiN or Pt is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. High temperature anneal of the ZnTe switching layer can further improve the performance of the ReRAM cells. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD). | 09-18-2014 |
20140264239 | Using multi-layer MIMCAPs in the tunneling regime as selector element for a cross-bar memory array - Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device. | 09-18-2014 |
20140264231 | Confined Defect Profiling within Resistive Random Memory Access Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide. | 09-18-2014 |
20140264224 | Performance Enhancement of Forming-Free ReRAM Devices Using 3D Nanoparticles - Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents. | 09-18-2014 |
20140264223 | Metal Aluminum Nitride Embedded Resistors for Resistive Random Memory Access Cells - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and resistive switching layer connected in series. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state, thereby preventing over-programming. The embedded resistor includes aluminum, nitrogen, and one or more additional metals (other than aluminum). The concentration of each component is controlled to achieve desired resistivity and stability of the embedded resistor. In some embodiments, the resistivity ranges from 0.1 Ohm-centimeter to 40 Ohm-centimeter and remains substantially constant while applying an electrical field of up 8 mega-Volts/centimeter to the embedded resistor. The embedded resistor may be made from an amorphous material, and the material is operable to remain amorphous even when subjected to typical annealing conditions. | 09-18-2014 |
20140264155 | High-selectivity wet patterning of source-drain electrodes over taos for a bce device structure - Methods and formulations for the selective etching of etch stop layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution. Methods and formulations for the selective etching of molybdenum-based and/or copper-based source/drain electrode layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution. | 09-18-2014 |
20140262749 | Methods of Plasma Surface Treatment in a PVD Chamber - Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma processing can be performed in a same process chamber. The process chamber, configured to perform sputter deposition and plasma processing, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap. The plasma processing may include plasma etching or plasma surface treatment. | 09-18-2014 |
20140262028 | Non-Contact Wet-Process Cell Confining Liquid to a Region of a Solid Surface by Differential Pressure - An open-bottomed reactor cell for wet processing of substrates can be configured to confine a process liquid to an area under the cell (processing the “internal site”), or alternatively to exclude the process liquid from most of the area under the cell (processing the “external site”) without physical contact between the cell and substrate. A slight underpressure or overpressure maintained inside the main cavity of the cell causes the liquid to form a meniscus in the narrow gap between the cell and substrate rather than flowing outside the desired process area. An area under a peripheral channel outside the main cavity of the cell is shared by both the internal site and the external side, allowing the entire substrate to be processed. | 09-18-2014 |
20140261660 | TCOs for Heterojunction Solar Cells - Methods are used to develop and evaluate new materials and deposition processes for use as TCO materials in HJCS solar cells. The TCO layers allow improved control over the uniformity of the TCO conductivity and interface properties, and reduce the sensitivity to the texture of the wafer. In Some embodiments, the TCO materials include indium, zinc, tin, and aluminum. | 09-18-2014 |
20140256111 | Nonvolatile Memory Elements - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. | 09-11-2014 |
20140252565 | Nucleation Interface for High-K Layer on Germanium - A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO | 09-11-2014 |
20140247649 | Bipolar Resistive-Switching Memory with a Single Diode Per Memory Cell - According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell. | 09-04-2014 |
20140246640 | Doped Electrodes Used To Inhibit Oxygen Loss in ReRAM Device - A nonvolatile memory device and method for forming a resistive switching memory element, with improved lifetime and switching performance. A nonvolatile memory element includes resistive switching layer formed between a first and second electrode. The resistive switching layer comprises a metal oxide. One or more electrodes include a dopant material to provide the electrode with enhanced oxygen-blocking properties that maintain and control the oxygen ion content within the memory element contributing to increased device lifetime and performance. | 09-04-2014 |
20140235029 | Bipolar Multistate Nonvolatile Memory - Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. | 08-21-2014 |
20140231744 | Methods for forming resistive switching memory elements - Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication. | 08-21-2014 |
20140231704 | Silicon Texturing Formulations - The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. The current invention describes silicon texturing formulations that include at least one high boiling point additive. The high boiling point additive may be a derivative compound of propylene glycol or a derivative compound of ethylene glycol. Processes for texturing a crystalline silicon substrate using these formulations are also described. Additionally, a combinatorial method of optimizing the textured surface of a crystalline silicon substrate is described. | 08-21-2014 |
20140230955 | Systems for Discretized Processing of Regions of a Substrate - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 08-21-2014 |
20140217348 | Transition Metal Oxide Bilayers - Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen. | 08-07-2014 |
20140192586 | Resistive Random Access Memory Cells Having Variable Switching Characteristics - Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in a different manner. For example, some ReRAM cells may be restively switched using lower switching voltages than other cells. The cells may also have different data retention characteristics. These differences may be achieved by using different forming operations for different cells or, more specifically, flowing forming currents in different directions for different cells. The resulting conductive paths formed within the resistive switching layers are believed to switch at or near different electrode interfaces, i.e., within a so called switching zone. In some embodiments, a switching zone of a ReRAM cell may be changed even after the initial formation. | 07-10-2014 |
20140192585 | Resistive Random Access Memory Cell Having Three or More Resistive States - Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold. | 07-10-2014 |
20140191365 | DEVICE DESIGN FOR PARTIALLY ORIENTED RUTILE DIELECTRICS - Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm. | 07-10-2014 |
20140191262 | MATERIAL WITH TUNABLE INDEX OF REFRACTION - Devices are described including a component comprising an alloy of AlN and AlSb. The component has an index of refraction substantially the same as that of a semiconductor in the optoelectronic device, and has high transparency at wavelengths of light used in the optoelectronic device. The component is in contact with the semiconductor in the optoelectronic device. The alloy comprises between 0% and 100% AlN by weight and between 0% and 100% AlSb by weight. The semiconductor can be a III-V semiconductor such as GaAs or AlGaInP. The component can be used as a transparent insulator. The alloy can also be doped to form either a p-type conductor or an n-type conductor, and the component can be used as a transparent conductor. Methods of making and devices utilizing the alloy are also disclosed. | 07-10-2014 |
20140188264 | Workflow Manager and Bar Coding System for Processing of Samples/Substrates in HPC (High Productivity Combinatorial) R&D Environment - Methods of semiconductor processing are described. An experiment is designed for each process of a semiconductor substrate, which are implemented on respective multiple regions of the semiconductor substrate. A unique identifier is assigned to the semiconductor substrate. The respective design of experiment is implemented for each of the processes of the semiconductor substrate. Process criteria for each process is recorded, where the recording is associated with the assigned unique identifier. Process information is retrieved for each process, via its respective assigned unique identifier. | 07-03-2014 |
20140187052 | Selective Etching of Hafnium Oxide Using Diluted Hydrofluoric Acid - Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as silicon nitride and/or silicon oxide structures. Etching solutions and processing conditions described herein provide high etching selectivity of hafnium oxide relative to these other materials. As such, the hafnium oxide structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching selectivity of hafnium oxide relative to silicon oxide is at least about 10 and even at least about 30. Etching rates of hafnium oxide may be between 3 and 100 Angstroms per minute. A highly diluted water based solution of hydrofluoric acid, e.g., having a dilution ratio of 1000:1 to 10,000:1, may be used for etching to achieve these etching rates and selectivity levels. The solution may be maintained at a temperature of 25° C. to 90° C. during etching. | 07-03-2014 |
20140187051 | Poly Removal for replacement gate with an APM mixture - A method for removing poly-silicon dummy gate structures using an ammonium hydroxide-hydrogen peroxide-water (APM) solution with concentrations between 1:10:20 and 1:1:2 and at temperatures between 20 C and 80 C for times between 1 minute and 60 minutes. | 07-03-2014 |
20140187041 | High Dose Ion-Implanted Photoresist Removal Using Organic Solvent and Transition Metal Mixtures - Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact. | 07-03-2014 |
20140187018 | Methods for Reproducible Flash Layer Deposition - A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands. | 07-03-2014 |
20140187016 | High Work Function, Manufacturable Top Electrode - Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer. | 07-03-2014 |
20140187015 | Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer. | 07-03-2014 |
20140186995 | Method of fabricating cigs solar cells with high band gap by sequential processing - A method for forming TFPV absorber layer. A first layer including In is formed on a substrate. The first layer is partially or fully selenized to form a layer that includes In | 07-03-2014 |
20140186617 | Low-Emissivity Coatings - Embodiments of the present invention include low emissivity (low-E) coatings and methods for forming the coatings. The low-E coating comprises a self-assembled monolayer (SAM) on a glass substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the glass substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the low-E coating comprises an assembly of one or more monomeric subunits of the following structure: Si—(C | 07-03-2014 |
20140186598 | Base-layer consisting of two materials layer with extreme high/low index in low-e coating to improve the neutral color and transmittance performance - Low emissivity coated panels can be fabricated using a base layer having a low refractive index layer on a high refractive index layer. The low refractive index layer can have refractive index less than 1.5, and can include Mg F | 07-03-2014 |
20140185357 | Barrier Design for Steering Elements - Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element. | 07-03-2014 |
20140185034 | Method to Extend Single Wavelength Ellipsometer to Obtain Spectra of Refractive Index - Methods are provided to use data obtained from a single wavelength ellipsometer to determine the refractive index of materials as a function of wavelength for thin conductive films. The methods may be used to calculate the refractive index spectrum as a function of wavelength for thin films of metals, and conductive materials such as conductive metal nitrides or conductive metal oxides. | 07-03-2014 |
20140183737 | Diffusion Barriers - Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(C | 07-03-2014 |
20140183697 | High Work Function, Manufacturable Top Electrode - Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer. | 07-03-2014 |
20140183696 | Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer. | 07-03-2014 |
20140183695 | Methods for Reproducible Flash Layer Deposition - A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands. | 07-03-2014 |
20140183666 | Flourine-Stabilized Interface - Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSi | 07-03-2014 |
20140183664 | Fullerene-Based Capacitor Electrode - A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer. | 07-03-2014 |
20140183439 | CURRENT SELECTOR FOR NON-VOLATILE MEMORY IN A CROSS BAR ARRAY BASED ON DEFECT AND BAND ENGINEERING METAL-DIELECTRIC-METAL STACKS - Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages. | 07-03-2014 |
20140183436 | Nonvolatile Memory Device Having a Current Limiting Element - Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. | 07-03-2014 |
20140183432 | MoOx-Based Resistance Switching Materials - Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo | 07-03-2014 |
20140183161 | Methods and Systems for Site-Isolated Combinatorial Substrate Processing Using a Mask - Embodiments provided herein describe methods and systems for processing substrates. A substrate processing tool includes a housing having a sidewall and a lid. The housing defines a processing chamber. A substrate support is configured to support a substrate within the processing chamber. A plasma generation source is coupled to the housing and in fluid communication with the processing chamber through the lid of the housing. The plasma generation source is configured to provide a plasma activated species into the processing chamber. A mask is positioned within the processing chamber to at least partially shield the substrate from the plasma activated species. The mask includes a plurality of openings configured such that when the mask is in first and second positions, the plasma activated species passes through a respective first and second of the plurality of openings and causes first and second regions on the substrate to be processed. | 07-03-2014 |
20140183036 | In Situ Sputtering Target Measurement - Methods and systems for in situ measuring sputtering target erosion are disclosed. The emission of material from the sputtering target is stopped, a distance sensor is scanned across a radial line on the sputtering target. The sputtering chamber contains a controlled environment separate and distinct from the environment outside the chamber, and the controlled environment is maintained during the scanning The resulting distance data is converted into a surface profile of the sputtering target. The accuracy of the surface profile can be less than about ±1 μm. The distance sensor is protected from deposition of the material from the sputtering target. End-of-life for a sputtering target can be determined by obtaining a surface profile of the sputtering target at regular intervals and replacing the sputtering target when the thinnest location on the target as measured by the surface profile is below a predetermined threshold. | 07-03-2014 |
20140182670 | LIGHT TRAPPING AND ANTIREFLECTIVE COATINGS - Light trapping and antireflection coatings are described, together with methods for preparing the coatings. An exemplary method comprises forming a light trapping coating on a substrate and a conformal antireflection coating on the light trapping coating. The light trapping coating comprises particles embedded in a support matrix having a thickness between about one third and two thirds of the mean particle size. The mean particle size is between about 10 μm and about 500 μm. The index of refraction of the particles and support matrix is substantially the same as the index of refraction of the substrate at wavelengths of interest. The index of refraction of the conformal antireflection coating is approximately equal the square root of the index of refraction of the substrate. | 07-03-2014 |
20140182665 | Optical Absorbers - Optical absorbers, solar cells comprising the optical absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a layer comprising a semiconductor having a bandgap of between about 1.0 eV and about 1.6 eV on a substrate. The thickness of the layer is from about 1 to about 10 microns. The semiconductor comprises Fe, at least one Group IVA element, and at least one Group VIA element. The Group VIA element can be S, Se or Te. The Group IVA element can be Si or Ge. Typical compositions are Fe | 07-03-2014 |
20140179123 | Site-Isolated Rapid Thermal Processing Methods and Apparatus - Methods and apparatus are described that allow the investigation of process variables used in RTP systems to be varied in a combinatorial manner across a plurality of site-isolated regions designated in the surface of a substrate. The methods and apparatus allow process variables such as power, dwell time, light source, cooling gas composition, cooling gas flow rate, reactive gas composition, reactive gas flow rate, and substrate support temperature and the like to be investigated. | 06-26-2014 |
20140179113 | Surface Treatment Methods and Systems for Substrate Processing - Embodiments provided herein describe methods and systems for processing substrates. A plasma including radical species and charged species is generated. The charged species of the plasma are collected. A substrate is exposed to the radical species of the plasma. A layer is formed on the substrate after exposing the substrate to the radical species. | 06-26-2014 |
20140179112 | High Productivity Combinatorial Techniques for Titanium Nitride Etching - Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7% by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40° C. and 60° C. | 06-26-2014 |
20140179107 | Etching Silicon Nitride Using Dilute Hydrofluoric Acid - Provided are methods for processing semiconductor substrates or, more specifically, methods for etching silicon nitride structures without damaging photoresist structures that are exposed to the same etching solutions. In some embodiments, a highly diluted hydrofluoric acid is used for etching silicon nitride. A volumetric ratio of water to hydrofluoric acid may be between 1000:1 and 10,000:1. This level of dilution results in a low etching selectivity of photoresist to silicon nitride. In some embodiments, this selectivity is less than 0.2 and even less than 0.02. The solution may be kept at a temperature of between 60° C. and 90° C. to increase silicon nitride etching rates and to maintain high selectivity. The process may proceed until complete removal of the silicon nitride structure, while the photoresist structure may remain substantially intact. | 06-26-2014 |
20140179100 | Method to Control Depth Profiles of Dopants Using a Remote Plasma Source - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer. | 06-26-2014 |
20140179095 | Methods and Systems for Controlling Gate Dielectric Interfaces of MOSFETs - Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided. A metallic layer is deposited on the germanium oxide layer. The metallic layer may be nanocrystalline or amorphous. The deposition of the metallic layer causes the germanium oxide layer to be reduced such that a metal oxide layer is formed adjacent to the germanium channel. | 06-26-2014 |
20140179082 | Selective Etching of Hafnium Oxide Using Non-Aqueous Solutions - Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as one or more of silicon nitride, silicon oxide, polysilicon, and titanium nitride structures. Selected etching solution compositions and processing conditions provide high etching selectivity of hafnium oxide relative to these other materials. As such, hafnium oxide structures may be partially or completely removed without significant damage to other exposed structures made from these other materials. In some embodiments, the etching rate hafnium oxide is two or more times greater than the etching rate of silicon oxide and/or twenty or more times greater that the etching rate of polysilicon. The etching rate of hafnium oxide may be one and half times greater than the etching rate of silicon nitride and/or five or more times greater than the etching rate of titanium nitride. | 06-26-2014 |
20140179033 | Methods for Forming Templated Materials - Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure. | 06-26-2014 |
20140179030 | Dissolution Rate Monitor - A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a fluid to the respective reactors. A sealing element associated with each reactor contacts a surface of a substrate disposed below the reactor block, which defines isolated regions on the surface of the substrate. A dissolution rate monitor extends into each reactor to monitor a rate of real-time dissolution of one or more layers on the surface of the substrate when it is disposed proximate to the surface of the substrate. | 06-26-2014 |
20140178657 | ANTIREFLECTION COATINGS - Fluorine-doped antireflection coatings, methods for preparing the coatings and articles comprising the coatings are disclosed. The fluorine-doped antireflection coating comprises a fluorine-doped xerogel coating disposed on a substrate. The index of refraction of the xerogel coating is less than the index of refraction of the substrate, generally between about 1.15 and about 1.45. The fluorine atoms can be distributed uniformly through the thickness of the coating, disposed at the surface of the coating, or the distribution can be graded from the surface through the thickness of the coating. The methods comprise applying a coating precursor solution comprising a sol-gel precursor to a glass substrate, heating the coating to form a xerogel coating, and fluorine-doping the coating. The fluorine-doping can be performed by utilizing a coating precursor solution comprising a first fluorine source, contacting the cured coating with a second fluorine source, or a combination thereof. | 06-26-2014 |
20140178583 | Combinatorial Methods and Systems for Developing Thermochromic Materials and Devices - Embodiments provided herein describe methods and systems for evaluating thermochromic material processing conditions. A plurality of site-isolated regions on at least one substrate are designated. A first thermochromic material is formed on a first of the plurality of site-isolated regions on the at least one substrate with a first set of processing conditions. A second thermochromic material is formed on a second of the plurality of site-isolated regions on the at least one substrate with a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions. | 06-26-2014 |
20140178578 | Barrier Layers for Silver Reflective Coatings and HPC Workflows for Rapid Screening of Materials for Such Barrier Layers - Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium −25-30%, titanium and aluminum −30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer. | 06-26-2014 |
20140177378 | High Dilution Ratio by Successively Preparing and Diluting Chemicals - A system and method for providing a plurality of diluted solutions are disclosed. Successive dilution operations are performed upon mixing vessels substantially simultaneously. Measured source volumes of a source solution are placed into the mixing vessels. First measured volumes of a liquid are added to the mixing vessels. Measured first waste volumes are dispensed from the mixing vessels. Second measured volumes of the liquid are added to the mixing vessels. Measured second waste volumes are dispensed from the mixing vessels. Third measured volumes of the liquid are added to the mixing vessels. Each vessel has an individual target dilution ratio. Measured volumes and number of dilution operations are individual to each of the mixing vessels. | 06-26-2014 |
20140177315 | Multi-Level Memory Array Having Resistive Elements For Multi-Bit Data Storage - A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state. | 06-26-2014 |
20140177042 | Novel silver barrier materials for low-emissivity applications - A method for making low emissivity panels, including control the composition of a barrier layer formed on a thin conductive silver layer. The barrier structure can include an alloy of a first element having high oxygen affinity with a second element having low oxygen affinity. The first element can include Ta, Nb, Zr, Hf, Mn, Y, Si, and Ti, and the second element can include Ru, Ni, Co, Mo, and W, which can have low oxygen affinity property. The alloy barrier layer can reduce optical absorption in the visible range, can provide color-neutral product, and can improve adhesion to the silver layer. | 06-26-2014 |