GIGADEVICE SEMICONDUCTOR (BEIJING) INC. Patent applications |
Patent application number | Title | Published |
20160125952 | NONVOLATILE MEMORY ERASURE METHOD AND DEVICE - Disclosed are non-volatile memory erasure method and device for solving the problem of unnecessary time expenditure and complex process of the current erasure operation. The method comprises: after receiving an erasure instruction, performing a pre-reading verification on the target erasure area corresponding to the erasure instruction; if the pre-reading verification passes, then performing an erasure operation on the target erasure area; if not, then performing pre-programming verification on the target erasure area, and after the pre-programming verification passes, performing the erasure operation on the target erasure area. The method of the present application can eliminate the unnecessary pre-programming verification process while ensuring the target erasure area is in a full-erasure state before the erasure operation, thus saving erasure time and simplifying the erasure process. | 05-05-2016 |
20150348939 | ENHANCED FLASH CHIP AND METHOD FOR PACKAGING CHIP - An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins. | 12-03-2015 |
20150318044 | ENHANCED FLASH CHIP AND METHOD FOR PACKAGING CHIP - An enhanced Flash chip and a method for packaging chip, wherein the enhanced Flash chip comprising: a FLASH and a RPMC, packaged integrally; the FLASH and the RPMC each comprising: a first internal IO pin and a second internal IO pin; the FLASH and the RPMC being further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the FLASH or the RPMC and the other end of which is mutually connected to the first internal IO pin of the RPMC or the FLASH; the second internal IO pin of the FLASH and the second internal IO pin of the RPMC being mutually connected. The enhanced Flash chip provided in the present application may effectively reduce design complexity and chip manufacturing cost, avoid the crossing of the metal lead wires in the chip package, and increase the yield of chip packages. | 11-05-2015 |