FUJITSU SEMICONDUCTOR LIMITED Patent applications |
Patent application number | Title | Published |
20150311164 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer. | 10-29-2015 |
20150278415 | DESIGN METHOD AND DESIGN APPARATUS - When a design apparatus adjusts clock skews, the design apparatus separates each of the power supply currents which flow through circuit sections that operate in synchronization with a clock signal into a plurality of frequency components, sets skew values of the clock signal which reaches the circuit sections, and performs, by changing the skew values, repetition of calculating a combined amplitude by combining, with respect to each of the frequency components, corresponding ones of the frequency components of the power supply currents which flow through the circuit sections and finds dependence of the combined amplitude on a skew. | 10-01-2015 |
20150254392 | LAYOUT VERIFICATION METHOD AND VERIFICATION APPARATUS - A method of verifying a layout of a semiconductor integrated circuit is disclosed. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process, executing layout correction with respect to the first layout information, comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires, and adding, by a computer, an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis. | 09-10-2015 |
20150214151 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening. | 07-30-2015 |
20150195089 | DATA SCRAMBLE DEVICE, SECURITY DEVICE, SECURITY SYSTEM, AND DATA SCRAMBLE METHOD - A data scramble device includes an intermediate key generation unit configured to generate intermediate keys from random numbers, and an extended key generation unit configured to generate an extended key from intermediate keys generated by the intermediate key generation unit. Further, the data scramble device includes a scramble arithmetic operation unit configured to generate scramble data by performing a scramble arithmetic operation of target data and an extended key generated by the extended key generation unit. | 07-09-2015 |
20150194527 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE - A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate. | 07-09-2015 |
20150186679 | SECURE PROCESSOR SYSTEM WITHOUT NEED FOR MANUFACTURER AND USER TO KNOW ENCRYPTION INFORMATION OF EACH OTHER - A secure processor system capable of improving the security of processor processing by the addition of minimum modules without the need for a manufacturer and a user to know encryption information of each other has been disclosed. The secure processor system includes a secure processor having a CPU core that executes a instruction code, an encryption key hold part that holds a processor key, and an encryption processing part that encrypts or decrypts data input/output to/from the core with a processor key and a memory, and the encryption key hold part includes a hardware register that holds a hardwired encryption key, a write only register that stores an encryption key for instruction to be input and holds the stored encryption key for instruction so that it cannot be read, and the encryption key hold part outputs a hardware encryption key as a processor key at the time of activation and outputs a command encryption key as a processor key after a encryption key for instruction is written. | 07-02-2015 |
20150180671 | AUTHENTICATION SYSTEM, METHOD FOR AUTHENTICATION, AUTHENTICATION DEVICE AND DEVICE TO BE AUTHENTICATED - An authentication system includes a device to be authenticated and an authentication device. The device to be authenticated includes a first communication unit configured to transmit an instruction code and a first comparison value, and to receive a random number, a first memory unit, and a first control unit configured to create the first comparison value based on the random number, the common secret identification information and the instruction code. The authentication device includes a second communication unit configured to transmit the random number and to receive the instruction code and the first comparison value, a second memory unit, and a second control unit configured to generate the random number, create a second comparison value, compare the first comparison value with the second comparison value, and execute the instruction code when the first comparison value matches with the second comparison value. | 06-25-2015 |
20150178311 | RECORDING MEDIUM AND METHOD FOR FILE ACCESS - A method for file access includes accessing, by a processor, a file which is divided and stored in data area including a plurality of access units on the base of an access unit management table, the accessing including using a first table included in the access unit management table, the first table including a first management information corresponding to a first access unit and indicating that the first access unit and a second access unit following the first access unit in chains are located in continuous addresses and a second management information corresponding to the first access unit and indicating that the first access unit and the second access unit are located in discontinuous addresses, and using a second table included in the access unit management table, the second table including access unit identification information of the first and the second access units which are located in the discontinuous addresses. | 06-25-2015 |
20150160274 | METHOD AND APPARATUS FOR POWER ESTIMATION - A power estimation method includes acquiring power values consumed by a power estimation target apparatus, each of the power values corresponding to a plurality of parameters; calculating magnitude of variation in the power values in relation to a mean thereof; creating, when the magnitude of variation is less than a first value, a first power prediction formula approximating power consumption of the power estimation target apparatus by a constant which is the mean; calculating a degree of influence of each of the parameters on the power consumption when the magnitude of variation is the first value or more; creating, by reducing the number of the parameters based on the degree of influence, a second power prediction formula approximating the power consumption by a linear equation; and estimating the power consumption using one of the first and the second power prediction formulae. | 06-11-2015 |
20150081987 | DATA SUPPLY CIRCUIT, ARITHMETIC PROCESSING CIRCUIT, AND DATA SUPPLY METHOD - An data supply circuit includes a buffer configured to store a plurality of data items each having a first width, a memory access unit configured to read source data stored in memory and to store the source data as one or more data items each having the first width in the buffer, and a selection control unit configured to repeat multiple times an operation of reading a data item having a second width shorter than or equal to the first width to read a plurality of data items each having the second width contiguously and sequentially from the buffer and configured to continue to read from a head end of the source data upon a read portion reaching a tail end of the source data. | 03-19-2015 |
20150074626 | DETERMINING METHOD, COMPUTER PRODUCT, AND DETERMINING APPARATUS - A determining method includes obtaining terminal information indicating a first object terminal that is among terminals included among partial circuits and subject to determination of whether the first object terminal is an open terminal; obtaining for each terminal, connection information and first attribute information indicating an attribute of any one among an input terminal and an output terminal; generating, by a computer, for each terminal, second attribute information indicating an attribute opposite to the attribute indicated by the first attribute information; and determining, by the computer, whether a state of the first object terminal indicated by the terminal information becomes a high-impedance state, by simulating on the basis of the connection information and the second attribute information, a state of each terminal when a value of a terminal among the terminals and indicated as an output terminal by the second attribute information, is set at a first specified value. | 03-12-2015 |
20150074384 | SECURE BOOT METHOD, SEMICONDUCTOR DEVICE AND RECORDING MEDIUM - A secure boot method for a system, the system including a processor and a storage medium configured to store a program, a plurality of first partial hash values calculated based on a plurality of first partial programs into which the program is divided, and a first legitimate hash value which is a hash value calculated based on a plurality of first legitimate partial hash values, the plurality of first legitimate partial hash values being calculated based on a plurality of legitimate partial programs. The secure boot method includes calculating, a second calculated hash value based on the plurality of first partial hash values, and determining, whether or not the second calculated hash value matches the first legitimate hash value to continue the start-up processing of the system when the determination indicates match, and suspend the start-up processing of the system when the determination does not indicate match. | 03-12-2015 |
20150070201 | CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY - Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analogue-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analogue converter, wherein: the first switching-circuitry unit is configured to sample an input analogue signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analogue signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of clock signals have the same specifications as one another. | 03-12-2015 |
20150070199 | CIRCUITRY AND METHODS FOR USE IN MIXED-SIGNAL CIRCUITRY - A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring. | 03-12-2015 |
20150070077 | SIGNAL DISTRIBUTION CIRCUITRY - Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines. | 03-12-2015 |
20150036017 | IMAGING CONTROL UNIT, IMAGING APPARATUS, AND METHOD FOR CONTROLLING AN IMAGING APPARATUS - An imaging control unit includes: a calculating unit that obtains block brightness-values of a plurality of blocks from each pixel of an image data of a frame, the image data of a frame being divided into the plurality of blocks; a limiting unit that limits to a first limit brightness-value a block brightness-value which is larger than the first limit brightness-value among the plurality of block brightness-values; and a controlling unit that controls an exposure amount of an imaging unit so that a representing brightness-value of the plurality of the block brightness-values correspond to a target brightness-value which is less than first limit brightness-value. | 02-05-2015 |
20150028451 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING THE SAME - A semiconductor device includes: a semiconductor substrate having a memory cell array region and a peripheral circuit region; a ferroelectric capacitor formed over the semiconductor substrate in the memory cell array region; and a dummy capacitor formed over the semiconductor substrate in the peripheral circuit region, with a layered structure same as that of the ferroelectric capacitor, with an area larger than that of the ferroelectric capacitor, and with a line width not larger than the width of the ferroelectric capacitor. | 01-29-2015 |
20140377921 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer above the first region is patterned to form a gate electrode of an MIS-type transistor. | 12-25-2014 |
20140375869 | IMAGING APPARATUS AND IMAGING METHOD - An imaging apparatus includes an imaging unit that photographs an object through a lens; a memory unit that stores images captured by the imaging unit; an adjusting unit that adjusts a position of the lens, based on a value that is obtained from each of the images captured by the imaging unit and that represents an extent of focusing by the lens; a calculating unit that calculates a local maximum value of the value, based on temporal changes of the value that is obtained from each of the images successively captured by the imaging unit and that represents the extent of focusing by the lens; and a selecting unit that selects an image from among the images stored in the memory unit, based on differences of the local maximum value and the value obtained from each of the images and representing the extent of focusing by the lens. | 12-25-2014 |
20140367861 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging. | 12-18-2014 |
20140367791 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included. | 12-18-2014 |
20140367754 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes, forming, on a substrate, an element isolation insulating film which includes a protruding portion protruding above a level of a surface of the substrate, forming a first film on the substrate and on the element isolation insulating film, polishing the first film to expose the protruding portion, forming a first resist pattern which straddles the first film and the protruding portion after polishing the first film, patterning the first film using the first resist pattern as a mask to form a first pattern, and forming a sidewall film at side surfaces of the first pattern. | 12-18-2014 |
20140363984 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes forming a first resist film above a substrate, placing a first photomask, that includes a first mask pattern, in a first position above the first resist film, transferring the first mask pattern to the first resist film to form a first resist pattern above the substrate, forming a second resist film above the substrate after forming the first resist pattern, placing the first photomask in a second position above the second resist film, and transferring the first mask pattern to the second resist film to form a second resist pattern above the substrate. | 12-11-2014 |
20140359306 | SYSTEM, INFORMATION PROCESSING APPARATUS, SECURE MODULE, AND VERIFICATION METHOD - A system includes a secure module structured to prevent information stored therein from being externally referenced; and an information processing apparatus configured to enable communication with the secure module. The information processing apparatus includes a first computer configured to execute a first verification process of verifying whether an application under execution by the information processing apparatus is in a secure state. The secure module includes a second computer, and a storage unit configured to store at least any one among a first feature amount obtained by extracting a feature of execution code of the first verification process, and execution code of an authentication process of authenticating the first verification process. The second computer is configured to execute a second verification process of verifying whether the first verification process under execution by the first computer is in a secure state, based on stored contents of the storage unit. | 12-04-2014 |
20140354458 | SAR ANALOG-TO-DIGITAL CONVERSION METHOD AND SAR ANALOG-TO-DIGITAL CONVERSION CIRCUIT - An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at 1/4 or 3/4 of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step. | 12-04-2014 |
20140351387 | COMPUTER-READABLE MEDIUM STORING DATA EDITING PROGRAM - A non-transitory computer-readable medium storing a data editing program causing a computer to execute data editing processing, the data editing processing includes transferring insert data between a transfer start position and a transfer end position to a transfer insertion position; the transferring the insert data including: transferring transfer-start-back-data at and after the transfer start position in a transfer start cluster to a first new cluster; transferring transfer-end-forward-data at and before the transfer end position in a transfer end cluster to a second new cluster; transferring transfer-insertion-forward-data at and before the transfer insertion position or transfer-insertion-back-data at and after the transfer insertion position to the first or the second new cluster; and editing the management data, such that a cluster next to the transfer start cluster is linked after the first new cluster, and a cluster preceding the transfer end cluster is linked before the second new cluster. | 11-27-2014 |
20140347518 | IMAGE DATA PROCESSING APPARATUS AND METHOD THEREFOR - A write control unit selects, in a row or column direction, N storing units from N×N storing units for storing pixel data of N (N≧2) read lines of image pickup devices and writes the data in sets of N pixels thereto, and switches a selection direction for selecting the storing units each time writes of the data of N lines are completed. A read control unit selects, in a direction different from the selection direction, N storing units and starts parallel reads of the data of N lines during writes of the data of every N-th line. Each storing unit to be first selected in the writes of the data of every N-th line performs write and read operations using different terminals, and each of the remaining storing units performs write and read operations using a common terminal. | 11-27-2014 |
20140347141 | RESISTANCE ADJUSTING CIRCUIT AND RESISTANCE ADJUSTING METHOD - A resistance adjusting circuit including, a reference resistor, a first power source configured to output a first voltage, a first current source configured to output a first current based on a reference current set by using the reference resistor, a first variable resistor, a second current source configured to output a second current obtained by multiplying the first current by a reciprocal ratio, the reciprocal ratio being obtained as a reciprocal number of a ratio of a target resistance of the first variable resistor to a resistance of the reference resistor, and a controller configured to set a resistance of the first variable resistor so that a voltage at a second terminal of the reference resistor and a voltage at a connecting part of the first variable resistor and the second current source become equal to each other. | 11-27-2014 |
20140341581 | ISOLATING DIFFERENTIAL TRANSMISSION LINES - An apparatus includes a first differential transmission line and a second differential transmission line. The second differential transmission line is parallel to the first differential transmission line through an overlap region. The first differential transmission line includes a first line and a second line. The first differential transmission line includes N crossovers along the first differential transmission line through the overlap region at which the first line and the second line switch lanes with each other. N is equal to 1+INT {L/(λ/C)}, where L is a length of the overlap region, λ is a wavelength of a differential signal carried by the first or second differential transmission line, C is a constant, and INT {L/(λ/C)} is {L/λ/C)} rounded down to the nearest integer. | 11-20-2014 |
20140333370 | OUTPUT CIRCUIT AND VOLTAGE SIGNAL OUTPUT METHOD - An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power supply and an output node;
| 11-13-2014 |
20140333363 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having: a latch circuit having a plurality of data holding nodes; a first capacitance element connected to the first data holding node included in the plurality of data holding nodes; and a first switch element provided between the first data holding node and the first capacitance element. | 11-13-2014 |
20140333347 | COMPARATOR - A comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal. | 11-13-2014 |
20140327494 | TRANSMISSION CIRCUIT AND SIGNAL TRANSMISSION AND RECEPTION CIRCUIT - A transmission circuit includes a first path that connects a first terminal for inputting or outputting signals, and one of a pair of second terminals for outputting or inputting the signals; a second path that connects the first terminal and another one of the pair of second terminals; a first circuit including a first capacitor that is serially inserted in the first path, which is configured to perform single-differential conversion on signals transmitted through the first path, to perform impedance matching, and to supply a bias voltage; a second circuit including a first inductor that is serially inserted in the second path, which is configured to perform single-differential conversion on signals transmitted through the second path, to perform impedance matching, and to supply a bias voltage; and a switch that is connected between the two terminals of the pair of second terminals. | 11-06-2014 |
20140327143 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 11-06-2014 |
20140325468 | STORAGE MEDIUM, AND GENERATION APPARATUS FOR GENERATING TRANSACTIONS FOR PERFORMANCE EVALUATION - A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process comprising: generating a transaction scenario that describes a dependency between operations of semiconductor elements included in a semiconductor circuit, according to a parameter for defining the dependency and waveform data that indicates a level transition of each signal output from each of the semiconductor elements; and generating transactions for testing the semiconductor circuit, according to the transaction scenario. | 10-30-2014 |
20140320187 | BUFFER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock, and an adjustment circuit section adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of the measurement result of the measurement circuit section. | 10-30-2014 |
20140320176 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a transistor circuit including a power supply terminal and a back gate terminal; a variable resistance connected between a first voltage terminal and the power supply terminal; and a control circuit controlling the variable resistance based on a digital signal in which a difference voltage is converted when an absolute value of the difference voltage between a voltage of the first voltage terminal and a voltage of the back gate terminal is lower than a threshold value. | 10-30-2014 |
20140317378 | Scheduling in a Multicore Architecture - This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue. | 10-23-2014 |
20140310667 | CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, AND CIRCUIT DESIGN SUPPORT APPARATUS - A circuit-design support method of a computer includes obtaining circuit information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining control circuit information concerning a control circuit that has a first flip-flop for scanning and controls the value of a given signal line by a value set by the first flip-flop; selecting based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating based on the control circuit information, connection information indicating serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop. | 10-16-2014 |
20140306674 | CHARGE AND DISCHARGE SIGNAL CIRCUIT AND DC-DC CONVERTER - A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied. | 10-16-2014 |
20140306339 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion. | 10-16-2014 |
20140306319 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well, and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well. | 10-16-2014 |
20140304669 | VERIFICATION ITEM EXTRACTION APPARATUS AND METHOD - A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a verification subject circuit based on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined based on the connection relationships being derived. Related I/Fs, which are related to inputs to the logics and are interfaces to an outside of the verification subject circuit, are extracted based on the connection information. Second priority for verifying the related I/Fs is determined based on the first priority. | 10-09-2014 |
20140300394 | DRIVE CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND CONTROL METHOD OF DRIVE CIRCUIT - A drive circuit including a second switching element that is connected in series to a source of a first switching element, that is switched ON when the first switching element is switched ON, and that is switched OFF when the first switching element is switched OFF. The drive circuit includes a conduction element that is provided between a drain of the second switching element and a power line, and that connects the drain of the second switching element to the power line in accordance with a signal that switches the second switching element OFF. | 10-09-2014 |
20140299987 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-09-2014 |
20140299965 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched. | 10-09-2014 |
20140298279 | CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, AND CIRCUIT DESIGN SUPPORT APPARATUS - A circuit design support method includes obtaining shared circuit information indicating various types of shared circuits each executing at least any one of various types of logical computations and causing plural signal lines to share an observation point at which a signal value is observable; determining for each of the signal lines to be observed in a circuit under-design, a value based on controllability representing ease of control to set a value of the signal line to be a specific value; selecting based on the obtained shared circuit information, any one shared circuit among the various types of shared circuits; and generating correlation information that correlates each input terminal of the selected shared circuit with a signal line among the signal lines to be observed and whose value determined therefor is equal to a non-controlling value of a logical computation executed for an input signal input into the input terminal. | 10-02-2014 |
20140297906 | BUFFER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A buffer circuit includes: a register array including registers in a plurality of stages; and a control circuit configured to rearrange a plurality of pieces of received data in the register in a determined transfer order and to control the register array to sequentially output the plurality of pieces of received data as one piece of transfer data when all the received data is stored, wherein the control circuit controls the register array to store stored data in each register in a preceding stage when the register array outputs the received data, and the control circuit determines a write register in accordance with the transfer order when the register array newly stores the received data and controls the register array to store data stored in the write register in a following stage of the write register and to store the new received data in the write register. | 10-02-2014 |
20140295781 | POWER AMPLIFIER AND COMMUNICATION DEVICE - A power amplifier, includes: a first and a second amplifier circuits that are controlled so that one of them do not amplify a signal when another one of them amplifies the signal; a first impedance conversion circuit, coupled between the first amplifier circuit and the output terminal, that converts an output impedance of the first amplifier circuit; a second impedance conversion circuit, coupled between the second amplifier circuit and a wiring coupling the first impedance conversion circuit and the output terminal, that converts an output impedance of the second amplifier circuit; and a connection circuit that, when the first amplifier circuit amplifies the signal, forms a path which bypasses the second impedance conversion circuit between a reference potential and the wiring coupling the first impedance conversion circuit and the output terminal, by coupling a wiring coupling the first amplifier circuit and the output terminal, with the reference potential. | 10-02-2014 |
20140294130 | RECEIVER AND SIGNAL PROCESSING METHOD - A receiver includes a detector to detect an interfered-with carrier from a received and demodulated signal, a fast Fourier transform computation part to perform fast Fourier transform to convert a time domain signal to a frequency domain signal and adjust an output power level of a desired carrier wave contained in the frequency domain signal based upon the detected interfered-with carrier, and a channel estimation part to estimate a channel characteristic based upon a non-interfered-with pilot signal that is not subject to influence of the interfered-with carrier and an interpolation value interpolated based upon the non-interfered-with pilot signal, the non-interfered-with pilot signal being obtained by removing, based upon the interfered-with carrier, an interfered-with pilot signal that is subject to the influence of the interfered-with carrier and an interpolation value interpolated based upon the interfered-with pilot signal. | 10-02-2014 |
20140294128 | RECEIVER AND SYNCHRONIZATION CORRECTING METHOD - A receiver includes a transformation part configured to convert a time domain received signal to a frequency domain signal, a known signal extraction part configured to extract a known signal from the frequency domain signal, an estimation part configured to estimate a channel characteristic based upon the extracted known signal, a time direction extraction part configured to extract channel characteristic values of a particular carrier in a time direction from the estimated channel characteristic, a power spectrum acquiring part configured to acquire a power spectrum from the channel characteristic values extracted in the time direction, an error calculation part configured to calculate a carrier frequency error from the power spectrum, and a carrier correction part configured to correct for a carrier frequency of the received signal based upon the carrier frequency error. | 10-02-2014 |
20140293852 | WIRELESS COMMUNICATION NETWORK SYSTEM, WIRELESS COMMUNICATION STATION, WIRELESS COMMUNICATION DEVICE, AND BATTERY CONSUMPTION SMOOTHING METHOD - A wireless communication network system includes a first wireless communication device; and second wireless communication devices. The first wireless communication device selects a master unit from among the second wireless communication devices, on the basis of reception quality and storage battery remaining levels, and sends, to the selected master unit, a master unit request and a storage battery remaining level threshold for the master unit. The selected second wireless communication device operates as the master unit in accordance with the master unit request, and monitors the storage battery remaining level of the selected second wireless communication device on the basis of the storage battery remaining level threshold. When the storage battery remaining level of the selected second wireless communication device does not match the storage battery remaining level threshold, the selected second wireless communication device sends a master unit change request to the first wireless communication device. | 10-02-2014 |
20140293716 | SWITCHING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A switching circuit includes a first well and a second well formed in a semiconductor substrate; a first transistor being connected with a first node at one end, and the first transistor being formed in the first well; a second transistor being connected with another end of the first node at one end, and connected with a second node at another end, and the second transistor being formed in the second well; and a potential control circuit that connects the second well with the first node during a predetermined period including a period for the first transistor and the second transistor to transition from off to on in a state where potential of the second node is lower than potential of the first node, and connects the second well with the second node after the predetermined period. | 10-02-2014 |
20140292379 | OUTPUT CIRCUIT - An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power source and an output node; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power source and the output node; a first capacitive coupling part connected between a gate of the first PMOS transistor and gates of the second PMOS transistor and the second NMOS transistor; and a second capacitive coupling part connected between a gate of the first NMOS transistor and gates of the second NMOS transistor and the second PMOS transistor, a first bias voltage is applied to the gate terminal of the second PMOS transistor, and a second bias voltage is applied to the gate terminal of the second NMOS transistor. | 10-02-2014 |
20140291864 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-02-2014 |
20140291863 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-02-2014 |
20140291862 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-02-2014 |
20140291861 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-02-2014 |
20140291807 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first well of a first conductivity type formed within the substrate, a second well of a second conductivity type formed underneath the first well within the substrate and a third well of the second conductivity type formed horizontally to the first well within the substrate, and including a first region formed to a first depth from a surface of the substrate, and a second region formed to a second depth greater than the first depth from the surface of the substrate and connected to the second well. | 10-02-2014 |
20140289491 | DATA PROCESSING DEVICE - A data processing device has: a shift circuit that makes data with a certain bit length to be input therein for each cycle, and shifts the data to delete first invalid data in the data; and a gate circuit that cuts, when data as a result of combining pieces of the shifted data for each cycle has the certain bit length or more, first data with the certain bit length to output the data to an outside. | 09-25-2014 |
20140285250 | SIGNAL GENERATION CIRCUIT - A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal. | 09-25-2014 |
20140285243 | POWER ON RESET CIRCUIT, POWER SUPPLY CIRCUIT, AND POWER SUPPLY SYSTEM - A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active. | 09-25-2014 |
20140273453 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring. | 09-18-2014 |
20140270022 | DATA SIGNAL CORRECTION CIRCUIT, RECEIVER, AND DATA SIGNAL CORRECTION METHOD - A data signal correction circuit includes a channel characteristic calculator unit configured to calculate a channel characteristic estimate value of a received data signal on the basis of a pilot signal, a path detector unit configured to determine a delay quantity of multipath propagation of the received data signal on the basis of the calculated channel characteristic estimate value, and an adaptive filter configured to receive the delay quantity and the channel characteristic estimate value as input items, adjust an input interval of the channel characteristic estimate value along a carrier frequency axis in accordance with the delay quantity, and perform adaptive equalization on the channel characteristic estimate value inputted to the adaptive filter at the adjusted input interval. | 09-18-2014 |
20140269872 | RECEIVER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND TEST METHOD - A receiver circuit includes a CDR circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude). The test pattern generator unit generates a test pattern to which the jitter is added, and supplies the test pattern to the CDR circuit. The comparator unit compares a value outputted from the CDR circuit with an expected value and outputs a comparison result. | 09-18-2014 |
20140269136 | POWER SUPPLY CIRCUIT AND SEMICONDUCTOR DEVICE - An output transistor coupled between an input terminal where an input voltage is input and an output terminal where an output voltage is output; an error amplifier configured to generate a first error signal and a second error signal based on a voltage in accordance with the output voltage and a reference voltage, and to output the first error signal to a gate terminal of the output transistor; an anti-overshoot circuit coupled to the output terminal and controlled by the second error signal; an output transistor control part configured to add a control signal based on a first current in accordance with an AC component of the output voltage to the first error signal; and a sensitivity adjustment part configured to decrease the first current based on the second error signal when the output voltage is higher than a certain voltage. | 09-18-2014 |
20140252490 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including a semiconductor device including a substrate, a nitride semiconductor layer formed over the substrate and including an active region and an element isolation region, inert atoms being introduced into the element isolation region, a source electrode formed over the nitride semiconductor layer in the active region, a gate electrode formed over the nitride semiconductor layer in the active region away from the source electrode, and a drain electrode formed over the nitride semiconductor layer in the active region away from the gate electrode, the drain electrode including an end portion provided away from a boundary between the element isolation region and the active region by a first distance, wherein the first distance is greater than a second distance, the second distance being a distance where a concentration of the inert atoms diffused from the element isolation region into the active region becomes a first concentration, and an electron density in the active region at a position where the concentration of the inert atoms is higher than the first concentration is lower than an electron density in a center portion of the active region. | 09-11-2014 |
20140244981 | PROCESSOR AND CONTROL METHOD FOR PROCESSOR - A processor includes a programmable logic circuit provided with a plurality of processing units. The programmable logic circuit is capable of reconfiguring a first logic circuit corresponding to first circuit configuration information according to a first process and a second logic circuit corresponding to second circuit configuration information according to a second process. Each of the first and second logic circuits includes an information holding unit. A first control circuit stores the second circuit configuration information in the information holding unit of the first logic circuit and generates an execution control signal for executing the first process. A second control circuit obtains the second circuit configuration information from the information holding unit of the first logic circuit in response to completion of the first process and controls the programmable logic circuit so as to reconfigure the second logic circuit corresponding to the second circuit configuration information. | 08-28-2014 |
20140240151 | ANALOG-TO-DIGITAL CONVERSION DEVICE - An analog-to-digital conversion device includes: an analog-to-digital converter that receives an analog voltage and converts the analog voltage into a digital value to output the converted digital value; and an offset correction unit that arithmetically operates an offset correction value based on a first digital value and a second digital value, the first digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a first analog voltage, the second digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a second analog voltage, the second analog voltage having a voltage value different from that of the first analog voltage, in which after the arithmetic operation of the offset correction value, the analog-to-digital converter outputs a digital value obtained by subtracting the offset correction value from the converted digital value. | 08-28-2014 |
20140239456 | SEMICONDUCTOR WAFER AND ITS MANUFACTURE METHOD, AND SEMICONDUCTOR CHIP - A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer. | 08-28-2014 |
20140237012 | PSEUDORANDOM NUMBER GENERATING CIRCUIT AND METHOD - A pseudorandom number generating circuit includes: a first generator including a shift register and configured to generate a first pseudorandom number, the shift register including registers, the first pseudorandom number having a plurality of bits corresponding to the registers; a second generator configured to generate a second pseudorandom number; and a selector configured to select a bit that is to be output from the plurality of bits by using the second pseudorandom number. | 08-21-2014 |
20140237010 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND COMPUTER PRODUCT - A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit. | 08-21-2014 |
20140235045 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A hard mask formed above a gate film is patterned with a first mask pattern, the patterned hard mask film is processed into a gate pattern with a second mask pattern, the gate film is patterned with the hard mask film as a mask, a spacer insulating film is formed, a third mask pattern covering an edges of the gate pattern is formed above the spacer insulating film, the spacer insulating film is etched with the third mask pattern as a mask, and a sidewall insulating film is formed on side walls of the gate film leaving the spacer insulating film in a region of the edge of the gate pattern. | 08-21-2014 |
20140235022 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions. | 08-21-2014 |
20140217567 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of the concave part. The front edge portion of the pillar electrode is exposed from the concave part of the resin, which makes it possible to suppress increase in the height of the pillar electrode and to form the pillar electrodes having fine patterns or a narrow pitch. | 08-07-2014 |
20140217153 | BONDING APPARATUS AND BONDING METHOD - To provide a bonding apparatus capable of increasing product quality by realizing high-precision control of a pressing force applied upon mounting of an electronic component on a substrate by bonding, and to a bonding method capable of providing high-quality products stably. The bonding apparatus includes: at least a bonding head | 08-07-2014 |
20140215423 | SEMICONDUCTOR DEVICE DESIGN METHOD AND DESIGN APPARATUS - A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section. | 07-31-2014 |
20140214355 | METHOD AND APPARATUS FOR VERIFYING CIRCUIT DESIGN - A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit. | 07-31-2014 |
20140213251 | WIRELESS COMMUNICATION CONTROLLING DEVICE, WIRELESS COMMUNICATION SYSTEM, AND WIRELESS COMMUNICATION CONTROLLING METHOD - A wireless communication controlling device for controlling a communication between a wireless terminal and a server via a base station, the wireless communication controlling device including: a receiver configured to receive a request of a service for the server, time data of the service, location data of the wireless terminal, quality data of the wireless communication channel, and service data of the service, and a processor configured to estimate a communication speed for the service in accordance with the time data and the location data, to determine a quality threshold and a speed threshold respectively, in accordance with the location data and the service data, and to determine whether to grant the request of the service for the server or not, in accordance with a comparison between the quality data and the quality threshold and a comparison between the estimated communication speed and the speed threshold. | 07-31-2014 |
20140212032 | IMAGE PROCESSING APPARATUS, METHOD AND IMAGING APPARATUS - An image processing apparatus includes an extraction section that extracts a first high brightness region from a source image where brightness is a first threshold value or greater, a mask generation section that performs blur processing and binarization processing on the first high brightness region and generates a mask containing the first high brightness region, a mask application section that based on the mask performs elimination processing, thinning processing, or both on the first high brightness region, a bright line generation section that generates a bright line based on a second high brightness region contained in output of the mask application section, and a synthesizing section that synthesizes the bright line onto the source image. | 07-31-2014 |
20140211898 | PHASE INTERPOLATION CIRCUIT AND RECEIVER CIRCUIT - A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal. | 07-31-2014 |
20140210657 | D/A CONVERTER - A digital-to-analog (D/A) converter includes first resistors coupled in series, second resistors respectively coupled to the first resistors and each having a resistance twice as large as the resistance of the first resistor, and first switch circuits respectively coupled to the second resistors. Third resistors each have a resistance twice as large as the resistance of the first resistor. Second switch circuits each are coupled to the third resistors and a GND wire. A control circuit controls the first and second switch circuit in accordance with the digital input signals to set a state of a connection node to either one of a first voltage, a second voltage, and a high impedance. | 07-31-2014 |
20140210561 | RING OSCILLATOR AND SEMICONDUCTOR DEVICE - There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition. | 07-31-2014 |
20140210445 | POWER SUPPLY CONTROL CIRCUIT, POWER SUPPLY DEVICE, ELECTRONIC APPARATUS, AND POWER SUPPLY CONTROL METHOD - A control circuit includes a detection circuit configured to detect a load current flowing into a load, and a setting circuit configured to set switching operations on first and second switch circuits according to the load current. The setting circuit is configured to cause both the first switch circuit and the second switch circuit to be in an off state, when a power supply stop signal is input from an outside, if the load current is in a first range, and to cause the first switch circuit to perform an on-off operation on the basis of the output voltage while causing the second switch circuit to be in the off state, if the load current is higher than a first reference value that is an upper limit of the first range. | 07-31-2014 |
20140205193 | IMAGE PROCESSING APPARATUS, METHOD AND IMAGING APPARATUS - An image processing apparatus includes a histogram computation section that for a plurality of images with different light exposure amounts captured, computes for each of the images a histogram of the number of pixels a light exposure amount ratio computation section that, based on a degree of similarity between a profile of a first histogram computed from a first image out of the plurality of images and a profile of a second histogram computed from a second image out of the plurality of images, computes as a light exposure amount ratio a ratio between a light exposure amount for the first image and a light exposure amount for the second image, and a pixel value adjustment section that adjusts the pixel values of pixels contained in one image out of the first image and the second image based on the light exposure amount ratio. | 07-24-2014 |
20140203291 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an FET chip; pads provided on an upper surface of the FET chip; bumps provided on at least one of the pads; leads having first portions that are connected to the FET chip by the bumps and extend along the upper surface of the FET chip, and second portions that contact surfaces of the first portions along the upper surface of the FET chip and extend along a side surface of the FET chip, the first and second portions being formed by press or cutting; and a seal layer that seals the FET chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the FET chip. | 07-24-2014 |
20140201582 | SCAN CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain. | 07-17-2014 |
20140197533 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element. | 07-17-2014 |
20140193960 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF DYNAMIC THRESHOLD TRANSISTOR - A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion. | 07-10-2014 |
20140191889 | ANALOG-DIGITAL CONVERSION CIRCUIT AND METHOD - An analog-digital conversion circuit includes a comparator that receives an analog input signal. A controller generates an N1-bit first signal and an N2B-bit second signal in accordance with an output signal from the comparator. A first digital-analog converter generates a first reference signal from the first signal. A second digital-analog converter generates a second reference signal from the second signal. A correction circuit corrects the first and second signals to generate a digital output signal. The N2B-bit second signal is acquired by adding a Kbit correction signal to an N2A-bit signal. The controller sequentially sets bit values of the first signal and bit values of the second signal in accordance with the output signal of the comparator. The correction circuit generates the (N1+N2A)-bit digital output signal based on a sum of a value acquired by multiplying the N1-bit first signal by 2̂N2A and a value of the N2B-bit second signal. | 07-10-2014 |
20140191328 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region. | 07-10-2014 |
20140191327 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well. | 07-10-2014 |
20140191288 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process. | 07-10-2014 |
20140187000 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a circuit substrate, a first semiconductor chip disposed on the circuit substrate, a plurality of first spacers disposed on the first semiconductor chip, a second semiconductor chip which includes a first adhesive agent layer on a lower face thereof and is disposed on upper portions of the plurality of spacers, a wire which connects the circuit substrate to the first semiconductor chip, and a first sealing material which seals a gap between the first semiconductor chip and the first adhesive agent layer, wherein each height of the plurality of the first spacers is greater than height of the wire relative to an upper face of the first semiconductor chip. | 07-03-2014 |
20140184298 | ELECTRIC CIRCUIT AND SEMICONDUCTOR DEVICE - An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied. | 07-03-2014 |
20140179098 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts. | 06-26-2014 |
20140179081 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer. | 06-26-2014 |
20140179072 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL SEMICONDUCTOR LAYER ABOVE IMPURITY LAYER - The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film. | 06-26-2014 |
20140173718 | MICROCOMPUTER, MIDDLEWARE, AND OPERATING METHOD FOR THE SAME - A microcomputer has a processing unit; a plurality of registers; a storage storing hardware initialization data that includes an initial value and a register address in which the initial value is set, the processing unit performing a process including: setting the initial value in a register having the register address based on the hardware initialization data; performing a functional capability limitation releasing processing to determine whether authentication data in an authentication register, which is selected in advance from the plurality of registers, is correct based on an authentication information for releasing limitations on a functional capability of a function, and to put a function corresponding to the authentication information into an executable state when the authentication data is correct; and executing the function which is put into the executable state to realize the functional capability of the executed function. | 06-19-2014 |
20140170814 | BALL GRID ARRAY SEMICONDUCTOR DEVICE AND ITS MANUFACTURE - A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts. | 06-19-2014 |
20140169638 | SPOT SEARCH DEVICE AND SPOT SEARCH METHOD - A spot search device which searches, based on image data of pattern light, a moved spotlight representing any of the plurality of spotlights that has moved, the spot search device includes, a first movement amount generating unit which detects the moved spotlight and calculates a first movement amount based on first image data, a second movement amount generating unit which, based on the first movement amount and a distance, calculates a second movement amount of the moved spotlight in second image data; and a spotlight position predicting unit which, when a velocity and an area of the moved spotlight calculated from at least two pieces of frame image data satisfy reference values, detects the moved spotlight as a same object moved spotlight group and predicts a predicted moved spotlight position of the same object moved spotlight group in a next frame, based on movement information. | 06-19-2014 |
20140169635 | DISTANCE MEASUREMENT APPARATUS AND DISTANCE MEASUREMENT METHOD - A distance measurement apparatus which outputs a plurality of spot beams in a grid-like pattern from a laser device to a target object and measures a distance to the target object based on image data of the plurality of spot beams, the apparatus includes a distance measurement unit configured to obtain the distance to the target object based on positions of the plurality of spot beams in the image data; and a control unit configured to perform, based on the image data, when a size of each of the spot beams is larger than a reference size, either one or both of a first control operation of reducing a diameter of laser light output from the laser device and a second control operation of increasing a shutter speed of an image sensing device which generates the image data. | 06-19-2014 |
20140169071 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped. | 06-19-2014 |
20140167992 | CAPACITIVE ELEMENT, CAPACITOR ARRAY, AND A/D CONVERTER - A capacitive element includes first electrodes and second electrodes that are alternately arranged in a concentric form. Each of the first electrodes and the second electrodes is formed with closed loop form, in at least one wiring layer provided on or above a substrate. | 06-19-2014 |
20140167824 | QUANTIZER, COMPARATOR CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A quantizer takes an analog signal as input and produces a quantized signal for output. The quantizer includes a shoot-through current detection unit and a feedback unit. The shoot-through current detection unit is configured to detect a shoot-through current flowing through the quantizer. The feedback unit is configured to feed back a signal from the shoot-through current detection unit and control an electric charge stored at an input of the quantizer. | 06-19-2014 |
20140167721 | POWER SUPPLY DEVICE - A power supply device includes: a first transistor that switches a first current flowing between a first terminal and a second terminal of the first transistor; a second transistor that has a first terminal connected to the first terminal of the first transistor and a control terminal connected to a control terminal of the first transistor and is formed in a chip in which the first transistor is formed; a current source that supplies a second current between the first and second terminals of the second transistor; and a control part that performs a turn-on and turn-off control of the first transistor on the basis of voltages of the second terminals of the first and second transistors. | 06-19-2014 |
20140167246 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point. | 06-19-2014 |
20140159685 | CONTROL DEVICE AND POWER SUPPLY DEVICE - A control device includes: a control circuit that controls a power supply circuit by a feedback of an output from an output terminal, the power supply circuit having a first transistor, the first transistor including gallium nitride material and having a source and a drain connected so that one of the source and the drain is connected to a first power supply and an other of the source and the drain is connected to the output terminal; and a first terminal via which a first control signal output by the control circuit is output to a gate of the first transistor. | 06-12-2014 |
20140152482 | COMPARATOR AND CORRECTION METHOD THEREFOR - A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value. | 06-05-2014 |
20140145692 | POWER SUPPLY DEVICE AND METHOD FOR CONTROLLING POWER SUPPLY - A power supply device includes a coil, a first switch circuit that accumulates energy in the coil, and a plurality of second switch circuits that couple the coil to a plurality of output terminals. A first control unit generates a first control signal that controls the first switch circuit to turn on and off based on a combined value of a plurality of output voltages respectively output from the plurality of output terminals and a first reference value. A second control unit generates a second control signal that controls the plurality of second switch circuits to turn on and off in a cycle that is the same as the first control signal based on a first output voltage of the plurality of output voltages and a second reference value. | 05-29-2014 |
20140145336 | SEMICONDUCTOR DEVICE INCLUDING TWO GROOVE-SHAPED PATTERNS - The semiconductor device has insulating films | 05-29-2014 |
20140145335 | SEMICONDUCTOR DEVICE INCLUDING TWO GROOVE-SHAPED PATTERNS - The semiconductor device has insulating films | 05-29-2014 |
20140138769 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface. | 05-22-2014 |
20140134754 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 05-15-2014 |
20140133568 | MOVING IMAGE PROCESSING APPARATUS - A moving image processing apparatus has an encoder unit configured to include a plurality of encoders which respectively encode a plurality of divided images into which images of a moving image are divided in such a manner that each divided image includes an overlapped area to generate encoded divided image data; and a decoder unit configured to include a plurality of decoders which respectively decode the plurality of encoded divided image data inputted from the encoder unit and respectively extract information on motion vectors of the divided images; and a composition unit which blends a plurality of decoded divided images decoded and generated by the plurality of decoders respectively in the overlapped area to output the images of the moving image. And the composition unit determines a blend ratio of the overlapped area based on the information on the motion vectors. | 05-15-2014 |
20140133252 | PARALLEL-SERIAL CONVERSION CIRCUIT, INTERFACE CIRCUIT, AND CONTROL DEVICE - A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal. | 05-15-2014 |
20140132322 | INPUT CIRCUIT - An input circuit includes a first P-channel MOS transistor including a first terminal supplied with a high-potential power supply voltage and a second terminal coupled to a first node, a second P-channel MOS transistor including a first terminal coupled to the first node and a second terminal coupled to a second node, a first N-channel MOS transistor including a first terminal coupled to the second node and a second terminal coupled to a third node, and a second N-channel MOS transistor including a first terminal coupled to the third node and a second terminal supplied with a low-potential power supply voltage. An input signal is supplied to gate terminals of the P-channel MOS transistors and the N-channel MOS transistors. A control circuit controls the potential at the first node and the potential at the third node based on the input signal and the potential at the second node. | 05-15-2014 |
20140131873 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor. | 05-15-2014 |
20140131860 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC DEVICE - A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element. | 05-15-2014 |
20140129889 | SEMICONDUCTOR INTEGRATED CIRCUIT - A state machine; a BIST circuit including a test pattern generator and an expected value comparison circuit; a state monitoring circuit configured to monitor whether or not a state of the state machine is a specific state; and a transition request detection circuit configured to detect a transition request signal from the specific state to a next state, are held. When the state monitoring circuit decides that the state of the state machine is the specific state, the state machine outputs a signal indicating the specific state as a state output of the state machine, and the BIST circuit performs a test of the state machine. When the transition request detection circuit detects the transition request signal while the test is performed, the BIST circuit stops the test of the state machine. | 05-08-2014 |
20140127613 | REFLECTIVE MASK AND METHOD FOR MANUFACTURING THE SAME - A reflective mask includes a substrate and a multilayer reflective film formed on the substrate. An absorption pattern is formed on the multilayer reflective film. A recess is formed in the multilayer reflective film in a peripheral region of the absorption pattern. | 05-08-2014 |
20140124930 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 05-08-2014 |
20140117562 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole. | 05-01-2014 |
20140113441 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film. | 04-24-2014 |
20140113422 | SEMICONDUCTOR DEVICE WITH POCKET REGIONS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth. | 04-24-2014 |
20140112065 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a memory cell of static type; a word line connected to the memory cell; a word driver driving the word line; and a compensating circuit including a first transistor of N-channel type having a drain connected to the word line and a source to be connected to a ground potential, and a control circuit connected to the first transistor and changing the first transistor from an OFF state to an ON state based on a rise of an ambient temperature or a rise of a power source voltage to thereby lower a voltage of the word line. | 04-24-2014 |
20140111672 | IMAGE PROCESSING DEVICE AND IMAGE CAPTURE DEVICE - A first distortion correction unit generates one first output pixel based on two input pixels that are adjacent in a first direction out of a plurality of input pixels included in image data pieces of a captured frame. A second distortion correction unit generates one second output pixel based on two first output pixels that are adjacent in a second direction different from the first direction. The second distortion correction unit successively reads two first output pixels adjacent in the second direction from a storage unit based on input coordinates, which correspond to coordinate values of second output pixels, and generates the one second output pixel by applying linear interpolation processing to the read two first output pixels based on interpolation coefficient. | 04-24-2014 |
20140111181 | ELECTRONIC CIRCUIT AND SEMICONDUCTOR DEVICE - An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages. | 04-24-2014 |
20140110712 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner. | 04-24-2014 |
20140108848 | PROCESSOR AND CONTROL METHOD FOR PROCESSOR - A processor includes a plurality of processing units. A plurality of first arbitration units each arbitrate request signals output from at least two of the processing units to generate a first arbitration signal. A second arbitration unit arbitrates first arbitration signals output from the first arbitration units to generate a second arbitration signal. A plurality of clock controllers, arranged in correspondence with the first arbitration units, each generate a clock signal supplied to a corresponding first arbitration unit and the processing units coupled to the corresponding first arbitration unit. A control unit determines whether or not to operate each processing unit in accordance with an operation state of the processor and generates control information according to the determination result. Each of the clock controllers supplies or stops the clock signal or changes a frequency of the clock signal in accordance with the control information. | 04-17-2014 |
20140098582 | BRIDGE RECTIFIER CIRCUIT - A bridge rectifier circuit has first to fourth diode groups which are bridge-connected and each include a main diode and sub-diodes being enabled to be respectively connected in parallel to the main diode, first and second input terminals to which AC power is supplied, a first output terminal connected to the first input terminal via the first diode group and connected to the second input terminal via the second diode group, a second output terminal connected to the first input terminal via the third diode group and connected to the second input terminal via the fourth diode group, and a control circuit configured to detect a current flowing through at least one diode group and increases the number of sub-diodes connected in parallel to the main diode of the diode group through which the detected current flows in accordance with an increase in the detected current. | 04-10-2014 |
20140097978 | AD CONVERSION CIRCUIT, SEMICONDUCTOR DEVICE, AND AD CONVERSION METHOD - A reference voltage generator generates a reference voltage at the time of sampling a received input signal. A sampling time controller detects a change in the reference voltage. When the reference voltage rises to a determined threshold, the sampling time controller determines that sampling is completed, and generates a sampling clock in which sampling time is controlled on the basis of an external clock. | 04-10-2014 |
20140097861 | SEMICONDUCTOR DEVICE AND TEST METHOD - A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion. | 04-10-2014 |
20140096101 | SEMICONDUCTOR DEVICE AND DESIGNING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has: a first signal line formed in a first wiring layer formed on a semiconductor substrate, and disposed in a first direction; first and second shield lines formed in the first wiring layer, disposed on both sides of the first signal line in the first direction, and given a first fixed potential; and a plurality of third shield lines formed in a second wiring layer formed on the semiconductor substrate, disposed with a first wiring width and at a first wiring interval in a second direction almost orthogonal to the first direction in a manner to partially overlap with each of the first signal line and the first and second shield lines, and given the first fixed potential. | 04-03-2014 |
20140095744 | DATA TRANSFER DEVICE AND METHOD - A transfer control circuit stores data in a FIFO memory, outputs data in the FIFO memory in response to a data request signal, and outputs a state signal in accordance with an amount of stored data in the FIFO memory. An output data generating unit outputs image data having a horizontal image size in accordance with a horizontal count value and a horizontal synchronizing signal, and thereafter, outputs blank data. When the state signal indicates that the FIFO memory is in a “EMPTY” or “MODERATE” storage state, a blank control unit outputs a blank addition signal until the FIFO memory changes to a “FULL” storage state. | 04-03-2014 |
20140092638 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An AlGaN/GaN.HEMT includes: a compound semiconductor layered structure; and an interlayer insulating film that covers a surface of the compound semiconductor layered structure, the interlayer insulating film including a first insulating film and a second insulating film that is formed on the first insulating film to fill irregularities on a surface of the first insulating film and has a flat surface. | 04-03-2014 |
20140092637 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film. | 04-03-2014 |
20140092636 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate electrode is formed above a compound semiconductor stacked structure, and the gate electrode includes a stack of a TaN:Al layer in which Al is solid-dissolved in TaN, a TaAlN layer made of a compound of TaN and Al, and an Al layer. | 04-03-2014 |
20140092635 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An AlGaN/GaN HEMT includes: a compound semiconductor layer; a source electrode and a drain electrode formed on an upper side of the compound semiconductor layer; and an Al—Si—N layer being a high-resistance layer disposed in a lower portion of at least one of the source electrode and the drain electrode and higher in an electric resistance value than the source electrode and the drain electrode. | 04-03-2014 |
20140092509 | PROTECTION CIRCUIT, INTERFACE CIRCUIT, AND COMMUNICATION SYSTEM - A protection circuit includes a control circuit coupled to a first power-supply wire applied with a first power-supply voltage. The control circuit generates a control voltage in accordance with the first power-supply voltage and an input voltage. A voltage limitation circuit is coupled between a first node applied with the input voltage and a second power-supply wire applied with a second power-supply voltage. The voltage limitation circuit includes a variable resistance unit having a resistance value that changes according to the control voltage. When the first power-supply voltage is not supplied to the protection circuit and the input voltage is larger than a first voltage, the control circuit generates the control voltage such that the resistance value of the variable resistance unit is smaller than that in a case where the input voltage is equal to or less than the first voltage. | 04-03-2014 |
20140092294 | FOCUS EVALUATION VALUE GENERATION APPARATUS, FOCUS EVALUATION VALUE GENERATION METHOD, AND COMPUTER-READABLE MEDIUM STORING FOCUS EVALUATION VALUE GENERATION PROGRAM - A focus evaluation value generation apparatus includes a low frequency image data generation unit configured to generate low frequency image data, a thinned image generation unit configured to generate thinned input image data and thinned low frequency image data, and a focus evaluation value generation unit configured to generate the focus evaluation value based on the thinned input image data and the thinned low frequency image data. | 04-03-2014 |
20140092273 | DEVICE AND METHOD FOR PROCESSING IMAGE, AND IMAGING DEVICE - A clock signal generator that generates a second clock signal and clock information from a transfer first clock signal and based on a thinning rate, the number of horizontal pre-blank data pieces, the number of effective horizontal pixels, and the number of horizontal post-blank data pieces stored in a register. A thinning processor retrieves image data in accordance with the first clock signal and a horizontal synchronization signal. The thinning processor performs a thinning process on the image data to generate thinned image data and stores the thinned image data in a memory. A read controller sequentially reads the thinned image data from the memory in accordance with the second clock signal having a frequency lower than the first clock signal. | 04-03-2014 |
20140091430 | SEMICONDUCTOR DEVICE INCLUDING OPERATIVE CAPACITORS AND DUMMY CAPACITORS - The semiconductor device according to the present invention comprises a plurality of actually operative capacitors formed, arranged in an actually operative capacitor part over a semiconductor substrate and each including a lower electrode, a ferroelectric film and an upper electrode; a plurality of dummy capacitors formed, arranged in a dummy capacitor part provided outside of the actually operative capacitor part over the semiconductor substrate and each including the lower electrode, the ferroelectric film and the upper electrode; a plurality of interconnections respectively formed on said plurality of the actually operative capacitors and respectively connected to the upper electrodes of said plurality of the actually operative capacitors; and the interconnections respectively formed on said plurality of the dummy capacitors. | 04-03-2014 |
20140091397 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THEREOF - It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different I | 04-03-2014 |
20140091365 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons. | 04-03-2014 |
20140091320 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a third semiconductor layer and a fourth semiconductor layer formed on the second semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode contacting and formed on the fourth semiconductor layer, wherein the third semiconductor layer is formed of a semiconductor material for attaining p-type on an area just under the gate electrode, and a concentration of silicon in the fourth semiconductor layer is higher than that in the second semiconductor layer. | 04-03-2014 |
20140091319 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer. | 04-03-2014 |
20140089681 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 03-27-2014 |
20140089680 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 03-27-2014 |
20140089676 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 03-27-2014 |
20140089570 | SEMICONDUCTOR MEMORY - A memory block area in a semiconductor memory includes program segments. Each program segment includes a group of memory cells arranged at positions where word lines and bit lines intersect and connected to a common source line. The word lines are shared by the program segments. At program operation time source line switches are used for supplying first voltage to a source line in a program segment, of the program segments, including a memory cell to be programmed and supplying second voltage to a source line in a program segment, of the program segments, not including the memory cell to be programmed. | 03-27-2014 |
20140087740 | WIRELESS STATION, SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION SYSTEM, AND A METHOD FOR CONTROLLING THE SAME - A wireless station includes a first wireless communication circuit, a second wireless communication circuit, and a control circuit. The first wireless communication circuit communicates by a first wireless communication system in a first cell which includes a first service area, and the second wireless communication circuit communicates by a second wireless communication system in a second cell which includes a second service area narrower than the first service area. The control circuit switches a communication system between the first wireless communication system and the second wireless communication system to control communication. When switching the communication system between the first wireless communication system and the second wireless communication system, the control circuit controls the first wireless communication circuit and the second wireless communication circuit to set a communication system which is used before the switching to an idle. | 03-27-2014 |
20140085981 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block as a code storage memory area which has a large memory capacity and in which the number of bits to be written at once is large, and a memory block as a work memory area which has a small memory capacity and in which the number of bits to be written at once is small, in which in writing to the code storage memory area a first voltage is supplied to a source line of this memory block, and in writing to the work memory area a second voltage higher than the first voltage is supplied to a source line of this memory block. | 03-27-2014 |
20140085960 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC DEVICE - A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines | 03-27-2014 |
20140084966 | DRIVER CIRCUIT OF SCHOTTKY TRANSISTOR - A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal. | 03-27-2014 |
20140084439 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, a plate-like member that is fixed on the semiconductor chip and has a thermal expansion coefficient different from that of the substrate, and a first adhesive that is provided between the substrate and the plate-like member, the first adhesive being connected to the plate-like member and separated from the substrate, or being separated from the plate-like member and connected to the substrate. | 03-27-2014 |
20140084345 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor stacked structure; a source electrode and a drain electrode formed separately from each other above the compound semiconductor stacked structure; a gate electrode formed between the source electrode and the drain electrode above the compound semiconductor stacked structure; and a passivation film formed above the compound semiconductor stacked structure and made of an insulating material containing Al, in which the passivation film is in a non-contact state with the compound semiconductor stacked structure under the source electrode and the drain electrode. | 03-27-2014 |
20140082624 | EXECUTION CONTROL METHOD AND MULTI-PROCESSOR SYSTEM - An execution control method is executed by a first processor of a multi-processor system controlled by plural operating systems (OSs). The execution control method includes determining by referring to first information that is stored in a storage unit and identifies a synchronization process for threads executed by OSs that are different from one another and among the OSs, whether a synchronization process for which an execution request is issued by a thread that is executed by a first OS that is among the OSs and controls the first processor, is the synchronization process for threads executed by OSs that are different from one another; and upon determining so, causing the first OS to execute the synchronization process for which the execution request is issued, using a storage area accessible by the first OS and specific to the first processor. | 03-20-2014 |
20140082371 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 03-20-2014 |
20140078850 | SEMICONDUCTOR DEVICE AND MEMORY CONTROL METHOD - An access detection section detects access to an access object circuit and outputs a signal which restricts switching the access object circuit from a first operation state to a second operation state (low power consumption operation state) in which power consumption is lower than power consumption in the first operation state (normal operation state) until no-access period which lasts from last access to next access reaches a first period. An operation control section controls operation of the access object circuit according to the output of the access detection section. | 03-20-2014 |
20140077392 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device has insulating films | 03-20-2014 |
20140071124 | IMAGE PROCESSING APPARATUS - An image processing apparatus has a texture mapping unit configured to obtain pixel data including first and second texture coordinates, and generate texel data corresponding to the first and second texture coordinates within a textured image having a gradation pattern based on a non-linear surface. A function of the non-linear surface is defined by a product of first and Bezier curve functions. The texture mapping unit includes first/second Bezier curve function calculation unit configured to calculate the first/second Bezier curve function by obtaining the first/second texture coordinate and control values of the first/second Bezier curve function; a multiplier configured to multiply respective outputs of the first and second Bezier curve function calculation units; and a blending processing unit configured to generate the texel data by blending a plurality of color data corresponding to the gradation pattern using a is multiplication value of the multiplier as a blending ratio. | 03-13-2014 |
20140068193 | SEMICONDUCTOR DEVICE AND MEMORY TEST METHOD - An address range of an L2 cache is divided into sets of a predetermined number of ways. A RAM-BIST pattern generating unit generates a memory address corresponding to a way, a test pattern, and an expected value with respect to the test pattern. The L2 cache and an XOR circuit write the test pattern to a memory address in accordance with the test pattern, read data from the memory address to which the test pattern is written, and compares the read data with the expected value. A decode unit generates a selection signal for each way of the L2 cache by using a memory address. A determination latch stores, by using a selection signal and in a way corresponding to each memory address, a comparison result with respect to the memory address, a scan-out being performed on the comparison result stored in each of the ways in a predetermined order. | 03-06-2014 |
20140061887 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor chips to be mutually bonded via a bonding resin; a sealing resin to seal the plurality of semiconductor chips; and an anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin. | 03-06-2014 |
20140059317 | DATA TRANSFER DEVICE - A data transfer device includes a FIFO memory and a control unit which obtains a data amount of the FIFO memory to control the FIFO memory and outputs a selection signal corresponding to the obtained data amount of the FIFO memory. An output data generation unit generates output data including either one of the second output data and an interpolation data selected based on the selection signal, and a first output data stored in a frame memory. | 02-27-2014 |
20140057421 | SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate. | 02-27-2014 |
20140056057 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes word lines, bit line pairs intersecting the word lines, and memory cells arranged where the word lines and the bit line pairs intersect. A word line driver arranged in correspondence with one of the word lines outputs a first voltage or a second voltage. A potential detection circuit is arranged in correspondence with at least one bit line pair to detect the potential at the bit line pair and generate a detection signal. A word line voltage adjustment circuit changes the output voltage of the word line driver from the first voltage to the second voltage in accordance with the detection signal from the potential detection circuit. A sense amplifier amplifies a potential difference of a selected one of the bit line pairs for access. | 02-27-2014 |
20140055218 | TUNABLE WIDEBAND DISTRIBUTION CIRCUIT - A tunable wideband distribution circuit for transmitting a wireless signal over a transmission line is disclosed. The tunable wideband distribution circuit may include a programmable gain buffer, wherein the gain of the programmable gain buffer is based at least in part on a frequency of the wireless signal. The tunable wideband distribution circuit may also include a tuning element configured to modify an effective impedance of the transmission line based at least on the frequency of the wireless signal, wherein the tuning element is electrically coupled to the transmission line. | 02-27-2014 |
20140051222 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, patterning the first insulating film to form a first and a second opening, forming a first sidewall film on side walls of the first and the second openings, etching the semiconductor substrate with the first insulating film and the first sidewall film as a mask to dig down the first opening and the second opening, removing the first sidewall film to form a first offset portion in the first opening and a second offset portion in the second opening, the first and the second offset portion including a part of a surface of the semiconductor substrate, and etching a bottom of the first opening with the first insulating film as a mask. | 02-20-2014 |
20140048858 | SEMICONDUCTOR DEVICE - A semiconductor device including a silicon substrate including a first region and a second region; a gate electrode above the first region and the second region; an insulation film extending from the gate electrode to the second region to cover part of the gate electrode and part of the second region; a source region and a drain region formed in the silicon substrate, silicide formed on the source region, on the drain region, and on the gate electrode; an interlayer insulation film formed above the gate electrode and the insulation film; a first electrically conductive via formed in the interlayer insulation film, a second electrically conductive via formed in the interlayer insulation, and a third electrically conductive via formed in the interlayer insulation and electrically connecting to the gate electrode; and at least one electrically conductive member formed on the insulation film in the interlayer insulation film. | 02-20-2014 |
20140042613 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation film, the pad including a trace; a first passivation film formed on the insulation film, located adjacent the pad, and separated from the pad; and a second passivation film formed on the first passivation film and the pad, the second passivation film covering the trace, and the second passivation film including an opening which exposes a part of the pad. | 02-13-2014 |
20140037902 | SUBSTRATE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - With TiN being a base material, TiN fine particles are deposited on a silicone substrate by, for example, a laser ablation method so that diameters of the TiN fine particles are about 3 nm, and thereafter, Co fine particles are deposited on the silicon substrate on which the TiN fine particles are deposited, by, for example, the laser ablation method so that sizes of the Co fine particles are equal to or smaller than sizes of the fine particles of the TiN fine particles, here about 1 nm in diameter. | 02-06-2014 |
20140030824 | SEMICONDUCTOR DEVICE HAVING CAPACITOR WITH CAPACITOR FILM HELD BETWEEN LOWER ELECTRODE AND UPPER ELECTRODE - A ferroelectric memory is constituted to comprise a capacitor being formed above a semiconductor substrate ( | 01-30-2014 |
20140027920 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis. | 01-30-2014 |
20140024224 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate. | 01-23-2014 |
20140021546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a source region of the second conductivity type formed in the second region, a drain region of the second conductivity type formed in the first region, a first junction part including a part of a border between the first region and the second region, which is on the side of the drain region, a second junction part including a part of the border between the first region and the second region, which is at a location different from the first junction part, a gate electrode formed above the first junction, and a conductor pattern formed above the second junction part and being electrically independent from the gate electrode. | 01-23-2014 |
20140021513 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer. | 01-23-2014 |
20140017819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor is formed above a semiconductor substrate ( | 01-16-2014 |
20140015112 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam. | 01-16-2014 |
20140008735 | SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A disclosed semiconductor device includes a semiconductor substrate including a first area, a gate electrode formed over the first area of the semiconductor substrate, a first active region formed in the first area of the semiconductor substrate at a lateral side of the gate electrode, a first silicide layer formed at least on a sidewall surface of the gate electrode in the first area, the first silicide layer is electrically connected to the first active region. | 01-09-2014 |
20140004711 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140004673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 01-02-2014 |
20130343141 | SEMICONDUCTOR MEMORY DEVICE AND ERASURE VERIFICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected; a reference cell; and a sense amplifier including a first input terminal to which selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected, the dummy bit line of one memory block of the plurality of memory blocks different from another memory block of the plurality of memory blocks including the selected memory cell being to be electrically connected to the second input terminal of the sense amplifier. | 12-26-2013 |
20130332761 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 12-12-2013 |
20130331040 | System and Method for Correcting Integral Nonlinearity in an Oscillator System - A method may include measuring a frequency difference between an actual frequency and an expected frequency associated with a frequency control calibration signal value for each of a plurality of frequency control calibration signal values during a calibration phase. The method may additionally include generating integral non-linearity compensation values based on the frequency differences measured The method may further include generating the applied frequency control signal based on a frequency control calibration signal value received by the digital-to-analog converter during the calibration phase. The method may also include generating a compensated frequency control signal value based on a frequency control signal value received by the integral non-linearity compensation module and an integral non-linearity compensation value associated with the frequency control signal value during an operation phase of the wireless communication element. | 12-12-2013 |
20130330912 | SILICON OXYCARBIDE, GROWTH METHOD OF SILICON OXYCARBIDE LAYER, SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O | 12-12-2013 |
20130326248 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 12-05-2013 |
20130326247 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 12-05-2013 |
20130326246 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 12-05-2013 |
20130322198 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 12-05-2013 |
20130321189 | AD CONVERTER CIRCUIT AND AD CONVERSION METHOD - A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit. | 12-05-2013 |
20130320508 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate. | 12-05-2013 |
20130318293 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 11-28-2013 |
20130315020 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 11-28-2013 |
20130315012 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 11-28-2013 |
20130307504 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit has N sets of voltage step-up circuits configured to start a voltage step-up operation for increasing an absolute value of an output voltage and configured to stop the voltage step-up operation when the output voltage reaches a step-up voltage that is independently set for each voltage step-up circuit; and a control circuit configured to control such that the N sets of voltage step-up circuits operate in accordance with order of priority while limiting a maximum number of voltage step-up circuits that simultaneously operate, out of the N sets of voltage step-up circuits, to a plural number lower than the N sets. | 11-21-2013 |
20130301363 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - Upon programming a semiconductor memory device including a first and a second n-wells, a first and a second p-channel memory transistors respectively formed in the first and the second n-wells, and a bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel memory transistor, a first voltage is applied to the first bit line, a second voltage is applied to the first n-well, and a third voltage lower than the second voltage is applied to the second n-well. | 11-14-2013 |
20130300514 | Transmission Line Shielding - A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile. | 11-14-2013 |
20130292779 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION PROCESS - A semiconductor device includes a first p-channel FET, the first p-channel FET includes: a first fin-type semiconductor region; a first gate electrode crossing the first fin-type semiconductor region and defining a first p-channel region at an intersection of the first fin-type semiconductor region and the first gate electrode; p-type first source/drain regions, each formed on either side of the first gate electrode in the first fin-type semiconductor region; and first and second compressive stress generating regions formed by oxidizing regions located outside the p-type first source/drain regions in the first fin-type semiconductor region. | 11-07-2013 |