EVERSPIN TECHNOLOGIES, INC. Patent applications |
Patent application number | Title | Published |
20160104835 | PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR - A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane. | 04-14-2016 |
20160084920 | APPARATUS AND METHOD FOR RESET AND STABILIZATION CONTROL OF A MAGNETIC SENSOR - A magnitude and direction of at least one of a reset current and a second stabilization current (that produces a reset field and a second stabilization field, respectively) is determined that, when applied to an array of magnetic sense elements, minimizes the total required stabilization field and reset field during the operation of the magnetic sensor and the measurement of the external field. Therefore, the low field sensor operates optimally (with the highest sensitivity and the lowest power consumption) around the fixed external field operating point. The fixed external field is created by other components in the sensor device housing (such as speaker magnets) which have a high but static field with respect to the low (earth's) magnetic field that describes orientation information. | 03-24-2016 |
20150333251 | STRUCTURES AND METHODS FOR SHIELDING MAGNETICALLY SENSITIVE COMPONENTS - Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements. | 11-19-2015 |
20150316624 | APPARATUS AND METHOD FOR SEQUENTIALLY RESETTING ELEMENTS OF A MAGNETIC SENSOR ARRAY - A semiconductor process and apparatus provide a high-performance magnetic field sensor with three differential sensor configurations which require only two distinct pinning axes, where each differential sensor is formed from a Wheatstone bridge structure with four unshielded magnetic tunnel junction sensor arrays, each of which includes a magnetic field pulse generator for selectively applying a field pulse to stabilize or restore the easy axis magnetization of the sense layers to orient the magnetization in the correct configuration. prior to measurements of small magnetic fields. The field pulse is sequentially applied to groups of the sense layers of the Wheatstone bridge structures, thereby allowing for a higher current pulse or larger sensor array size for maximal signal to noise ratio. | 11-05-2015 |
20150219689 | PROBE CARD AND METHOD FOR TESTING MAGNETIC SENSORS - A probe card and method are provided for testing magnetic sensors at the wafer level. The probe card has one or more probe tips having a first pair of solenoid coils in parallel configuration on first opposed sides of each probe tip to supply a magnetic field in a first (X) direction, a second pair of solenoid coils in parallel configuration on second opposed sides of each probe tip to supply a magnetic field in a second (Y) direction orthogonal to the first direction, and an optional third solenoid coil enclosing or inscribing the first and second pair to supply a magnetic field in a third direction (Z) orthogonal to both the first and second directions. The first pair, second pair, and third coil are each symmetrical with a point on the probe tip array, the point being aligned with and positioned close to a magnetic sensor during test. | 08-06-2015 |
20150200001 | MEMORY DEVICE WITH REDUCED ON-CHIP NOISE - In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device. | 07-16-2015 |
20150192655 | APPARATUS AND METHOD FOR RESETTING A Z-AXIS SENSOR FLUX GUIDE - A method and apparatus eliminate magnetic domain walls in a flux guide by applying, either simultaneously or sequentially, a current pulse along serially positioned reset lines to create a magnetic field along the flux guide, thereby removing the magnetic domain walls. By applying the current pulses in parallel and stepping through pairs of shorter reset lines segments via switches, less voltage is required. | 07-09-2015 |
20150061663 | APPARATUS AND METHOD FOR SEQUENTIALLY RESETTING ELEMENTS OF A MAGNETIC SENSOR ARRAY - A semiconductor process and apparatus provide a high-performance magnetic field sensor with three differential sensor configurations which require only two distinct pinning axes, where each differential sensor is formed from a Wheatstone bridge structure with four unshielded magnetic tunnel junction sensor arrays, each of which includes a magnetic field pulse generator for selectively applying a field pulse to stabilize or restore the easy axis magnetization of the sense layers to orient the magnetization in the correct configuration prior to measurements of small magnetic fields. The field pulse is sequentially applied to groups of the sense layers of the Wheatstone bridge structures, thereby allowing for a higher current pulse or larger sensor array size for maximal signal to noise ratio. | 03-05-2015 |
20150054502 | APPARATUS AND METHOD FOR RESET AND STABILIZATION CONTROL OF A MAGNETIC SENSOR - A magnitude and direction of at least one of a reset current and a second stabilization current (that produces a reset field and a second stabilization field, respectively) is determined that, when applied to an array of magnetic sense elements, minimizes the total required stabilization field and reset field during the operation of the magnetic sensor and the measurement of the external field. Therefore, the low field sensor operates optimally (with the highest sensitivity and the lowest power consumption) around the fixed external field operating point. The fixed external field is created by other components in the sensor device housing (such as speaker magnets) which have a high but static field with respect to the low (earth's) magnetic field that describes orientation information. | 02-26-2015 |
20150023093 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied with each write pulse or a series of write pulses, and may be applied prior to or subsequent to the write pulse. | 01-22-2015 |
20150019806 | MEMORY DEVICE WITH PAGE EMULATION MODE - In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row. | 01-15-2015 |
20140315329 | METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE - A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode. | 10-23-2014 |
20140287536 | METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE WITH VIA INTEGRATION - A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer. | 09-25-2014 |
20140220707 | METHOD FOR MANUFACTURING AND MAGNETIC DEVICES HAVING DOUBLE TUNNEL BARRIERS - A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer. | 08-07-2014 |
20140217528 | SPIN-TORQUE MAGNETORESISTIVE MEMORY ELEMENT AND METHOD OF FABRICATING SAME - A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier. | 08-07-2014 |
20140212993 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber. | 07-31-2014 |
20140190933 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask. | 07-10-2014 |
20140159179 | TWO-AXIS MAGNETIC FIELD SENSOR HAVING REDUCED COMPENSATION ANGLE FOR ZERO OFFSET - A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer. | 06-12-2014 |
20140138346 | PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR - A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane. | 05-22-2014 |
20140104963 | MEMORY DEVICE WITH REDUCED ON-CHIP NOISE - In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device. | 04-17-2014 |
20140104937 | MEMORY DEVICE WITH TIMING OVERLAP MODE - In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes. | 04-17-2014 |
20130308374 | CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES - A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array. | 11-21-2013 |
20130301346 | SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin. | 11-14-2013 |
20130300402 | METHOD AND STRUCTURE FOR TESTING AND CALIBRATING THREE AXIS MAGNETIC FIELD SENSING DEVICES - A structure and method are provided for self-test of a Z axis sensor. Two self-test current lines are symmetrically positioned adjacent, but equidistant from, each sense element. The vertical component of the magnetic field created from a current in the self-test lines is additive in a flux guide positioned adjacent, and orthogonal to, the sense element; however, the components of the magnetic fields in the plane of the sense element created by each of the two self-test current line pairs cancel one another at the sense element center, resulting in only the Z axis magnetic field being sensed during the self-test. | 11-14-2013 |
20130272060 | SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column. | 10-17-2013 |
20130221949 | APPARATUS AND METHOD FOR RESETTING A Z-AXIS SENSOR FLUX GUIDE - A method and apparatus eliminate magnetic domain walls in a flux guide by applying, either simultaneously or sequentially, a current pulse along serially positioned reset lines to create a magnetic field along the flux guide, thereby removing the magnetic domain walls. By applying the current pulses in parallel and stepping through pairs of shorter reset lines segments via switches, less voltage is required. | 08-29-2013 |
20130155763 | CIRCUIT AND METHOD FOR SPIN-TORQUE MRAM BIT LINE AND SOURCE LINE VOLTAGE REGULATION - Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write | 06-20-2013 |
20130155762 | RANDOM ACCESS MEMORY ARCHITECTURE FOR READING BIT STATES - An architecture and method includes providing an oscillatory signal through each magnetic tunnel junction (MTJ), or in a line adjacent each MTJ, in a magnetoresistive random access memory array. A rectified signal appearing across each MTJ is measured and compared to a reference signal for determining the state of the MTJ. | 06-20-2013 |
20130155760 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method for determining an optimized write pattern for low write error rate operation of a spin torque magnetic random access memory. The method provides a way to optimize the write error rate without affecting the memory speed. The method comprises one or more write pulses. The pulses may be independent in amplitude, duration and shape. Various exemplary embodiments adjust the write pattern based on the memory operating conditions, for example, operating temperature. | 06-20-2013 |
20130128658 | WRITE DRIVER CIRCUIT AND METHOD FOR WRITING TO A SPIN-TORQUE MRAM - A write driver for writing to a spin-torque magnetoresistive random access memory (ST-MRAM) minimizes sub-threshold leakage of the unselected (off) word line select transistors in the selected column. An effective metal resistance in the bit line and/or source line is reduced and power supply noise immunity is increased. Write driver bias signals are isolated from global bias signals, and a first voltage is applied at one end of a bit line using one of a first NMOS-follower circuit or a first PMOS-follower circuit. A second voltage is applied at opposite ends of a source line using, respectively, second and third PMOS-follower circuits, or second and third NMOS-follower circuits. | 05-23-2013 |
20130128657 | HYBRID READ SCHEME FOR SPIN TORQUE MRAM - A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation. | 05-23-2013 |
20130128650 | DATA-MASKED ANALOG AND DIGITAL READ FOR RESISTIVE MEMORIES - An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier. | 05-23-2013 |
20130082339 | METHOD FOR MANUFACTURING AND MAGNETIC DEVICES HAVING DOUBLE TUNNEL BARRIERS - A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer. | 04-04-2013 |
20130009659 | PROBE CARD AND METHOD FOR TESTING MAGNETIC SENSORS - A probe card and method are provided for testing magnetic sensors at the wafer level. The probe card has one or more probe tips having a first pair of solenoid coils in parallel configuration on first opposed sides of each probe tip to supply a magnetic field in a first (X) direction, a second pair of solenoid coils in parallel configuration on second opposed sides of each probe tip to supply a magnetic field in a second (Y) direction orthogonal to the first direction, and an optional third solenoid coil enclosing or inscribing the first and second pair to supply a magnetic field in a third direction (Z) orthogonal to both the first and second directions. The first pair, second pair, and third coil are each symmetrical with a point on the probe tip array, the point being aligned with and positioned close to a magnetic sensor during test. | 01-10-2013 |
20120313191 | SPIN-TORQUE MAGNETORESISTIVE MEMORY ELEMENT AND METHOD OF FABRICATING SAME - A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic, layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier. | 12-13-2012 |
20120311396 | MRAM FIELD DISTURB DETECTION AND RECOVERY - A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error. | 12-06-2012 |
20120212217 | APPARATUS AND METHOD FOR SEQUENTIALLY RESETTING ELEMENTS OF A MAGNETIC SENSOR ARRAY - A semiconductor process and apparatus provide a high-performance magnetic field sensor with three differential sensor configurations which require only two distinct pinning axes, where each differential sensor is formed from a Wheatstone bridge structure with four unshielded magnetic tunnel junction sensor arrays, each of which includes a magnetic field pulse generator for selectively applying a field pulse to stabilize or restore the easy axis magnetization of the sense layers to orient the magnetization in the correct configuration. prior to measurements of small magnetic fields. The field pulse is sequentially applied to groups of the sense layers of the Wheatstone bridge structures, thereby allowing for a higher current pulse or larger sensor array size for maximal signal to noise ratio. | 08-23-2012 |
20120198313 | METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE - A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort. | 08-02-2012 |
20120195112 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read. | 08-02-2012 |
20120193736 | FABRICATION PROCESS AND LAYOUT FOR MAGNETIC SENSOR ARRAYS - A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout. The X and Y pitch of the sense elements are arranged such that the line segment that stabilizes, for example, the right side of one sense element; also stabilizes the left side of the adjacent sense element. | 08-02-2012 |
20120163061 | MEMORY ARRAY HAVING LOCAL SOURCE LINES - A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality of M bit lines; first and second local source lines and first and second word lines, each coupled to each of the plurality of memory elements; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in the selected row group coupled to one of the plurality of M bit lines by applying current of magnitude less than N to two or more of the remaining M-1 bit lines. | 06-28-2012 |
20120156806 | MAGNETIC RANDOM ACCESS MEMORY INTEGRATION HAVING IMPROVED SCALING - A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F | 06-21-2012 |
20120155160 | MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES - A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM). | 06-21-2012 |
20120122247 | ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer. | 05-17-2012 |
20120081950 | STRUCTURES AND METHODS FOR A FIELD-RESET SPIN-TORQUE MRAM - An apparatus and method of programming a spin-torque magnetoresistive memory array includes a conductive reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state having magnetization perpendicular to the film plane of the magnetoresistive bits by generating a magnetic field when an electrical current flows therethrough. The conductive reset line is positioned such that the magnetic field is applied with a predominant component perpendicular to the film plane when an electrical current of predetermined magnitude, duration, and direction flows through the first conductive reset line. Another conductive reset line may be positioned wherein the magnetic field is created between the two conductive reset lines. A permeable ferromagnetic material may be positioned around a portion of the conductive reset line or lines to focus the magnetic field in the desired direction by positioning edges of permeable ferromagnetic material on opposed sides of the film plane. A spin torque transfer current is applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. | 04-05-2012 |
20120015099 | STRUCTURE AND METHOD FOR FABRICATING A MAGNETIC THIN FILM MEMORY HAVING A HIGH FIELD ANISOTROPY - A method for depositing uniform and smooth ferromagnetic thin films with high deposition-induced microstructural anisotropy includes a magnetic material deposited in two or more static oblique deposition steps from opposed directions to form a free layer having a high kink Hk, a high energy barrier to thermal reversal, a low critical current in spin-torque switching embodiments, and improved resistance to diffusion of material from adjacent layers in the device. Nonmagnetic layers deposited by the static oblique deposition technique may be used as seed layers for a ferromagnetic free layer or to generate other types of anisotropy determined by the deposition-induced microstructural anisotropy. Additional magnetic or non-magnetic layers may be deposited by conventional methods adjacent to oblique layer to provide magnetic coupling control, reduction of surface roughness, and barriers to diffusion from additional adjacent layers in the device. | 01-19-2012 |
20110292714 | STRUCTURES AND METHODS FOR A FIELD-RESET SPIN-TORQUE MRAM - An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied. | 12-01-2011 |
20110244599 | PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR - A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane. | 10-06-2011 |
20110169488 | METHOD AND STRUCTURE FOR TESTING AND CALIBRATING MAGNETIC FIELD SENSING DEVICE - A method of sensing a magnetic field including at least one magnetoresistive sensing element ( | 07-14-2011 |
20110147867 | METHOD OF VERTICALLY MOUNTING AN INTEGRATED CIRCUIT - A method of mounting a first integrated circuit ( | 06-23-2011 |
20110121826 | Two-Axis Magnetic Field Sensor with Multiple Pinning Directions - A fabrication process and apparatus provide a high-performance magnetic field sensor ( | 05-26-2011 |
20110074406 | THREE AXIS MAGNETIC FIELD SENSOR - Three bridge circuits ( | 03-31-2011 |
20110062538 | MAGNETIC ELEMENT HAVING REDUCED CURRENT DENSITY - A memory device includes a fixed magnetic layer, a tunnel barrier layer over the fixed magnetic layer, and a free magnetic structure formed over the tunnel barrier layer, wherein the free magnetic structure has layers or sub-layers that are weakly magnetically coupled. Thus, a low programming voltage can be used to avoid tunnel barrier breakdown, and a small pass transistor can be used to save die real estate. | 03-17-2011 |
20100277971 | METHOD FOR REDUCING CURRENT DENSITY IN A MAGNETOELECTRONIC DEVICE - A method for reducing spin-torque current density needed to switch a magnetoelectronic device ( | 11-04-2010 |
20100276389 | TWO-AXIS MAGNETIC FIELD SENSOR WITH SUBSTANTIALLY ORTHOGONAL PINNING DIRECTIONS - A fabrication process and apparatus provide a high-performance magnetic field sensor ( | 11-04-2010 |
20100213933 | MAGNETIC FIELD SENSING DEVICE - A magnetic field sensing device for determining the strength of a magnetic field, includes four magnetic tunnel junction elements or element arrays ( | 08-26-2010 |
20100197043 | STRUCTURE AND METHOD FOR FABRICATING CLADDED CONDUCTIVE LINES IN MAGNETIC MEMORIES - A method of forming a magnetoelectronic device includes forming a dielectric material ( | 08-05-2010 |
20100165710 | Random access memory architecture including midpoint reference - A random access memory architecture includes a first series connected pair of memory elements ( | 07-01-2010 |
20100148167 | MAGNETIC TUNNEL JUNCTION STACK - A magnetic tunnel junction ( | 06-17-2010 |