Applied Micro Circuits Corporation Patent applications |
Patent application number | Title | Published |
20160020978 | SYSTEM AND METHOD FOR MONITORING ENCODED SIGNALS IN A NETWORK - Various aspects provide for non-intrusively monitoring a network system. A multiplexing component is configured to receive a plurality of first encoded signals and generate a plurality of second encoded signals. The plurality of second encoded signals contain a different data rate and a different number of network lanes than the plurality of first encoded signals. A monitoring component is configured to identify a block location for repeating blocks and an alignment marker in each of the plurality of first encoded signals and/or the plurality of second encoded signals. The monitoring component can also be configured to identify one or more defects, identify error information and/or determine one or more skew values associated with the plurality of first encoded signals and/or the plurality of second encoded signals. | 01-21-2016 |
20150326379 | DUPLEX TRANSMISSION OVER REDUCED PAIRS OF TWINAX CABLES - Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds. | 11-12-2015 |
20150326197 | PROGRAMMABLE GAIN AMPLIFIER WITH CONTROLLED GAIN STEPS - Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port | 11-12-2015 |
20150324306 | FLOW PINNING IN A SERVER ON A CHIP - Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams. | 11-12-2015 |
20150324203 | HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A BUFFER ASSOCIATED WITH BRANCH PREDICTION - Various aspects provide for facilitating prediction of instruction pipeline hazards in a processor system. A system comprises a fetch component and an execution component. The fetch component is configured for storing a hazard prediction associated with a group of memory access instructions in a buffer associated with branch prediction. The execution component is configured for executing a memory access instruction associated with the group of memory access instructions as a function of the hazard prediction entry. In an aspect, the hazard prediction entry is configured for predicting whether the group of memory access instructions is associated with an instruction pipeline hazard. | 11-12-2015 |
20150324133 | SYSTEMS AND METHODS FACILITATING MULTI-WORD ATOMIC OPERATION SUPPORT FOR SYSTEM ON CHIP ENVIRONMENTS - Systems and methods that facilitate multi-word atomic operation support for systems on chip are described. One method involves: receiving an instruction associated with a calling process, and determining a first memory width associated with execution of the instruction based on an operator of the instruction and a width of at least one operand of the instruction. The instruction can be associated with an atomic operation. In some embodiments, the instruction contains a message having a first field identifying the operator and a second field identifying the operand. | 11-12-2015 |
20150323956 | GENERATING A TIMEOUT SIGNAL BASED ON A CLOCK COUNTER ASSOCIATED WITH A DATA REQUEST - Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device. | 11-12-2015 |
20150323569 | HIGH FREQUENCY VOLTAGE SUPPLY MONITOR - Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device. | 11-12-2015 |
20150317158 | IMPLEMENTATION OF LOAD ACQUIRE/STORE RELEASE INSTRUCTIONS USING LOAD/STORE OPERATION WITH DMB OPERATION - A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed. | 11-05-2015 |
20150163024 | TIMES-SLICED DESIGN SEGMENTATION - Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and configured to process the data streams in a first fragment-based time-sliced schedule. A time slice in the first fragment-based time-sliced schedule is determined based on a predetermined boundary associated with the data fragment and is allocated to process a data fragment of the data streams. | 06-11-2015 |
20150160945 | ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR SYSTEM BASED ON PREDICTION OF AN INSTRUCTION PIPELINE HAZARD - Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard. | 06-11-2015 |
20150150009 | MULTPLE DATASTREAMS PROCESSING BY FRAGMENT-BASED TIMESLICING - Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream. | 05-28-2015 |
20150110233 | JITTER MITIGATING PHASE LOCKED LOOP CIRCUIT - Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero. | 04-23-2015 |
20150106679 | DEFECT PROPAGATION OF MULTIPLE SIGNALS OF VARIOUS RATES WHEN MAPPED INTO A COMBINED SIGNAL - Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective signal during aggregation, by an aggregation component. In another aspect, the maintenance signal can replace the defective signal during de-aggregation | 04-16-2015 |
20150098469 | TCP SEGMENTATION OFFLOAD IN A SERVER ON A CHIP - A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls a coprocessor interface and delivers some metadata about the chunk of data to the interface. The coprocessor segments the chunk of data into a maximum transmission unit size associated with the network interface and increments a sequential number field in the header information of each packet before sending the segments to the network interface. | 04-09-2015 |
20150095610 | MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE - Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester. | 04-02-2015 |
20150078406 | MAPPING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS - Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure. | 03-19-2015 |
20150071311 | REFORMATING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS - Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal. | 03-12-2015 |
20150067381 | DISCRETE TIME COMPENSATION MECHANISMS - Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels. | 03-05-2015 |
20150052286 | RETRIEVAL HASH INDEX - Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient. | 02-19-2015 |
20150049847 | FAST FILTERING FOR A TRANSCEIVER - Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels. | 02-19-2015 |
20150032794 | END-TO-END FLOW CONTROL IN SYSTEM ON CHIP INTERCONNECTS - Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network, the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also provided is a free pool manager that can keep at least some high priority slots available by consuming lower priority slots first. | 01-29-2015 |
20140314192 | METHOD AND APPARATUS FOR SMOOTHING JITTER GENERATED BY BYTE STUFFING - Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte. | 10-23-2014 |
20140307500 | INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL - A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver. | 10-16-2014 |
20140289541 | DYNAMIC POWER CONTROL - Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient. | 09-25-2014 |
20140289467 | CACHE MISS DETECTION FILTER - Systems and methods are provided that facilitate cache miss detection in an electronic device. The system contains a probabilistic filter coupled to the processing device. A probing component determines existence of an entry associated with a request. The probing component can communicate a miss token without the need to query a cache. Accordingly, power consumption can be reduced and electronic devices can be more efficient. | 09-25-2014 |
20140281722 | DEBUGGING PROCESSOR HANG SITUATIONS USING AN EXTERNAL PIN - Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction. | 09-18-2014 |
20140281695 | PROCESSOR HANG DETECTION AND RECOVERY - Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction. | 09-18-2014 |
20140281275 | BROADCAST MESSAGING AND ACKNOWLEDGMENT MESSAGING FOR POWER MANAGEMENT IN A MULTIPROCESSOR SYSTEM - Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor. | 09-18-2014 |
20140266339 | METHOD AND APPARATUS FOR GAPPING - Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider. | 09-18-2014 |
20140266328 | FREQUENCY SYNTHESIS WITH GAPPER - Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal. | 09-18-2014 |
20140237223 | SYSTEM BOOT WITH EXTERNAL MEDIA - Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader. | 08-21-2014 |
20140233588 | LARGE RECEIVE OFFLOAD FUNCTIONALITY FOR A SYSTEM ON CHIP - Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network segments in response to a determination that a gather buffer that stores packet data for the one or more network segments has reached a predetermined size. | 08-21-2014 |
20140215181 | QUEUE REQUEST ORDERING SYSTEMS AND METHODS - The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In one embodiment, the storage component maintains a request without stalling a request in an aliasing condition. | 07-31-2014 |
20140209801 | METHOD FOR USING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE - A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter. | 07-31-2014 |
20140201481 | DOMAIN PROTECTION AND VIRTUALIZATION FOR SATA - Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the system processor and has commands from one or more VMs. | 07-17-2014 |
20140177356 | PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE - Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell. | 06-26-2014 |
20140147945 | METHOD FOR MANUFACTURING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE - A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter. | 05-29-2014 |
20140120787 | MINI SAS HD CONNECTOR - An apparatus including top and bottom portions that when mated form a connector. The top portion includes a top connector portion including a first wall, a second wall opposite the first wall, a first top cap connecting the first and second walls, and wherein the first wall comprises a first concave/convex feature for interlocking. The bottom portion includes a bottom connector portion configured to mate with the top connector portion to form the connector. The bottom connector portion includes a third wall, a fourth wall opposite the third wall, a first bottom connecting the third wall and the fourth wall, and wherein the third wall includes a second concave/convex feature for interlocking with the first concave/convex feature, wherein the second concave/convex feature is oriented opposite the first concave/convex feature. | 05-01-2014 |
20140115886 | METHOD AND SYSTEM FOR MARKING SUBSTRATE AND PLACING COMPONENTS FOR HIGH ACCURACY - A method and system for pre-marking a substrate to provide a visual reference enabling repetitive and accurate component placement on one or more substrates. The method for marking includes determining a first location on a substrate for placing a component relative to a cut outline of the substrate. The method includes placing a fiducial at a second location on the substrate to provide a known dimensional reference to the first location, such that the fiducial and the first location are configured to be in a field-of-view of a component placement machine. | 05-01-2014 |
20140115409 | SELF-TEST DESIGN FOR SERIALIZER / DESERIALIZER TESTING - Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate. | 04-24-2014 |
20140101381 | MANAGING BANKS IN A MEMORY SYSTEM - Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced. | 04-10-2014 |
20140101380 | MANAGING BANKS IN A MEMORY SYSTEM - Systems and methods are provided that facilitate memory storage in a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array writes or retrieves data contained therein based upon the command. The memory controller can monitor multiple banks and manage bank activations. Accordingly, memory access overhead can be reduced and memory devices can be more efficient. | 04-10-2014 |
20140099125 | COLLIMATED BEAM CHANNEL WITH FOUR LENS OPTICAL SURFACES - An optical system and method disclosed include a first lens component and a second lens component within the receive path or the transmit path. The first lens component includes at least two aspheric surfaces that oppose one another and generate a collimated beam channel. The second lens component generates a converging beam and magnifies the converging beam with a magnification factor that is different from a magnification factor in the other path, either the receive path or the transmit path. The receive path and the transmit path include symmetrical lengths and asymmetrical magnification factors. | 04-10-2014 |
20140099124 | HIGH-DENSITY FIBER COUPLING AND EMISSION/DETECTION SYSTEM - An optical system including an array of photonic devices that convert light signals to electrical signals or electrical signals to light signals are coupled together and optically coupled to an array of optic fibers of an information channel. A lens couples optical beams generated to at least one array of photonic devices and the array of optic fibers for an optical communication there-between. The array of photonic devices and the array of optic fibers are respectively arranged in a honeycomb configuration. | 04-10-2014 |
20140093250 | IMAGING SYSTEM FOR PASSIVE ALIGNMENT OF ENGINES - Methods and systems for facilitating alignment of optical systems and optoelectronic systems are disclosed here. The methods and systems include passively detecting images, determining relative positions of components and aligning components. An imaging component can detect images and determine relative positions and repositioning instructions. | 04-03-2014 |
20140082935 | METHOD FOR PASSIVE ALIGNMENT OF OPTICAL COMPONENTS TO A SUBSTRATE - A method for placing components on a substrate, the method comprising determining a reference point of a mechanical holding jig based upon a plurality of mechanical features of the mechanical holding jig and placing the substrate into the jig such that mechanical features on the substrate align with the mechanical features on the mechanical holding jig. A location of the substrate is determined with the reference point of the mechanical holding jig. The method continues by installing a plurality of first components onto the substrate aligned to the mechanical holding jig. The substrate is removed from the mechanical holding jig and a second component is placed onto the substrate to cover the plurality of first components. The second component is placed onto the substrate to align a plurality of references points of the second component to the mechanical features on the substrate. The second component is secured to the substrate. | 03-27-2014 |
20130215949 | DETECTION AND ESTIMATION OF NARROWBAND INTERFERENCE BY MATRIX MULTIPLICATION - One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference. | 08-22-2013 |
20120128049 | Confirmation of Presence of Narrowband Interference By Harmonic Analysis - One or more processing units confirm existence of narrow band interference in a signal by using an estimate f of the frequency, to check for one or more harmonics. In illustrative embodiments, the estimate f is automatically identified as a second harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at either of two frequencies namely (A) frequency f/2 and (B) frequency (M−f)/2 and whichever of these two frequencies is stronger is identified as the fundamental frequency. In several such embodiments, the estimate f is automatically identified as a third harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at any of three frequencies namely (C) frequency f/3 and (D) frequency (M−t)/3 and (E) frequency (M+f)/3. If the predetermined criteria are not met at all five frequencies (A)-(E) then f is identified as the fundamental frequency. | 05-24-2012 |
20120128048 | Detection and Estimation of Narrowband Interference By Matrix Multiplication - One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference. | 05-24-2012 |
20120126903 | Stabilized Digital Quadrature Oscillator - A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively. | 05-24-2012 |
20120014487 | Adaptive Narrowband Interference Prediction Circuit and Method - An input signal that includes narrowband interference is spectrally enhanced by an adaptive circuit that supplies as output signal(s), portion(s) of NBI at one or more frequencies that change adaptively. The output signal(s) are used in one or more tone predictor(s) to generate, based on prior values of the NBI portion, one or more predicted tone signals that are subtracted from a received signal containing the NBI, and the result is used in the normal manner, e.g. decoded. The adaptive circuit and the one or more tone predictor(s), form a feed-forward NBI predictor wherein the received signal is supplied as the input signal of the adaptive circuit. The result of subtraction may be supplied to a slicer that slices the result, yielding a sliced signal which is subtracted from the received signal to generate a signal can be used as the input signal, to implement a feedback NBI predictor. | 01-19-2012 |
20120014416 | Narrowband Interference Cancellation Method and Circuit - A narrowband interference (NBI) canceller is coupled to an A/D converter to receive an input signal and supply an NBI-canceled signal to an error correcting decoder. In the NBI canceller, a first arithmetic unit receives the input signal and a predicted-interference signal, and supplies a difference thereof as the interference-canceled signal. A slicer receives the interference-canceled signal and supplies a decision signal. A second arithmetic unit subtracts the decision signal from the input signal to generate a noise signal. A coarse frequency estimator receives the noise signal and analyzes the frequency spectrum to generate a coarse estimate of a fundamental frequency of the NBI. The coarse estimate is used by an adaptive narrowband interference predictor to generate the predicted-interference signal while adaptively tracking the narrowband interference. Use of the NBI canceller in a transceiver can eliminate link drop caused by operation of wireless devices that generate EMI in a cable. | 01-19-2012 |
20120013398 | Adaptive Spectral Enhancement and Harmonic Separation - A circuit and method perform adaptive spectral enhancement at a frequency ω | 01-19-2012 |
20100244785 | Source Power Limiting Charging System - Methods and systems for charging energy storage devices are disclosed. Often the charging circuit may have different levels of power available to charge the energy storage device depending on the state of other subsystems of the electronic system. The present invention provides a source power limiting charging system. Often the losses of the charging system and losses due to the power requirements of support systems are not well known and/or are variable. Controlling source power to the charging system maximizes the amount of power delivered to the energy storage device for a given value of these losses and avoids power contention with the other elements of the electronic system. Therefore, the power drawn from the power source by a controllable power limiting charging circuit is controlled to be less than a source power limit. | 09-30-2010 |
20100100569 | Method of Accelerating the Shortest Path Problem - The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance. | 04-22-2010 |
20090148161 | 10 GBE LAN SIGNAL MAPPING TO OTU2 SIGNAL - A high-capacity digital communications system and method of transporting 10 GbE LAN packets between user devices over an OTN network that allows the packets to be transported in a manner that is transparent to the destination device(s) on the network. The digital communications system includes an OTN network, and at least one source device and at least one destination device connected to the network via respective 10Gbase-R interfaces. The system transports 10 GbE LAN data packets over the OTN network by performing decoding on the packets to recover the preamble and variable length data contained in each packet, removing the IPG between successive packets in the stream, encapsulating the packets including the respective preambles and data, and mapping the encapsulated packets to the overhead and payload areas of ODUk frames. The packets are then transported over the OTN network from the source device to the destination device. | 06-11-2009 |
20090037661 | Cache mechanism for managing transient data - A system and method are provided for managing transient data in cache memory. The method accepts a segment of data and stores the segment in a cache line. In response to accepting a read-invalidate command for the cache line, the segment is both read from the cache line and the cache line made invalid. If, prior to accepting the read-invalidate command, the segment in the cache line is modified, the modified segment is not stored in a backup storage memory as a result of subsequently accepting the read-invalidate command. In one aspect, the segment is initially identified as transient data, and the read-invalidate command is used in response to identifying the segment as transient data. | 02-05-2009 |
20090037660 | Time-based cache control - A time-based system and method are provided for controlling the management of cache memory. The method accepts a segment of data, and assigns a cache lock-time with a time duration to the segment. If a cache line is available, the segment is stored (in cache). The method protects the segment stored in the cache line from replacement until the expiration of the lock-time. Upon the expiration of the lock-time, the cache line is automatically made available for replacement. An available cache line is located by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. In one aspect, the cache lock-time is assigned to the segment by accessing a list with a plurality of lock-times having a corresponding plurality of time duration, and selecting from the list. In another aspect, the lock-time durations are configurable by the user. | 02-05-2009 |
20080320485 | Logic for Synchronizing Multiple Tasks at Multiple Locations in an Instruction Stream - Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task). | 12-25-2008 |