ANALOG DEVICES GLOBAL Patent applications |
Patent application number | Title | Published |
20160134301 | DELTA-SIGMA MODULATOR HAVING TRANSCONDUCTOR NETWORK FOR DYNAMICALLY TUNING LOOP FILTER COEFFICIENTS - A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance. | 05-12-2016 |
20160126935 | CIRCUIT AND METHOD FOR COMPENSATING FOR EARLY EFFECTS - Early effects are intrinsically present in bipolar junction transistors (BJTs). Described are examples of complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) cells that reduce errors associated with the Early effects that would otherwise be present. | 05-05-2016 |
20160119019 | FULL DUPLEX RADIO - Embodiments of full duplex radios are disclosed herein. For example, a radio may include: a first transmitter, a second transmitter, and a receiver. The first transmitter may be configured to receive an input signal, process the input signal to generate a first transmit signal, and transmit the first transmit signal. The second transmitter may be configured to receive the input signal, process the input signal to generate a second transmit signal, and couple the second transmit signal into an input path of the receiver. Leakage at the receiver may thus be reduced. Some embodiments of a radio may also include a base band correction circuit and means for reducing transmitter noise that leaks into the receiver. | 04-28-2016 |
20150318841 | METHOD OF IMPROVING NOISE IMMUNITY IN A SIGNAL PROCESSING APPARATUS, AND A SIGNAL PROCESSING APPARATUS HAVING IMPROVED NOISE IMMUNITY - A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period. | 11-05-2015 |
20150188562 | DIGITAL TUNING ENGINE FOR HIGHLY PROGRAMMABLE DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS - An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by decimalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value. In some embodiments, the integrated circuit further includes a scaling module configured to scale the component value based on scaling parameters. | 07-02-2015 |
20150147005 | METHODS AND APPARATUS FOR IMAGE PROCESSING AT PIXEL RATE - Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth. | 05-28-2015 |
20150070200 | System, Method and Recording Medium for Analog to Digital Converter Calibration - A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block. | 03-12-2015 |