3D PLUS Patent applications |
Patent application number | Title | Published |
20140349008 | METHOD FOR PRODUCING RECONSTITUTED WAFERS WITH SUPPORT OF THE CHIPS DURING THEIR ENCAPSULATION - A method for collectively fabricating a reconstituted wafer comprising chips exhibiting connection pads on a front face of the chip, comprises: positioning the chips on an initial adhesive support, front face on the support, vapor deposition at atmospheric pressure and ambient temperature, of an electrically insulating layer on the initial support and the chips, having a mechanical role of holding the chips, transfer of the chips covered with the mineral layer onto a provisional adhesive support, rear face of the chips toward this provisional adhesive support, removal of the initial adhesive support, overlaying the chips onto a support of “chuck” type, front faces of the chips toward this support, removal of the provisional adhesive support, deposition of a resin on the support of “chuck” type to encapsulate the chips, and then polymerization of the resin, removal of the support of “chuck” type, production of an RDL layer active face side. | 11-27-2014 |
20130344654 | Process For Flip-Chip Connection of an Electronic Component - The invention relates to a process for flip-chip connection of an electronic component (D) to a substrate (B), characterized in that it comprises producing at least one interconnect pad (PC) by etching a thick conductive film and bonding it, by means of at least one conductive adhesive, between a receiving pad or area of said electronic component and a receiving pad or area (PAS) of said substrate. | 12-26-2013 |
20130171752 | Method for Collective Fabrication of 3D Electronic Modules Comprising Only Validated PCBs - A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, moulding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules. | 07-04-2013 |
20120094439 | Method for Positioning Chips During the Production of a Reconstituted Wafer - A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer. | 04-19-2012 |
20110312132 | METHOD FOR POSITIONING CHIPS DURING THE PRODUCTION OF A RECONSTITUTED WAFER - A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips. | 12-22-2011 |
20110247210 | PROCESS FOR THE WAFER-SCALE FABRICATION OF ELECTRONIC MODULES FOR SURFACE MOUNTING - A process for the wafer-scale fabrication of CMS electronic modules starts from a wafer with metallized outputs, comprising electronic components molded in resin and, on one side, the external outputs of the electronic components on which a nonoxidizable metal or alloy is deposited, and of a printed circuit provided with oxidizable metal or alloy contact pads. In the process, the wafer is cut in predetermined patterns for obtaining reconfigured molded components that include at least one electronic component; the reconfigured components are assembled on the printed circuit, the metallized external outputs of the reconfigured components being placed opposite the metallized contact pads of the printed circuit; and these external outputs are connected solderlessly to the metallized contact pads of the printed circuit by means of a material based on an electrically conductive adhesive or ink. | 10-13-2011 |
20100276081 | METHOD OF INTERCONNECTING ELECTRONIC WAFERS - The invention relates to a method of interconnecting electronic components of a first wafer (T | 11-04-2010 |
20090260228 | PROCESS FOR THE VERTICAL INTERCONNECTION OF 3D ELECTRONIC MODULES BY VIAS - The present invention relates to a process for the vertical interconnection of 3D electronic modules ( | 10-22-2009 |
20090209052 | PROCESS FOR THE COLLECTIVE FABRICATION OF 3D ELECTRONIC MODULES - The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer ( | 08-20-2009 |
20080316727 | 3D Electronic Module - The invention relates to a 3D electronic module comprising a stack ( | 12-25-2008 |
20080289174 | Process for the Collective Fabrication of 3D Electronic Modules - The invention relates to the collective fabrication of n 3D modules. It comprises a step of fabricating a batch of n wafers I on one and the same plate, this step being repeated K times, then a step of stacking the K plates, a step of forming plated-through holes in the thickness of the stack, these holes being intended for connecting the slices together, and then a step of cutting the stack in order to obtain the n 3D modules. | 11-27-2008 |