Top Inventors for class "Electronic digital logic circuitry" |
Rank | Inventor's name | Country | City/State | Last publication | # of patent apps in this class |
1 | Steven Teig | US | Menlo Park, CA | Mar 24, 2016 / 20160087635 - Operational Time Extension | 50 |
2 | Jason Redgrave | US | Mountain View, CA | Mar 24, 2016 / 20160087635 - Operational Time Extension | 44 |
3 | Herman Schmit | US | Palo Alto, CA | Jan 13, 2022 / 20220014201 - Techniques For Reducing Uneven Aging In Integrated Circuits | 33 |
4 | David Lewis | CA | Toronto | Apr 07, 2016 / 20160098507 - INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT FOR RETIMING | 21 |
5 | Yoshiyuki Kurokawa | JP | Sagamihara | Sep 15, 2022 / 20220293049 - SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, ELECTRONIC DEVICE, AND OPERATION METHOD OF SEMICONDUCTOR DEVICE | 20 |
6 | Martin Voogel | US | Los Altos, CA | Jul 23, 2015 / 20150207504 - CONFIGURATION CONTEXT SWITCHER WITH A LATCH | 19 |
7 | Brian A. Box | US | Seabrook, NH | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 18 |
8 | Benjamin S. Ting | US | Saratoga, CA | Oct 03, 2013 / 20130257478 - PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS | 18 |
9 | Steven Hennick Kelem | US | Los Altos Hills, CA | May 14, 2015 / 20150135191 - Compiler System, Method and Software for a Resilient Integrated Circuit Architecture | 18 |
10 | Lee D. Whetsel | US | Parker, TX | Aug 18, 2022 / 20220260631 - INTERPOSER INSTRUMENTATION METHOD AND APPARATUS | 17 |
11 | Peter M. Pani | US | Mountain View, CA | Oct 03, 2013 / 20130257478 - PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS | 16 |
12 | Stephen L. Wasson | US | Marina, CA | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 15 |
13 | Raminda Udaya Madurawe | US | Sunnyvale, CA | Sep 12, 2019 / 20190279993 - PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS | 15 |
14 | Jun Koyama | JP | Sagamihara | Jul 07, 2022 / 20220216242 - SHIFT REGISTER AND DISPLAY DEVICE AND DRIVING METHOD THEREOF | 13 |
15 | Andrew Caldwell | US | Santa Clara, CA | Mar 24, 2016 / 20160087635 - Operational Time Extension | 12 |
16 | Trevis Chandler | US | San Francisco, CA | Jul 23, 2015 / 20150207504 - CONFIGURATION CONTEXT SWITCHER WITH A LATCH | 12 |
17 | Enno Wein | US | San Jose, CA | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 11 |
18 | Jaime C. Cummins | US | Saratoga, CA | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 11 |
19 | Andy L. Lee | US | San Jose, CA | Nov 05, 2015 / 20150318029 - Integrated Circuits with Asymmetric and Stacked Transistors | 11 |
20 | John L. Watson | US | Edgewood, WA | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 11 |
21 | Charles A. Furciniti | US | Bedford, NH | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 11 |
22 | Robert Plunkett | US | Sunnyvale, CA | Mar 06, 2014 / 20140062526 - Fault Tolerant Integrated Circuit Architecture | 11 |
23 | Theodore Speers | US | San Jose, CA | Feb 13, 2014 / 20140043059 - SECURE DIGEST FOR PLD CONFIGURATION DATA | 10 |
24 | Yasuhiko Takemura | JP | Isehara | Dec 02, 2021 / 20210375876 - SEMICONDUCTOR MEMORY DEVICE | 10 |
25 | Zvi Or-Bach | US | San Jose, CA | Dec 31, 2020 / 20200411594 - 3D SEMICONDUCTOR DEVICE AND STRUCTURE | 10 |
26 | Kiyoshi Kato | JP | Atsugi | Sep 15, 2022 / 20220293159 - SEMICONDUCTOR DEVICE | 10 |
27 | James E. Baumgardner | US | Odenton, MD | Jul 24, 2014 / 20140203838 - QUANTUM PROCESSOR | 10 |
28 | Huy M. Nguyen | US | San Jose, CA | May 19, 2016 / 20160142053 - Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance | 10 |
29 | Brad L. Hutchings | US | Fremont, CA | May 14, 2015 / 20150130508 - Non-Sequentially Configurable IC | 9 |
30 | Brad Hutchings | US | Provo, UT | Aug 20, 2015 / 20150234008 - INTEGRATED CIRCUIT (IC) WITH PRIMARY AND SECONDARY NETWORKS AND DEVICE CONTAINING SUCH AN IC | 9 |
31 | Michael D. Hutton | US | Mountain View, CA | Jan 13, 2022 / 20220014204 - CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS | 9 |
32 | Michael Butts | US | Portland, OR | May 14, 2015 / 20150130508 - Non-Sequentially Configurable IC | 9 |
33 | Robert Norman | US | Pendleton, OR | Dec 23, 2021 / 20210398949 - MEMORY DEVICE INCLUDING MODULAR MEMORY UNITS AND MODULAR CIRCUIT UNITS FOR CONCURRENT MEMORY OPERATIONS | 9 |
34 | Rajit Manohar | US | Ithaca, NY | Sep 17, 2015 / 20150262055 - NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALABLE NEURAL NETWORK | 9 |
35 | David Cashman | CA | Toronto | Oct 03, 2013 / 20130257476 - INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS | 9 |
36 | Takayuki Ikeda | JP | Atsugi | Sep 01, 2022 / 20220278187 - DISPLAY DEVICE | 9 |
37 | Shinichi Yasuda | JP | Tokyo | Apr 21, 2016 / 20160112049 - PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA | 8 |
38 | Sarma Vrudhula | US | Chandler, AZ | Aug 18, 2022 / 20220263508 - THRESHOLD LOGIC GATES USING FLASH TRANSISTORS | 8 |
39 | Quentin P. Herr | US | Ellicott City, MD | Feb 04, 2021 / 20210035004 - SUPERCONDUCTING CLOCK CONDITIONING SYSTEM | 8 |
40 | Gregory Bakker | US | San Jose, CA | Jun 24, 2010 / 20100156457 - PLD PROVIDING SOFT WAKEUP LOGIC | 8 |
41 | Kyung Suk Oh | US | Cupertino, CA | Jul 21, 2022 / 20220230993 - EMBEDDED MULTI-DIE INTERCONNECT BRIDGE WITH IMPROVED POWER DELIVERY | 8 |
42 | Peter J. Klim | US | Austin, TX | Oct 18, 2012 / 20120264241 - TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES | 8 |
43 | Timothy M. Hollis | US | Meridian, ID | Jul 14, 2022 / 20220224570 - TIME-VARIABLE DECISION FEEDBACK EQUALIZATION | 7 |
44 | Min-Su Kim | KR | Hwaseong-Si | Sep 17, 2020 / 20200294988 - INTEGRATED CIRCUIT INCLUDING ASYMMETRIC ENDING CELLS AND SYSTEM-ON-CHIP INCLUDING THE SAME | 7 |
45 | Scott Pitkethly | US | Redwood City, CA | Feb 04, 2016 / 20160036446 - CROSS POINT SWITCH | 7 |
46 | Aaron A. Pesetski | US | Gambrills, MD | Feb 04, 2021 / 20210033683 - MAGNETIC FLUX SOURCE SYSTEM | 7 |
47 | Yoshiaki Saito | JP | Kawasaki-Shi | Mar 17, 2016 / 20160078913 - MAGNETIC MEMORY, SPIN ELEMENT, AND SPIN MOS TRANSISTOR | 7 |
48 | Jia Di | US | Fayetteville, AR | Nov 27, 2014 / 20140347097 - SINGLE COMPONENT SLEEP-CONVENTION LOGIC (SCL) MODULES | 7 |
49 | Hagop Nazarian | US | San Jose, CA | Jan 06, 2022 / 20220005527 - CAPACITANCE MEASUREMENT AND APPARATUS FOR RESISTIVE SWITCHING MEMORY DEVICES | 7 |
50 | Richard Ferrant | FR | Esquibien | Mar 24, 2016 / 20160086652 - MEMORY DEVICE WITH DYNAMICALLY OPERATED REFERENCE CIRCUITS | 7 |
51 | Brad Hutchings | US | Fremont, CA | Jan 28, 2016 / 20160028399 - RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC | 7 |
52 | Bruce B. Pedersen | US | Sunnyvale, CA | Apr 28, 2016 / 20160116536 - METHODS AND APPARATUS FOR AUTOMATIC FAULT DETECTION | 7 |
53 | Hideyuki Sugiyama | JP | Kawasaki-Shi | Mar 17, 2016 / 20160078913 - MAGNETIC MEMORY, SPIN ELEMENT, AND SPIN MOS TRANSISTOR | 7 |
54 | Yutaka Shionoiri | JP | Isehara | Apr 19, 2018 / 20180109267 - SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE | 7 |
55 | Yukihiro Kaneko | JP | Osaka | Sep 24, 2015 / 20150269483 - NEURAL NETWORK CIRCUIT AND LEARNING METHOD FOR NEURAL NETWORK CIRCUIT | 7 |
56 | Huy Nguyen | US | San Jose, CA | May 14, 2015 / 20150130507 - INTEGRATED CIRCUIT WITH CONFIGURABLE ON-DIE TERMINATION | 7 |
57 | Vijay Gadde | US | Cupertino, CA | Jan 06, 2022 / 20220007443 - Negotiation on Bearer Type Configurations | 7 |
58 | Hiroki Fujisawa | JP | Tokyo | Oct 21, 2021 / 20210327856 - STACKED DIE PACKAGE INCLUDING A FIRST DIE COUPLED TO A SUBSTRATE THROUGH DIRECT CHIP ATTACHMENT AND A SECOND DIE COUPLED TO THE SUBSTRATE THROUGH WIRE BONDING, AND RELATED METHODS, DEVICES AND APPARATUSES | 7 |
59 | Alexander Fish | IL | Hadera | Aug 02, 2012 / 20120194219 - LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN | 6 |
60 | Arkadiy Morgenshtein | IL | Kiryat-Motzkin | Aug 02, 2012 / 20120194219 - LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN | 6 |
61 | William F. Lawson | US | Vestal, NY | Apr 14, 2016 / 20160105182 - LEVEL SHIFTING AN I/O SIGNAL INTO MULTIPLE VOLTAGE DOMAINS | 6 |
62 | Seiichi Yoneda | JP | Atsugi | Jun 22, 2017 / 20170179955 - PROGRAMMABLE LOGIC DEVICE | 6 |
63 | Shunpei Yamazaki | JP | Setagaya | Sep 15, 2022 / 20220293798 - SEMICONDUCTOR DEVICE | 6 |
64 | Sang Thanh Nguyen | US | Union City, CA | Nov 06, 2014 / 20140327470 - FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY | 6 |
65 | Mizue Ishikawa | JP | Yokohama-Shi | Mar 17, 2016 / 20160078913 - MAGNETIC MEMORY, SPIN ELEMENT, AND SPIN MOS TRANSISTOR | 6 |
66 | Kyung Suk Oh | US | Campbell, CA | Oct 18, 2012 / 20120265930 - CONTROLLING ON-DIE TERMINATION IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE | 6 |
67 | Teju Khubchandani | US | Milpitas, CA | Jan 28, 2016 / 20160028399 - RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC | 6 |
68 | Richard G. Cliff | US | Los Altos, CA | Jul 31, 2014 / 20140210515 - PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS | 6 |
69 | Anthony Stansfield | GB | Bristol | Nov 08, 2012 / 20120280710 - REUSE OF CONSTANTS BETWEEN ARITHMETIC LOGIC UNITS AND LOOK-UP-TABLES | 6 |
70 | Robert Paul Masleid | US | Monte Sereno, CA | Feb 04, 2016 / 20160036424 - POWER EFFICIENT MULTIPLEXER | 6 |
71 | Tatsuji Nishijima | JP | Hadano | Jun 22, 2017 / 20170179955 - PROGRAMMABLE LOGIC DEVICE | 6 |
72 | Chun-Seok Jeong | KR | Kyoungki-Do | Feb 09, 2012 / 20120033507 - ON DIE THERMAL SENSOR OF SEMICONDUCTOR MEMORY DEVICE | 6 |
73 | Scott Christopher Smith | US | Rogers, AR | Oct 02, 2014 / 20140292371 - MULTI-THRESHOLD DUAL-SPACER DUAL-RAIL DELAY-INSENSITIVE LOGIC (MTD3L) CIRCUIT DESIGN | 6 |
74 | Christopher M. Durham | US | Round Rock, TX | Oct 18, 2012 / 20120264241 - TEST STRUCTURE AND METHODOLOGY FOR THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES | 6 |
75 | Ian P. Shaeffer | US | San Jose, CA | Nov 06, 2014 / 20140329359 - PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM | 6 |
76 | Gajendra Prasad Singh | US | Sunnyvale, CA | Aug 20, 2015 / 20150236695 - MULTI-THRESHOLD FLASH NCL LOGIC CIRCUITRY WITH FLASH RESET | 6 |
77 | Altera Corporation | US | | Sep 18, 2014 / 20140282560 - Mapping Network Applications to a Hybrid Programmable Many-Core Device | 6 |
78 | Munehiro Kozuma | JP | Isehara | Apr 19, 2018 / 20180109835 - SEMICONDUCTOR DEVICE, BROADCASTING SYSTEM, AND ELECTRONIC DEVICE | 6 |
79 | Jonathan W. Greene | US | Palo Alto, CA | Jan 02, 2014 / 20140006887 - On-Chip Probe Circuit for Detecting Faults in an FPGA | 5 |
80 | Jeffrey T. Watt | US | Palo Alto, CA | Nov 05, 2015 / 20150318029 - Integrated Circuits with Asymmetric and Stacked Transistors | 5 |
81 | Takao Marukame | JP | Tokyo | Jun 30, 2016 / 20160191833 - IMAGING ELEMENT, IMAGING DEVICE AND SEMICONDUCTOR DEVICE | 5 |
82 | Robert P. Masleid | US | Monte Sereno, CA | Oct 13, 2016 / 20160301422 - VARIABLE RUN LENGTH ENCODING OF A BIT STREAM | 5 |
83 | Kyung-Hoon Kim | KR | Gyeonggi-Do | Jul 21, 2022 / 20220227173 - Airless Wheel | 5 |
84 | Wen Zhou | CN | Beijing | Dec 23, 2010 / 20100322115 - Reference Signal Sounding for Uplink Pilot Time Slot in Wireless Communication System | 5 |
85 | James D. Warnock | US | Somers, NY | Jun 22, 2017 / 20170177777 - ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS | 5 |
86 | Masashi Tsubuku | JP | Atsugi | Nov 25, 2021 / 20210366944 - TRANSISTOR AND DISPLAY DEVICE | 5 |
87 | Shogo Nakaya | JP | Tokyo | Aug 27, 2015 / 20150244312 - POWER CONVERTER, SOLAR ENERGY DEVICE AND SOLAR ENERGY POWER CONVERSION METHOD | 5 |
88 | Berndt Gammel | DE | Markt-Schwaben | Dec 31, 2015 / 20150381351 - CRYPTOGRAPHIC PROCESSOR, METHOD FOR IMPLEMENTING A CRYPTOGRAPHIC PROCESSOR AND KEY GENERATION CIRCUIT | 5 |
89 | Mark F. Turner | US | Longmont, CO | May 29, 2014 / 20140145775 - OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS | 5 |
90 | Shyh-An Chi | TW | Hsinchu City | Mar 03, 2016 / 20160062928 - INFORMATION PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT | 5 |
91 | Senani Gunaratna | US | Los Gatos, CA | Jan 28, 2016 / 20160028401 - MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES | 5 |
92 | Dirk A. Reese | US | Campbell, CA | Mar 27, 2014 / 20140089677 - METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE DEVICE | 5 |
93 | Satoshi Muraoka | JP | Yokohama | Apr 24, 2014 / 20140112073 - SIGNAL TRANSMISSION SYSTEM AND STORAGE SYSTEM | 5 |
94 | Benedict Lau | US | San Jose, CA | Jun 15, 2017 / 20170169876 - MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS | 5 |
95 | Kosuke Tatsumura | JP | Kawasaki-Shi | May 26, 2016 / 20160149834 - STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD | 5 |
96 | Claude L. Bertin | US | Venice, FL | Jul 13, 2017 / 20170200769 - Resistive Change Element Array Using Vertically Oriented Bit Lines | 5 |
97 | Brent M. Segal | US | Woburn, MA | Jan 10, 2013 / 20130009109 - Spin-Coatable Liquid for Formation of High Purity Nanotube Films | 5 |
98 | Brent Arnold Myers | US | Palm Bay, FL | Sep 14, 2017 / 20170258362 - INGESTIBLE BIO-TELEMETRY COMMUNICATION NETWORK AND ASSOCIATED SYSTEMS | 5 |
99 | Jeng-Jye Shau | US | Palo Alto, CA | May 07, 2015 / 20150123493 - HIGH PERFORMANCE POWER INPUT CIRCUITS USING SYNCHRONIZED MECHANICAL SWITECHES | 5 |
100 | Sinan Kaptanoglu | US | Belmont, CA | Jan 22, 2015 / 20150022236 - Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays | 5 |