DEVICE FOR CONTROLLING A TRANSISTOR

Abstract

The present invention relates to a device for controlling a transistor, comprising: a separating assembly for generating a first voltage, a transformer for obtaining a first and second converted voltage from the first voltage, a rectifier circuit for generating a third voltage from parts of the same sign of the first converted voltage and of the opposite of the second converted voltage, a latch for generating a fourth voltage from the converted voltages, a switching assembly for multiplying the third voltage with a fourth voltage normalized in order to obtain a multiplied voltage, and a shifting circuit for shifting the multiplied amplitude in order to obtain a control voltage.

Description

[0001] The present invention relates to a device for controlling a transistor. The present invention also relates to a converter comprising a transistor and such a device for controlling the transistor. The present invention also relates to an on-board system comprising such a converter.

[0002] In the context of the development of current converters, the use of MOSFET transistors (Metal Oxide Semiconductor Field Effect Transistor) made from silicon carbide makes it possible to improve the performance of such converters. In particular, silicon carbide MOSFET transistors make it possible to obtain converters performing several conversion functions within a same card. Furthermore, such transistors make it possible to obtain a better efficiency relative to silicon MOSFET transistors.

[0003] However, the current control circuits are unsuitable for controlling silicon carbide transistors. In particular, such control circuits generally have a symmetrical control voltage that is capable of damaging silicon carbide transistors.

[0004] There is therefore a need for control device suitable for controlling all types of transistors, in particular silicon carbide transistors, without risk of damaging the transistor controlled by said device.

[0005] To that end, the invention relates to a device for controlling a transistor, the device comprising:

[0006] a separating assembly for generating a first voltage from a DC input voltage, a first control signal and a second control signal, the first control signal and the second control signal each being formed by pulses with no temporal overlap between the pulses of said control signals, the first voltage being formed by:

[0007] pulses of amplitude equal to the input voltage and in phase with the pulses of the first control signal, and

[0008] pulse of amplitude equal to the opposite of the input voltage and in phase with the pulses of the second control signal,

[0009] a transformer connected to the separating assembly, the transformer comprising two secondary windings, the two secondary windings being connected to one another at a midpoint, the first secondary winding being able to convert the first voltage to obtain a first converted voltage, the second secondary winding being able to convert the first voltage to obtain a second converted voltage (V.sub.E), each of the first and second converted voltage being formed by:

[0010] pulses of amplitude with the same sign as the first voltage and in phase with the pulses of the first voltage having an amplitude equal to the input voltage, and

[0011] pulses of amplitude with the opposite sign from the first voltage and in phase with the pulses of the first voltage having an amplitude equal to the opposite of the input voltage.

[0012] a rectifier circuit able to extract the parts of the same sign from the first converted voltage and of opposite sign from the second converted voltage and to generate a third voltage from the extracted parts of the same sign,

[0013] a latch able to generate a fourth voltage from the converted voltages, the fourth voltage having a high state and a low state, the high state being triggered as a function of the sign of the amplitude of the first converted voltage, the low state being triggered as a function of the sign of the amplitude of the opposite of the second converted voltage,

[0014] a switching assembly able to multiply the third voltage by the normalized state of the fourth voltage to obtain a multiplied voltage, the multiplied voltage having two states corresponding to the states of the fourth voltage, one of the states having a value equal to the third voltage, the other state having a nil value,

[0015] a shifting circuit able to shift the amplitude of the multiplied voltage to obtain a control voltage of the transistor, the control voltage having:

[0016] a peak-to-peak amplitude equal to the third voltage,

[0017] a high state corresponding to the high state of the fourth voltage, and

[0018] a low state corresponding to the low state of the fourth voltage and in which the sign of the control voltage is opposite the sign of the high state of the control voltage.

[0019] According to specific embodiments, the control device comprises one or more of the following features, considered alone or according to any technically possible combinations:

[0020] each of the rectifier circuit and the latch is directly connected to the transformer;

[0021] each of the first secondary winding and the second secondary winding is able to convert the first voltage by multiplying it by a same multiplication coefficient;

[0022] the first winding extends between a first terminal and the midpoint and the second winding extends between a second terminal and the midpoint, the rectifier circuit being connected to the midpoint and each of the first terminal and the second terminal, the latch being connected to the first terminal and the second terminal;

[0023] the rectifier circuit comprises:

[0024] a rectifier able to rectify the first converted voltage and the opposite of the second converted voltage to obtain a rectified voltage, the rectifier comprising a first diode and a second diode, the first diode being able to rectify the first converted voltage, the second diode being able to rectify the opposite of the second converted voltage, and

[0025] a capacitor able to charge itself to obtain the third voltage.

[0026] the high state of the fourth voltage is triggered during rising edges of the positive pulses of the converted first voltage, the low state of the fourth voltage being triggered during rising edges of the positive pulses of the opposite of the converted second voltage;

[0027] the multiplied voltage has two states, the shifting circuit comprising a capacitor and a Zener diode; the Zener diode being able, in one of the states of the multiplied voltage, to charge the capacitor to a fifth voltage equal to the third voltage decreased by the voltage of the Zener diode, and to produce a control voltage of the transistor equal to the voltage of the Zener diode;

[0028] the Zener diode is able, in the other state of the multiplied voltage, to produce a control voltage of the transistor equal to the opposite of the fifth voltage present across the terminals of the capacitor.

[0029] The invention also relates to a converter comprising at least one transistor and at least one device for controlling the transistor as previously described.

[0030] The invention also relates to an on-board system comprising such a converter.

[0031] Other features and advantages of the invention will appear upon reading the following description of embodiments of the invention, provided solely as an example and done in reference to the drawings, which are:

[0032] FIG. 1, a block diagram of an example of a transistor and a device for controlling the transistor,

[0033] FIG. 2, a schematic view of an electrical circuit comprising the transistor and the device for controlling the transistor of FIG. 1,

[0034] FIGS. 3 and 4, a timing diagram of a first control signal, respectively a second control signal,

[0035] FIGS. 5 and 6, a timing diagram of a first voltage, respectively a first and second converted voltage,

[0036] FIGS. 7 to 11, a timing diagram of a third voltage, respectively of a fourth voltage, respectively of a multiplied voltage, respectively of a fifth voltage, respectively of a control voltage, and

[0037] FIG. 12, a schematic view of an on-board system.

[0038] A transistor 10 and a device 12 for controlling such a transistor 10 are illustrated by FIGS. 1 and 2.

[0039] In the example illustrated by FIG. 2, the transistor 10 comprises a gate G, a source S, a drain D and a base B.

[0040] The transistor 10 is for example a MOSFET transistor. Such a MOSFET transistor is for example a silicon transistor or a silicon carbide transistor. Relative to silicon transistors, silicon carbide transistors have a higher voltage behavior, a higher switching speed, and a higher operating temperature.

[0041] The control device 12 is able to generate a control voltage V.sub.out of the transistor 10, and more particularly, a control voltage V.sub.out of the gate of the transistor 10.

[0042] The control device 12 comprises, successively connected to one another, a voltage source 15, a separating assembly 16, a transformer 18, a rectifier circuit 20, a latch 22, a switching assembly 24 and a shifting circuit 26.

[0043] The voltage source 15 is able to deliver a DC voltage V.sub.in to the input of the separating assembly 16.

[0044] The separating assembly 16 comprises a set of switches controlled by periodic pulse signals to deliver a first voltage V.sub.C as output. The first voltage V.sub.C is formed by successive pulses of amplitude alternately equal to the input voltage V.sub.in and equal to the opposite of the input voltage V.sub.in.

[0045] In particular, in the example of FIG. 2, the separating assembly 16 comprises two branches 28, 29 connected in parallel and supplied by the input voltage V.sub.in. The two branches 28, 29 of the separating assembly 16 thus form a bridge, called "H bridge".

[0046] The first branch 28 comprises two switches K1 and K3 connected in series at a midpoint M1. The second branch 29 comprises two switches K2 and K4 connected in series at a midpoint M2. Each switch K1, K2, K3, K4 is controlled by a control input 27A, 27B, 27C, 27D. For example, when the switches K1, K2, K3, K4 are field-effect transistors, the control inputs 27A, 27B, 27C, 27D correspond to the gates of said transistors.

[0047] The control inputs 27A, 27B of the switch K1 of the first branch 28 and the switch K4 of the second branch 29 are controlled by a first control signal V.sub.A. An example of a timing diagram of the first control signal V.sub.A is illustrated by FIG. 3.

[0048] The control inputs 27C, 27D of the switch K3 of the first branch 28 and the switch K2 of the second branch 29 are controlled by a second control signal V.sub.B. An example of a timing diagram of the second control signal V.sub.B is illustrated by FIG. 4.

[0049] The first control signal V.sub.A and the second control signal V.sub.B are generated by a pulse generator.

[0050] Each of the first control signal V.sub.A and the second control signal V.sub.B is made up of pulses with a constant width L, repeating with a constant period T such that the form factor L/T of each pulse is strictly less than 50 percent (%). The form factor of a pulse is the ratio of the width of the pulse to the period between the pulse and a consecutive pulse.

[0051] The high level of the pulses of the control signals V.sub.A, V.sub.B corresponds to the closed state of the corresponding switch K1, K2, K3, K4. The low level of the pulses of the control signals V.sub.A, V.sub.B corresponds to the open state of the corresponding switch K1, K2, K3, K4. The first control signal V.sub.A and the second control signal V.sub.B are time-shifted relative to one another such that there is no temporal overlap between the pulses of the first control signal V.sub.A and the second control signal V.sub.B. This is necessary so as not to short-circuit the voltage source 15.

[0052] Alternatively, the first control signal V.sub.A and the second control signal V.sub.B are formed by pulses of different widths L.sub.A and L.sub.B and/or different pulse repetition periods T.sub.A and T.sub.B. The first control signal V.sub.A and the second control signal V.sub.B are time-shifted relative to one another such that there is no temporal overlap between the pulses of the first control signal V.sub.A and the second control signal V.sub.B.

[0053] The separating assembly 16 is configured to deliver the first voltage V.sub.C, illustrated by FIG. 2, from the input voltage V.sub.in, of the first control signal V.sub.A and the second control signal V.sub.B.

[0054] The first voltage V.sub.C, illustrated in FIG. 5, is formed by:

[0055] pulses of amplitude equal to the input voltage V.sub.in and in phase with the pulses of the first control signal V.sub.A, and

[0056] pulse of amplitude equal to the opposite of the input voltage V.sub.in and in phase with the pulses of the second control signal V.sub.B.

[0057] Thus, to within the transitional responses of the switches, the first voltage V.sub.C is expressed in the form of the following expression:

V.sub.C=V.sub.inV.sub.an-V.sub.inV.sub.bn

where

[0058] V.sub.in is the input voltage,

[0059] V.sub.an is the first normalized control signal (value 0 or 1), and

[0060] V.sub.bn is the second normalized control signal (value 0 or 1).

[0061] The transformer 18 is supplied at the input with the first voltage V.sub.C.

[0062] The transformer 18 comprises a primary winding 31 and two secondary windings 34, 36.

[0063] The term "winding" refers to an electric coil.

[0064] The primary winding 31 is directly connected on the one hand to the midpoint M1 between the switches K1 and K3 of the first branch 28 of the separating assembly 16, and on the other hand, to the midpoint M2 between the switches K2 and K4 of the second branch 29 of the separating assembly 16 so as to receive the first voltage V.sub.C.

[0065] The secondary windings 34 and 36 have the same number of turns. The secondary windings 34 and 36 are connected to one another at a midpoint 38.

[0066] The first secondary winding 34 extends between a first terminal 40 and the midpoint 38. The second secondary winding 36 extends between a second terminal 42 and the midpoint 38.

[0067] The two secondary windings 34, 36 having the same number of turns, each of the first secondary winding 34 and the second secondary winding 36 in association with the primary winding 31 is able to convert the first voltage V.sub.C by multiplying the amplitude of said first voltage V.sub.C by a same multiplication coefficient N. The multiplication coefficient N is defined as the ratio of the number of turns of each secondary winding 34, 36 of the transformer 18 by the number of turns of the primary winding 31 of the transformer 18.

[0068] Thus, the first secondary winding 34 in association with the primary winding 31 is able to convert the first voltage V.sub.C to obtain a first converted voltage V.sub.D. The second winding 36 in association with the primary winding 31 is able to convert the first voltage V.sub.C to obtain a second converted voltage V.sub.E. Inasmuch as the multiplication coefficient N is the same for each of the first and second winding 34, 36, the second converted voltage V.sub.E is identical to the first converted voltage V.sub.D. An example of a timing diagram of the first and second converted voltage V.sub.D, V.sub.E is illustrated by FIG. 6.

[0069] Each of the first and second converted voltage V.sub.D, V.sub.E is formed by:

[0070] pulses of amplitude equal to the multiplication coefficient N multiplied by the first voltage V.sub.C and in phase with the pulses of the first voltage V.sub.C having an amplitude equal to the input voltage V.sub.in, and

[0071] pulses of amplitude equal to the multiplication coefficient N multiplied by the opposite of the first voltage V.sub.C and in phase with the pulses of the first voltage V.sub.C having an amplitude equal to the opposite of the input voltage V.sub.in.

[0072] The rectifier circuit 20 is able to extract the parts of the same sign from each converted voltage V.sub.D, V.sub.E and to deliver a third voltage V.sub.F from the extracted parts of the same sign. The expression "parts of the same sign" refers to the positive or negative component of a signal.

[0073] The third voltage V.sub.F is a DC voltage of amplitude equal to the peak value of the parts of the same sign of each converted voltage, and therefore the input voltage V.sub.in multiplied by the multiplication coefficient N of the transformer 18. An example of a timing diagram of the third voltage V.sub.F is illustrated by FIG. 7.

[0074] The rectifier circuit 20 is directly connected to each secondary winding 34, 36 of the transformer 18. Thus, the control voltage V.sub.out generated at the output of the device 12 is galvanically isolated from the input voltage V.sub.in, without adding other isolation devices such as additional transformers or optocouplers.

[0075] The rectifier circuit 20 comprises a rectifier 43 and a capacitor 44.

[0076] The rectifier circuit 20 has a terminal connected to the midpoint 38 and a terminal connected to the first terminal 40 so as to be supplied by the first converted voltage V.sub.D. The rectifier circuit 20 also has a terminal connected to the midpoint 38 and a terminal connected to the second terminal 42 so as to be supplied by the second converted voltage V.sub.E.

[0077] The rectifier 43 is able to rectify the converted voltage V.sub.D and the opposite of the converted voltage V.sub.E and to charge the capacitor 44 in order to obtain a third voltage V.sub.F.

[0078] The rectifier 43 comprises a first diode 45 and a second diode 46.

[0079] The anode of the first diode 45 is connected to the first terminal 40. The anode of the second diode 46 is connected to the second terminal 42. The cathodes of each of the first diode 45 and the second diode 46 are connected to one another at a connection point 48.

[0080] The first diode 45 is able to rectify the first converted voltage V.sub.D. The second diode 46 is able to rectify the opposite of the second converted voltage V.sub.E. In particular, each of the diodes 45, 46 only allowing the current to pass in one direction, said diodes 45, 46 provide the assembly formed by the capacitor 44 and the charge in parallel, with a voltage relative to the midpoint 38 that has a unique sign. In the example illustrated by FIG. 2, the orientation of the diodes 45, 46 causes the positive parts of the first converted voltage V.sub.D and the opposite of the second converted voltage V.sub.E to pass. In a variant in which the diodes 45, 46 are oriented in the opposite direction, the negative parts of the first converted voltage V.sub.D and the opposite of the second converted voltage V.sub.E pass.

[0081] The capacitor 44 is connected on the one hand to the midpoint 38, and on the other hand to the connection point 48.

[0082] The latch 22 is for example an RS latch (abbreviation for "Reset" and "Set").

[0083] The latch 22 is directly connected to the transformer 18.

[0084] The latch 22 comprises two inputs and at least one output.

[0085] The first input of the latch 22 receives the first converted voltage V.sub.D. The second input of the latch 22 receives the second converted voltage V.sub.E. The latch 22 is also supplied by a power source 23.

[0086] The latch 22 is able to deliver, as output, a fourth voltage V.sub.H from the converted voltages V.sub.D and V.sub.E. The fourth voltage V.sub.H is a logic signal having a high state and a low state. The first input of the latch 22 makes it possible to deliver the high state of the fourth voltage V.sub.H. The second input of the latch 22 makes it possible to deliver the low state of the fourth voltage V.sub.H. An example of a timing diagram of the fourth voltage V.sub.H is illustrated by FIG. 8.

[0087] In the example illustrated by the figures, the high state of the fourth voltage V.sub.H is triggered during rising edges of the positive pulses of the first converted voltage V.sub.D. The low state of the fourth voltage V.sub.H is triggered during rising edges of the positive pulses of the opposite of the second converted voltage V.sub.E, i.e., rising edges of the negative pulses of the second converted voltage V.sub.E.

[0088] The switching assembly 24 is able to multiply the third voltage V.sub.F by the normalized state of the fourth voltage V.sub.H to obtain a multiplied voltage V.sub.I.

[0089] The switching assembly 24 is connected to the rectifier circuit 20 so as to receive the third voltage V.sub.F. The switching assembly 24 is connected to the latch 22 so as to receive the fourth voltage V.sub.H.

[0090] The switching assembly 24 comprises two switches 50, 52 and a reverse amplifier 54.

[0091] The two switches 50, 52 are connected in series at a midpoint 56.

[0092] The first switch 50 comprises an input for controlling said switch 50 receiving the fourth voltage V.sub.H. The second switch 52 comprises an input for controlling said second switch 52 receiving the opposite of the fourth voltage V.sub.H, since the inverter 54 is connected between the output of the latch 22 and the input for controlling the second switch 52.

[0093] One of the states of the fourth voltage V.sub.H makes the switch 50 on (closed) and the switch 52 off (open). The other state of the fourth voltage V.sub.H makes the switch 50 off (open) and the switch 52 on (closed). For example, the high states of the fourth voltage V.sub.H turn on the switch 50 and turn off the switch 52, such that the multiplied voltage V.sub.I is equal to the third voltage V.sub.F. The low states of the fourth voltage V.sub.H turn off the switch 50 and turn on the switch 52, such that the multiplied voltage V.sub.I is equal to zero. An example of a timing diagram of the multiplied voltage V.sub.I is illustrated by FIG. 9.

[0094] The shifting circuit 26 able to shift the amplitude of the multiplied voltage V.sub.I to obtain a control voltage V.sub.out of the transistor 10.

[0095] The control voltage V.sub.out has a peak-to-peak amplitude equal to the third voltage V.sub.F. Furthermore, the control voltage V.sub.out has: a high state corresponding to the first state of the fourth voltage V.sub.H and a low state corresponding to the second state of the fourth voltage V.sub.H and in which the sign of the control voltage V.sub.out is opposite the sign of the high state.

[0096] In the example illustrated by FIG. 2, the shifting circuit 26 comprises a capacitor 60, a Zener diode 62 and a diode 63.

[0097] The shifting circuit 26 receives the multiplied voltage V.sub.I.

[0098] The capacitor 60 has a terminal connected at the output of the switching assembly 24 to the midpoint 56 between the two switches 50, 52 and a terminal connected to the cathode of the Zener diode 62 at a connection point 64.

[0099] The anode of the Zener diode 62 is connected to the anode of the diode 63. Thus, the Zener diode 62 and the diode 63 are arranged head to tail.

[0100] The cathode of the diode 63 is connected to the terminal of the capacitor 44 of the rectifier circuit 20, which is connected to the midpoint 38.

[0101] The diode 63 is able to block the passage of the current.

[0102] When the first switch 50 is on and the second switch 52 is off, the multiplied voltage V.sub.I is equal to the third voltage V.sub.F, the capacitor 60 is then charged to a fifth voltage V.sub.J equal to the third voltage V.sub.F decreased by the voltage V.sub.Z of the Zener diode 62 (to within the voltage drop of the diode 63) and the control voltage V.sub.out is equal to the voltage V.sub.Z of the Zener diode (to within the voltage drop of the diode 63). The voltage V.sub.Z of the Zener diode 62 is direct.

[0103] When the first switch 50 is off and the second switch 52 is on, the multiplied voltage V.sub.I is nil and the control voltage V.sub.out is equal to the opposite of the fifth voltage V.sub.J, i.e., to the voltage V.sub.Z of the Zener diode (to within the voltage drop of the diode 63) minus the third voltage V.sub.F. The diode 63 makes it possible to prevent the capacitor 60 from discharging into the Zener diode 62, which alone would be on and would short-circuit the capacitor 60.

[0104] Examples of timing diagrams of the fifth voltage V.sub.J and the control voltage V.sub.out are respectively illustrated by FIGS. 10 and 11.

[0105] The previous explanation is given as an example, ignoring the value of the voltage of the diode 63. If the voltage of the diode 63 is not ignored, the previous explanation remains valid by replacing the amplitude of the voltage V.sub.Z of the Zener diode 62 by the sum of the amplitudes of the voltage V.sub.Z of the Zener diode 62 and the voltage drop of the diode 63.

[0106] The operation of the device 12 for controlling the transistor 10 will now be described.

[0107] Initially, the separating assembly 16 generates a first voltage V.sub.C from the input voltage V.sub.in, of the first control signal V.sub.A and the second control signal V.sub.B.

[0108] Next, the first secondary winding 34 of the transformer 18 in association with the primary winding 31 converts the first voltage V.sub.C to obtain a first converted voltage V.sub.D. Likewise, the second secondary winding 36 of the transformer 18 in association with the primary winding 31 converts the first voltage V.sub.C to obtain a second converted voltage V.sub.E.

[0109] Then, the rectifier circuit 20 extracts the parts of the same sign from each converted voltage V.sub.D, -V.sub.E and delivers a third voltage V.sub.F from the extracted parts of the same sign. In particular, the rectifier 43 rectifies the converted voltage V.sub.D and the opposite of the converted voltage V.sub.E to obtain the third voltage V.sub.F. The capacitor 44 is charged at the third voltage V.sub.F.

[0110] In parallel, the latch 22 delivers a fourth voltage V.sub.H from the converted voltages V.sub.D and -V.sub.E.

[0111] Next, the switching assembly 24 multiplies the third voltage V.sub.F by the normalized state (0 or 1) of the fourth voltage V.sub.H to obtain a multiplied voltage V.sub.I.

[0112] Lastly, the shifting circuit 26 shifts the amplitude of the multiplied voltage V.sub.I to obtain a control voltage V.sub.out of the transistor 10. In particular, the capacitor 60 of the shifting circuit 26 charges itself at a fifth voltage V.sub.J equal to the third voltage V.sub.F decreased by the voltage V.sub.Z of the Zener diode 62, making it possible to obtain a control voltage V.sub.out of the transistor 10 with two states V.sub.Z and V.sub.Z-V.sub.F.

[0113] Thus, the control voltage 12 makes it possible to choose the voltage shift of the control voltage V.sub.out so as to obtain a symmetrical or asymmetrical control voltage V.sub.out as a function of the controlled transistor 10. This makes it possible to eliminate existing problems with the current control devices that are not suitable for controlling transistors requiring an asymmetrical control voltage, such as silicon carbide transistors.

[0114] Furthermore, the control device 12 has a low impedance with respect to the gate of the transistor 10, irrespective of the control phase of the transistor 10. The control device 12 is thus less sensitive to the risks of disruptions by stray coupling, which may affect the state of the charge of the transistor 10 gate.

[0115] Furthermore, the transformer 18 of the control device 12 does not directly charge the gate of the transistor 10, but passes through a buffer component that is the capacitor 44 of the rectifier circuit 20, which makes it possible to desensitize the control device 12 to resonance phenomena.

[0116] The control device 12 also has a relatively limited number of components, which makes it possible to keep a compact enough control device 12. In particular, the control device 12 allows the transmission of power and control in parallel via the transformer 18 with midpoint 38 without using other components, such as optocouplers or additional transformers to transmit the control.

[0117] FIG. 12 additionally illustrates an on-board system 100, such as an aircraft, comprising a converter 111. The converter 111 comprises the transistor 10 and the control device 12 of the transistor 10.

Claims

1. A device for controlling a transistor, the device comprising: a separating assembly for generating a first voltage from a DC input voltage, a first control signal and a second control signal, the first control signal and the second control signal each being formed by pulses with no temporal overlap between the pulses of said control signals, the first voltage being formed by: pulses of amplitude equal to the input voltage and in phase with the pulses of the first control signal, and pulse of amplitude equal to the opposite of the input voltage and in phase with the pulses of the second control signal, a transformer connected to the separating assembly, the transformer comprising two secondary windings, the two secondary windings being connected to one another at a midpoint, the first secondary winding being able to convert the first voltage to obtain a first converted voltage, the second secondary winding being able to convert the first voltage to obtain a second converted voltage, each of the first and second converted voltage being formed by: pulses of amplitude with the same sign as the first voltage and in phase with the pulses of the first voltage having an amplitude equal to the input voltage, and pulses of amplitude with the opposite sign from the first voltage and in phase with the pulses of the first voltage having an amplitude equal to the opposite of the input voltage, a rectifier circuit able to extract the parts of the same sign from the first converted voltage and of opposite sign from the second converted voltage and to generate a third voltage from the extracted parts of the same sign, a latch able to generate a fourth voltage from the converted voltages, the fourth voltage having a high state and a low state, the high state being triggered as a function of the sign of the amplitude of the first converted voltage, the low state being triggered as a function of the sign of the amplitude of the opposite of the second converted voltage, a switching assembly able to multiply the third voltage by the normalized state of the fourth voltage to obtain a multiplied voltage, the multiplied voltage having two states corresponding to the states of the fourth voltage, one of the states having a value equal to the third voltage, the other state having a nil value, and a shifting circuit able to shift the amplitude of the multiplied voltage to obtain a control voltage of the transistor, the control voltage having: a peak-to-peak amplitude equal to the third voltage, a high state corresponding to the high state of the fourth voltage, and a low state corresponding to the low state of the fourth voltage and in which the sign of the control voltage is opposite the sign of the high state of the control voltage.

2. The device according to claim 1, wherein each of the rectifier circuit and the latch is directly connected to the transformer.

3. The device according to claim 1, wherein each of the first secondary winding and the second secondary winding is able to convert the first voltage by multiplying it by a same multiplication coefficient.

4. The device according to claim 1, wherein the first winding extends between a first terminal and the midpoint and the second winding extends between a second terminal and the midpoint, the rectifier circuit being connected to the midpoint and each of the first terminal and the second terminal, the latch being connected to the first terminal and the second terminal.

5. The device according to claim 1, wherein the rectifier circuit comprises: a rectifier able to rectify the first converted voltage and the opposite of the second converted voltage to obtain a rectified voltage, the rectifier comprising a first diode and a second diode, the first diode being able to rectify the first converted voltage, the second diode being able to rectify the opposite of the second converted voltage, and a capacitor able to charge itself to obtain the third voltage.

6. The device according to claim 1, wherein the high state of the fourth voltage is triggered during rising edges of the positive pulses of the converted first voltage, the low state of the fourth voltage being triggered during rising edges of the positive pulses of the opposite of the converted second voltage.

7. The device according to claim 1, wherein the multiplied voltage has two states, the shifting circuit comprising a capacitor and a Zener diode; the Zener diode being able, in one of the states of the multiplied voltage, to charge the capacitor to a fifth voltage equal to the third voltage decreased by the voltage of the Zener diode, and to produce a control voltage of the transistor equal to the voltage of the Zener diode.

8. The device according to claim 7, wherein the Zener diode is able, in the other state of the multiplied voltage, to produce a control voltage of the transistor equal to the opposite of the fifth voltage present across the terminals of the capacitor.

9. A converter comprising at least one transistor and at least one device for controlling the transistor according to claim 1.

10. An on-board system comprising a converter according to claim 9.