ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY

Abstract

A one time programmable (OTP) non-volatile memory including a substrate, a switch device and a fuse structure is provided. The switch device is disposed on the substrate. The fuse structure includes a conductive layer, a spacer and a plug. The conductive layer is coupled to a terminal of the switch device. The spacer is disposed on a sidewall of the conductive layer. The plug is disposed on the conductive layer and covers the spacer. An overlap area of an overlap portion between the plug and a top surface of the conductive layer is smaller than a top view area of the plug.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefits of U.S. provisional application Ser. No. 62/063,410, filed on Oct. 14, 2014. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to a memory, and more particularly, to a one time programmable non-volatile memory (OTP non-volatile memory).

[0004] 2. Description of Related Art

[0005] Since a non-volatile memory device has an advantage of still maintaining stored data even if the power is cut off, it becomes a memory device widely used by personal computers and electronic equipments.

[0006] Generally, the non-volatile memory may be classified into the read only memory (ROM), the OTP memory and the rewritable memory.

[0007] In recent years, the one time programmable non-volatile memory has become an indispensable element in the semiconductor integrated circuit device. The one time programmable non-volatile memory may be extensively applied to perform a redundant function in the memories having great storage capacity, such as the dynamic random access memory (DRAM) or the static random access memory (SRAM). Besides, the one time programmable non-volatile memory may also be utilized for performing a calibrating function for analog circuits or code storage function for low keys, a data storage chip identification (ID) function for managing a fabrication process, and so forth.

[0008] Based on requirements of users, the one time programmable non-volatile memory may utilize a current to burn out a fuse therein in order to write in desired data and programs. However, it is a common goal in the industry as how to effectively reduce the current required to burn out the fuse.

SUMMARY OF THE INVENTION

[0009] The invention is directed to a one time programmable non-volatile memory capable of effectively reducing the current required to burn out the fuse.

[0010] The invention provides a one time programmable non-volatile memory, which includes a substrate, a switch device and a fuse structure. The switch device is disposed on the substrate. The fuse structure includes a conductive layer, a spacer and a plug. The conductive layer is coupled to a terminal of the switch device. The spacer is disposed on a sidewall of the conductive layer. The plug is disposed on the conductive layer and covers the spacer. An overlap area of an overlap portion between the plug and a top surface of the conductive layer is smaller than a top view area of the plug.

[0011] According to an embodiment of the invention, in the one time programmable non-volatile memory, the switch device is, for example, a transistor or a diode.

[0012] According to an embodiment of the invention, in the one time programmable non-volatile memory, the transistor is, for example, a metal oxide semiconductor field effect transistor (MOSFET).

[0013] According to an embodiment of the invention, in the one time programmable non-volatile memory, the metal oxide semiconductor field effect transistor includes a gate, a first doped region, a second doped region and a gate dielectric layer. The gate is disposed on the substrate. The first doped region and the second doped region are disposed in the substrate at two sides of the gate respectively. The first doped region is served as the terminal coupled to the conductive layer. The gate dielectric layer is disposed between the gate and the substrate.

[0014] According to an embodiment of the invention, in the one time programmable non-volatile memory, the conductive layer and the gate are originated from, for example, an identical semiconductor material layer.

[0015] According to an embodiment of the invention, in the one time programmable non-volatile memory, the conductive layer is coupled to the first doped region through an interconnect structure, for example.

[0016] According to an embodiment of the invention, in the one time programmable non-volatile memory, the diode is, for example, a P-N junction diode or a PIN (P-intrinsic-N) diode.

[0017] According to an embodiment of the invention, in the one time programmable non-volatile memory, the diode includes a P-type semiconductor layer and an N-type semiconductor layer. The N-type semiconductor layer is disposed at one side of the P-type semiconductor layer and served as the terminal coupled to the conductive layer.

[0018] According to an embodiment of the invention, in the one time programmable non-volatile memory, the conductive layer and the N-type semiconductor layer are originated from, for example, an identical semiconductor material layer.

[0019] According to an embodiment of the invention, in the one time programmable non-volatile memory, an intrinsic layer may be further included. The intrinsic layer is disposed between the P-type semiconductor layer and the N-type semiconductor layer.

[0020] According to an embodiment of the invention, in the one time programmable non-volatile memory, a material of the intrinsic layer is, for example, a polysilicon.

[0021] According to an embodiment of the invention, in the one time programmable non-volatile memory, the conductive layer is, for example, directly connected to the N-type semiconductor layer.

[0022] According to an embodiment of the invention, in the one time programmable non-volatile memory, the plug may completely cover or partially cover the spacer.

[0023] According to an embodiment of the invention, in the one time programmable non-volatile memory, a width of the conductive layer at the overlap portion is, for example, less than a width of the plug.

[0024] According to an embodiment of the invention, in the one time programmable non-volatile memory, the width of the conductive layer at the overlap portion is, for example, a minimal width complied with a design rule for the conductive layer.

[0025] According to an embodiment of the invention, in the one time programmable non-volatile memory, the width of the plug is, for example, a minimal width complied with a design rule for the plug.

[0026] According to an embodiment of the invention, in the one time programmable non-volatile memory, a material of the conductive layer is, for example, a doped polysilicon.

[0027] According to an embodiment of the invention, in the one time programmable non-volatile memory, the plug is, for example, a contact plug or a via plug.

[0028] According to an embodiment of the invention, in the one time programmable non-volatile memory, a material of the plug is, for example, W, Cu, Al, Au, Ag, or an alloy thereof.

[0029] According to an embodiment of the invention, in the one time programmable non-volatile memory, an isolation structure may be further included. The isolation structure is disposed in the substrate. The conductive layer is located on the isolation structure.

[0030] Based on the above, according to the one time programmable non-volatile memory proposed in the foregoing embodiments, the overlap area of the overlap portion between the plug and the top surface of the conductive layer is smaller than the top view area of the plug, so that the current will concentrated at the overlap portion between the plug and the top surface of the conductive layer during writing operation of the memory.

[0031] Therefore, it only requires smaller current to burn out the fuse structure, such that the current required to burn out the fuse structure may be effectively reduced.

[0032] To make the above features and advantages of the present disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0034] FIG. 1 is a top view of a one time programmable non-volatile memory according to an embodiment of the invention.

[0035] FIG. 2A is a cross-sectional view taken along a sectional line I-I' depicted in FIG. 1.

[0036] FIG. 2B is a cross-sectional view taken along a sectional line II-II' depicted in FIG. 1.

[0037] FIG. 3 is a top view of a one time programmable non-volatile memory according to another embodiment of the invention.

[0038] FIG. 4 is a cross-sectional view taken along a sectional line depicted in FIG. 3.

DESCRIPTION OF THE EMBODIMENTS

[0039] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0040] FIG. 1 is a top view of a one time programmable non-volatile memory according to an embodiment of the invention. In order to clearly describe a structure of the one time programmable non-volatile memory, illustration of an isolation structure and a dielectric layer is omitted in FIG. 1. FIG. 2A is a cross-sectional view taken along a sectional line I-I' depicted in FIG. 1. FIG. 2B is a cross-sectional view taken along a sectional line II-II' depicted in FIG. 1.

[0041] Referring to FIG. 1, FIG. 2A and FIG. 2B together, a one time programmable non-volatile memory 10 includes a substrate 100, a switch device 102 and a fuse structure 104. The substrate 100 is, for example, a silicon substrate.

[0042] The switch device 102 is disposed on the substrate 100. The switch device 102 is, for example, a transistor or a diode. The transistor is, for example, a metal oxide semiconductor field effect transistor. The diode is, for example, a P-N junction diode or a PIN diode.

[0043] In this embodiment, the switch device 102 is illustrated as the metal oxide semiconductor field effect transistor for example, but the invention is not limited thereto. It falls in the scope of the invention for which protection is sought as long as the switch device is an electronic component with switch functions. The switch device 102 includes a gate 106, a doped region 108, a doped region 110 and a gate dielectric layer 112. The gate 106 is disposed on the substrate 100. A material of the gate 106 is, for example, a doped polysilicon. The doped region 108 and the doped region 110 are disposed in the substrate 100 at two sides of the gate 106 respectively, and can be served as a source and a drain respectively. The doped region 108 may be connected to an external power source or an external circuit through a plug 109 and a wire 111 located in a dielectric layer 107. A material of the dielectric layer 107 is, for example, a silicon oxide. A material of the plug 109 is, for example, W, Cu, Al, Au, Ag, or an alloy thereof A material of the wire 111 is, for example, Cu, Al or W. The gate dielectric layer 112 is disposed between the gate 106 and the substrate 100. A material of the gate dielectric layer 112 is silicon oxide, for example. In addition, the switch device 102 may further include a spacer 114. The spacer 114 is disposed on a sidewall of the gate 106. A material of the spacer 114 is, for example, a silicon oxide, silicon nitride, dielectric layer or composite dielectric layer.

[0044] The fuse structure 104 includes a conductive layer 116, a spacer 118 and a plug 120. The conductive layer 116 is coupled to a terminal of the switch device 102. In this embodiment, the conductive layer 116 is described by using a shape of dumb bell that is wider at two ends and is narrow at middle as an example, but the invention is not limited thereto. In other embodiments, the conductive layer 116 may also be a rectangle with uniform width. The conductive layer 116 and the gate 106 are originated from, for example, an identical semiconductor material layer. A material of the conductive layer 116 is, for example, a doped polysilicon.

[0045] In this embodiment, the doped region 110 of the switch device 102 is served as the terminal coupled to the conductive layer 116 for example, that is, the conductive layer 116 is coupled to the doped region 110 of the switch device 102. The conductive layer 116 is coupled to the doped region 110 through an interconnect structure 122, for example. For instance, the interconnect structure 122 is located in the dielectric layer 107, and includes a plug 124, a wire 126 and a plug 128 connected in sequence. As such, the conductive layer 116 may be coupled to the doped region 110 through the plug 124, the wire 126 and the plug 128. Materials of the plug 124 and the plug 128 are, for example, W, Cu, Al, Au, Ag, or an alloy thereof, respectively. A material of the wire 126 is, for example, Cu, Al or W.

[0046] The spacer 118 is disposed on a sidewall of the conductive layer 116. The spacer 118 and the spacer 114 are originated from, for example, an identical spacer material layer. A material of the spacer 118 is, for example, a silicon oxide, silicon nitride, dielectric layer or composite dielectric layer.

[0047] The plug 120 is disposed on the conductive layer 116 and covers the spacer 118. The plug 120 is, for example, located in the dielectric layer 107. An overlap area of an overlap portion R1 between the plug 120 and a top surface of the conductive layer 116 is smaller than a top view area of the plug 120. Accordingly, during writing operation of the memory, the current will concentrated at the overlap portion R1 between the plug 120 and the top surface of the conductive layer 116. Therefore, it only requires smaller current to burn out the fuse structure 104, such that the current required to burn out the fuse structure 104 may be effectively reduced. In addition, the plug 120 can completely cover or partially cover the spacer 118. This embodiment is described by using an example in which the plug 120 completely covers the spacer 118 (referring to FIG. 2B). The plug 120 may be connected to an external power source or an external circuit through a wire 130 in the dielectric layer 107. A material of the wire 130 is, for example, Cu, Al or W.

[0048] Further, a width W1 of the conductive layer 116 at the overlap portion R1 is, for example, less than a width W2 of the plug 120. The plug 120 is, for example, a contact plug or a via plug. A material of the plug 120 is, for example, W, Cu, Al, Au, Ag, or an alloy thereof

[0049] Furthermore, the width W1 of the conductive layer 116 at the overlap portion R1 is, for example, a minimal width complied with a design rule for the conductive layer 116 and the width W2 of the plug 120 is, for example, a minimal width complied with a design rule for the plug 120. Therefore, the current required to burn out the fuse structure 104 may be further reduced by setting the line widths to the minimal widths.

[0050] Moreover, in another embodiment, the width W1 of the conductive layer 116 at the overlap portion R1 is 10% less than a minimal width complied with a design rule for the conductive layer 116, for example. Or the width W2 of the plug 120 is 10% less than a minimal width complied with a design rule for the plug 120, for example. That is to say, the width W1 of the conductive layer 116 and the width W2 of the plug 120 may be set to be less than the minimal width of the design rule. Therefore, the current required to burn out the fuse structure 104 may be further reduced.

[0051] Also, the one time programmable non-volatile memory 10 may further include an isolation structure 132. The isolation structure 132 is disposed in the substrate 100, and the conductive layer 116 is, for example, located on a dielectric layer 113 above the isolation structure 132. The isolation structure 132 is a shallow trench isolation structure, for example. A material of the isolation structure 132 is, for example, a silicon oxide. The dielectric layer 113 and the gate dielectric layer 112 are originated from, for example, an identical dielectric material layer. A material of the dielectric layer 113 is, for example, a silicon oxide.

[0052] Based on the foregoing embodiments, it can be known that, in the one time programmable non-volatile memory 10, by setting the overlap area of the overlap portion R1 between the plug 120 and the top surface of the conductive layer 116 to be smaller than the top view area of the plug 120, it only requires smaller current to burn out the fuse structure 104, such that the current required to burn out the fuse structure 104 may be effectively reduced.

[0053] FIG. 3 is a top view of a one time programmable non-volatile memory according to another embodiment of the invention. In order to clearly describe a structure of the one time programmable non-volatile memory, illustration of an isolation structure and a dielectric layer is omitted in FIG. 3. FIG. 4 is a cross-sectional view taken along a sectional line depicted in FIG. 3.

[0054] Referring to FIG. 3 and FIG. 4 together, a one time programmable non-volatile memory 20 includes a substrate 200, a switch device 202 and a fuse structure 204. The substrate 200 is, for example, a silicon substrate.

[0055] In this embodiment, the switch device 202 is illustrated as the diode for example, but the invention is not limited thereto. It falls in the scope of the invention for which protection is sought as long as the switch device is an electronic component with switch functions. The switch device 202 includes a P-type semiconductor layer 206 and an N-type semiconductor layer 208. The P-type semiconductor layer 206 is disposed on the substrate 200. A material of the P-type semiconductor layer 206 is, for example, a doped polysilicon. The N-type semiconductor layer 208 is disposed on the substrate 200 at one side of the P-type semiconductor layer 206. A material of the N-type semiconductor layer 208 is, for example, a doped polysilicon. In addition, the switch device 202 may further include an intrinsic layer 210. The intrinsic layer 210 is disposed between the P-type semiconductor layer 206 and the N-type semiconductor layer 208. A material of the intrinsic layer 210 is, for example, a polysilicon. In addition, the switch device 202 may further include a spacer 212. The spacer 212 may be disposed on a sidewall of the P-type semiconductor layer 206, the N-type semiconductor layer 208 and the intrinsic layer 210. A material of the spacer 212 is, for example, a silicon oxide, silicon nitride, dielectric layer or composite dielectric layer.

[0056] The fuse structure 204 includes a conductive layer 214, a spacer 216 and a plug 218. The conductive layer 214 is coupled to a terminal of the switch device 202. In this embodiment, the conductive layer 214 is described by using a shape of hammer that is wider at one end, but the invention is not limited thereto. In other embodiments, the conductive layer 214 may also be a rectangle with uniform width. The conductive layer 214 and the N-type semiconductor layer 208 are originated from, for example, an identical semiconductor material layer. A material of the conductive layer 214 is, for example, a doped polysilicon.

[0057] In this embodiment, the N-type semiconductor layer 208 of the switch device 202 is served as the terminal coupled to the conductive layer 214 for example, that is, the conductive layer 214 is coupled to the N-type semiconductor layer 208 of the switch device 202. The conductive layer 214 is, for example, directly connected to the N-type semiconductor layer 208.

[0058] The spacer 216 is disposed on a sidewall of the conductive layer 214. The spacer 216 and the spacer 212 are originated from, for example, an identical spacer material layer. A material of the spacer 216 is, for example, a silicon oxide, silicon nitride, dielectric layer or composite dielectric layer.

[0059] The plug 218 is disposed on the conductive layer 214 and covers the spacer 216. The plug 218 is, for example, located in the dielectric layer 220. A material of the dielectric layer 220 is, for example, a silicon oxide. An overlap area of an overlap portion R2 between the plug 218 and a top surface of the conductive layer 214 is smaller than a top view area of the plug 218. Accordingly, during writing operation of the memory, the current will concentrated at the overlap portion R2 between the plug 218 and the top surface of the conductive layer 214. Therefore, it only requires smaller current to burn out the fuse structure 204, such that the current required to burn out the fuse structure 204 may be effectively reduced. In addition, the plug 218 can completely cover or partially cover the spacer 216. This embodiment is described by using an example in which the plug 218 completely covers the spacer 216 (referring to FIG. 4).

[0060] Moreover, a width W3 of the conductive layer 214 at the overlap portion R2 is, for example, less than a width W4 of the plug 218. The plug 218 is, for example, a contact plug or a via plug. A material of the plug 218 is, for example, W, Cu, Al, Au, Ag, or an alloy thereof.

[0061] Furthermore, the width W3 of the conductive layer 214 at the overlap portion R2 is, for example, a minimal width complied with a design rule for the conductive layer 214 and the width W4 of the plug 218 is, for example, a minimal width complied with a design rule for the plug 218. Therefore, the current required to burn out the fuse structure 204 may be further reduced by setting the line widths to the minimal widths.

[0062] Moreover, in another embodiment, the width W3 of the conductive layer 214 at the overlap portion R2 is 10% less than a minimal width complied with a design rule for the conductive layer 214, for example. Or the width W4 of the plug 218 is 10% less than a minimal width complied with a design rule for the plug 218, for example. That is to say, the width W3 of the conductive layer 214 and the width W4 of the plug 218 may be set to be less than the minimal width of the design rule. Therefore, the current required to burn out the fuse structure 204 may be further reduced.

[0063] Also, the one time programmable non-volatile memory 20 may further include an isolation structure 222. The isolation structure 222 is disposed in the substrate 200, and the conductive layer 214 is located on the isolation structure 222. The isolation structure 222 is a shallow trench isolation structure, for example. A material of the isolation structure 222 is, for example, a silicon oxide.

[0064] Based on the foregoing embodiments, it can be known that, in the one time programmable non-volatile memory 20, by setting the overlap area of the overlap portion R2 between the plug 218 and the top surface of the conductive layer 214 to be smaller than the top view area of the plug 218, it only requires smaller current to burn out the fuse structure 204, such that the current required to burn out the fuse structure 204 may be effectively reduced.

[0065] In summary, according to the one time programmable non-volatile memory proposed in the foregoing embodiments, the current required to burn out the fuse structure may be effectively reduced by setting the overlap area of the overlap portion between the plug and the top surface of the conductive layer to be smaller than the top view area of the plug.

[0066] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A one time programmable non-volatile memory, comprising: a substrate; a switch device, disposed on the substrate; and a fuse structure comprising: a conductive layer, coupled to a terminal of the switch device; a spacer, disposed on a sidewall of the conductive layer; and a plug, disposed on the conductive layer and covering the spacer, wherein an overlap area of an overlap portion between the plug and a top surface of the conductive layer is smaller than a top view area of the plug.

2. The one time programmable non-volatile memory of claim 1, wherein the switch device comprises a transistor or a diode.

3. The one time programmable non-volatile memory of claim 2, wherein the transistor comprises a metal oxide semiconductor field effect transistor.

4. The one time programmable non-volatile memory of claim 3, wherein the metal oxide semiconductor field effect transistor comprises: a gate, disposed on the substrate; a first doped region and a second doped region, disposed in the substrate at two sides of the gate respectively, wherein the first doped region is served as the terminal coupled to the conductive layer; and a gate dielectric layer, disposed between the gate and the substrate.

5. The one time programmable non-volatile memory of claim 4, wherein the conductive layer and the gate are originated from an identical semiconductor material layer.

6. The one time programmable non-volatile memory of claim 4, wherein the conductive layer is coupled to the first doped region through an interconnect structure.

7. The one time programmable non-volatile memory of claim 2, wherein the diode comprises a P-N junction diode or a PIN diode.

8. The one time programmable non-volatile memory of claim 2, wherein the diode comprises: a P-type semiconductor layer; and an N-type semiconductor layer, disposed at one side of the P-type semiconductor layer and served as the terminal coupled to the conductive layer.

9. The one time programmable non-volatile memory of claim 8, wherein the conductive layer and the N-type semiconductor layer are originated from an identical semiconductor material layer.

10. The one time programmable non-volatile memory of claim 8, further comprising: an intrinsic layer, disposed between the P-type semiconductor layer and the N-type semiconductor layer.

11. The one time programmable non-volatile memory of claim 10, wherein a material of the intrinsic layer comprises a polysilicon.

12. The one time programmable non-volatile memory of claim 8, wherein the conductive layer is directly connected to the N-type semiconductor layer.

13. The one time programmable non-volatile memory of claim 1, wherein the plug completely covers or partially covers the spacer.

14. The one time programmable non-volatile memory of claim 1, wherein a width of the conductive layer at the overlap portion is smaller than a width of the plug.

15. The one time programmable non-volatile memory of claim 14, wherein the width of the conductive layer at the overlap portion is a minimal width complied with a design rule for the conductive layer.

16. The one time programmable non-volatile memory of claim 14, wherein the width of the plug is a minimal width complied with a design rule for the plug.

17. The one time programmable non-volatile memory of claim 1, wherein a material of the conductive layer comprises a doped polysilicon.

18. The one time programmable non-volatile memory of claim 1, wherein the plug comprises a contact plug or a via plug.

19. The one time programmable non-volatile memory of claim 1, wherein a material of the plug comprises W, Cu, Al, Au, Ag, or an alloy thereof.

20. The one time programmable non-volatile memory of claim 1, further comprising: an isolation structure, disposed in the substrate, wherein the conductive layer is located on the isolation structure.

Images