Patent application number | Description | Published |
20150194660 | 3D BARRIER SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An embodiment of the present invention discloses a 3D barrier substrate o and a method for manufacturing the same, and a display device in order to improve the utilization of facilities, increase the production efficiency, and decrease the cost of production. The method of manufacturing 3D barrier substrate comprises: forming a transparent electrode thin film on a substrate, and forming a passivation layer on the transparent electrode thin film; forming an transparent electrode and a passivation layer via hole by a patterning process, wherein the via hole is used for coupling the transparent electrode to the signal line; and forming a signal line, wherein the signal line is coupled to the transparent electrode through the via hole. | 07-09-2015 |
20150228733 | Array Substrate, Manufacturing Method Thereof, and Display Device - The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate comprises a gate electrode, a gate line, a data line, a gate insulating layer, an active layer, a source electrode and a drain electrode on a substrate. The gate electrode, the gate line and the data line are arranged on an identical layer, the gate line intersects the data line at a right angle, and the data line is disconnected at an intersection with the gate line. The source electrode and the drain electrode are arranged above the gate electrode, the gate line and the data line, and the disconnected data lines are connected via the source electrode. | 08-13-2015 |
20150236128 | THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE - The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably. | 08-20-2015 |
20150311222 | Array Substrate, Its Manufacturing Method, and Display Device - The present invention provides an array substrate, its manufacturing method, and a display device. The array substrate comprises a gate metal layer, a gate insulating layer, a source/drain metal layer, first common electrode lines arranged on an identical layer to the gate metal layer, a first via hole arranged in the gate insulating layer and corresponding to the first common electrode line, a source/drain metal filling part arranged within the first via hole, a second via hole in communication with the first via hole, and a transparent connection part. The first common electrode lines are, by means of the transparent connection part and the source/drain metal filling part, in electrical connection with each other through the second via hole. According to the present invention, it is able to reduce the depth of the via holes in the array substrate, and improve the uneven diffusion of an alignment layer. | 10-29-2015 |
20150318304 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product. | 11-05-2015 |
20150318362 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor and manufacturing method thereof, an array substrate ( | 11-05-2015 |
20150325159 | ARRAY SUBSTRATE AND TESTING METHOD AND MANUFACTURING METHOD THEREOF - An array substrate, a testing method and a manufacturing method of the array substrate are disclosed. The array substrate comprises a first test line ( | 11-12-2015 |
20150329432 | Method for Preparing Polycrystalline Metal Oxide Pattern - Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal oxide film by laser, so as to convert the amorphous metal oxide in the predetermined region into a polycrystalline metal oxide; and etching the amorphous metal oxide outside of the predetermined region so as to remove it. By the method according to the present invention, firstly, the predetermined region of an amorphous metal oxide film is annealed by laser so as to convert the amorphous metal oxide into a polycrystalline metal oxide, and then, the amorphous metal oxide outside of the predetermined region is etched away, thereby a polycrystalline metal oxide pattern is formed. The method for preparing a polycrystalline metal oxide pattern according to the present invention is simple, and can effectively shorten the production period and save production costs. | 11-19-2015 |