Patent application number | Description | Published |
20080292116 | MULTI-MODE AUDIO AMPLIFIERS - A multimode audio amplifier comprises: a mode controller adapted to provide a control signal; and at least one multimode module, wherein each of the multimode modules has a plurality of operating modes, wherein the operating modes are selected in accordance with the control signal, wherein changing the operating modes results in a measurable change in at least one characteristic of the multimode audio amplifier; wherein the characteristics of the multimode audio amplifier consist of signal to noise ratio (SNR); total harmonic distortion and noise (THD+N); input to output delay; power consumption; and efficiency. | 11-27-2008 |
20090055605 | METHOD AND SYSTEM FOR OBJECT-ORIENTED DATA STORAGE - In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read/write speed requirements. A data block to be written may be considered an object, and is examined, and from its attributes one or more memory device operating modes may be determined, such as different numbers of bits per cell, different numbers of error-correction code (ECC) parities per user data block, and encryption vs. lack of encryption. The storage controller then performs the writing process according to the mode(s) of operation determined by the attributes. Multi-level flash memory, in particular, is capable of operating in these various modes, at a trade-off between reliability, speed, endurance on the one hand, and capacity on the other hand. | 02-26-2009 |
20090055717 | ARCHITECTURE AND CONTROL OF REED-SOLOMON LIST DECODING - Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | 02-26-2009 |
20090059661 | SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE - A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells. | 03-05-2009 |
20090063937 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-05-2009 |
20090083608 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-26-2009 |
20090150746 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the | 06-11-2009 |
20090210771 | SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION - A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell. | 08-20-2009 |
20090292976 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR IDENTIFICATION AND EVALUATION - Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | 11-26-2009 |
20090300465 | STATISTICAL TRACKING FOR FLASH MEMORY - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data. | 12-03-2009 |
20090319825 | MONITORING MEMORY - Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory. | 12-24-2009 |
20100034018 | ACCESSING MEMORY USING FRACTIONAL REFERENCE VOLTAGES - Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results. | 02-11-2010 |
20100269026 | ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING - The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths. | 10-21-2010 |
20100322353 | NONLINEAR POST-PROCESSORS FOR CHANNELS WITH SIGNAL-DEPENDENT NOISE - A non-linear post-processor for estimating at least one source of signal-dependent noise is disclosed. The post processor may receive a set of preliminary decisions from a sub-optimal detector along with the sampled data signal. The post-processor may then compute the transition jitter and white noise associated with each preliminary decision in the set and assign a cost metric to each decision based on the total signal noise. The post-processor may output the decision with the lowest cost metric as the final decision of the detector. | 12-23-2010 |
20110043390 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-24-2011 |
20110060969 | METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY - A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels. | 03-10-2011 |
20110082976 | METHOD AND SYSTEM FOR OBJECT-ORIENTED DATA STORAGE - In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read or write speed requirements. A data block to be written may be considered an object, and is examined, and from its attributes one or more memory device operating modes may be determined, such as different numbers of bits per cell, different numbers of error-correction code (ECC) parities per user data block, and encryption vs. lack of encryption. The storage controller then performs the writing process according to the mode(s) of operation determined by the attributes. Respective designated portions of the storage device may be selectively operated in respective ones of a plurality of operating modes to process each of the plurality of data objects based on a corresponding one or more of the attributes. | 04-07-2011 |
20110225477 | SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information. | 09-15-2011 |
20120023284 | Nonvolatile Memory System - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 01-26-2012 |
20120042224 | System and Method for Correcting Errors in Non-Volatile Memory Using Product Codes - A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension. | 02-16-2012 |
20120099372 | Sequence Detection for Flash Memory With Inter-Cell Interference - A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells. | 04-26-2012 |
20120137197 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 05-31-2012 |
20120233524 | LOW-DENSITY PARITY CHECK CODES FOR HOLOGRAPHIC STORAGE - Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput. | 09-13-2012 |
20120278545 | NON-VOLATILE MEMORY DEVICE WITH NON-EVENLY DISTRIBUTABLE DATA ACCESS - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes memory cells arranged among physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 11-01-2012 |
20120278682 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 11-01-2012 |
20120278686 | SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information. | 11-01-2012 |
20120284588 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 11-08-2012 |
20120317459 | SYSTEMS AND METHODS FOR OPERATING ON A STORAGE DEVICE USING A LIFE-CYCLE DEPENDENT CODING SCHEME - Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme. | 12-13-2012 |
20120331368 | SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION - A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell. | 12-27-2012 |
20130058504 | MULTI-MODE AUDIO AMPLIFIERS - A multimode audio amplifier comprises: a mode controller adapted to provide a control signal; and at least one multimode module, wherein each of the multimode modules has a plurality of operating modes, wherein the operating modes are selected in accordance with the control signal, wherein changing the operating modes results in a measurable change in at least one characteristic of the multimode audio amplifier; wherein the characteristics of the multimode audio amplifier consist of signal to noise ratio (SNR); total harmonic distortion and noise (THD+N); input to output delay; power consumption; and efficiency. | 03-07-2013 |
20130073922 | METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF ITERATIVE DECODERS ON CHANNELS WITH MEMORY - Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode. | 03-21-2013 |
20130080729 | PILOT PLACEMENT FOR NON-VOLATILE MEMORY - A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison. | 03-28-2013 |
20130107622 | SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE | 05-02-2013 |
20130117637 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 05-09-2013 |
20130229869 | ACCESSING MEMORY USING REFERENCE VOLTAGES - Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of reference voltages that are near an integral reference voltage to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results. | 09-05-2013 |
20130243073 | ADAPTIVELY INTERPOLATING AND SEARCHING TO REFINE SAMPLING IN PULSE WIDTH MODULATION - Systems, methods, and other embodiments associated with estimating a natural sampling point from uniform sample points when generating a PWM signal are described. According to one embodiment, an apparatus includes a cross point logic configured to determine which of the samples along the analog signal are adjacent to a crossing point of a reference signal and the analog signal by identifying samples between which the crossing point occurs. The apparatus includes an interpolation logic configured to adaptively interpolate points along the analog signal that approach the crossing point by using the samples. The interpolation logic is configured to adaptively interpolate the points to refine a region between the points within which the crossing point occurs. The apparatus includes a search logic configured to search within the region to produce an estimated location of the crossing point by using the interpolated points. | 09-19-2013 |
20130246879 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 09-19-2013 |
20130290813 | Method and System For Error Correction in Flash Memory - A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal. | 10-31-2013 |
20140143641 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 05-22-2014 |
20140157068 | PROGRAMMING NONVOLATILE MEMORY BASED ON STATISTICAL ANALYSIS OF CHARGE LEVEL DISTRIBUTIONS OF MEMORY CELLS - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data. | 06-05-2014 |
20140173197 | METHOD AND STORAGE DRIVE FOR WRITING PORTIONS OF BLOCKS OF DATA IN RESPECTIVE ARRAYS OF MEMORY CELLS OF CORRESPONDING INTEGRATED CIRCUITS - A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells. | 06-19-2014 |
20140201600 | APPARATUS AND METHOD FOR ENCODING DATA FOR STORAGE IN MULTI-LEVEL NONVOLATILE MEMORY - A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory. | 07-17-2014 |
20140325179 | SYSTEM AND METHOD FOR WRITING PILOT DATA INTERSPERSED WITH USER DATA FOR ESTIMATING DISTURBANCE EXPERIENCED BY USER DATA - A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page. | 10-30-2014 |
20150058702 | MULTI-LEVEL MEMORY CONTROLLER WITH PROBABILITY-DISTRIBUTION-BASED ENCODING - A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells. | 02-26-2015 |