Patent application number | Description | Published |
20080288905 | Method and Apparatus for Congestion Based Physical Synthesis - A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set of candidate areas is determined to form a set of costs. The cost associated with a candidate area is the cost of making the change to the circuit design in the candidate area. Using the set of costs, a candidate area is selected from the set of candidate areas in which to make the change to the circuit design. | 11-20-2008 |
20110302545 | DETAILED ROUTABILITY BY CELL PLACEMENT - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing. | 12-08-2011 |
20110320992 | BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit. | 12-29-2011 |
20120011482 | MULTIPLE THRESHOLD VOLTAGE CELL FAMILIES BASED INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families. | 01-12-2012 |
20120110532 | LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS - A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one. | 05-03-2012 |
20120124539 | Clock Optimization with Local Clock Buffer Control Optimization - A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers. | 05-17-2012 |
20120144358 | Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs - A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated. | 06-07-2012 |
20120240093 | ROUTING AND TIMING USING LAYER RANGES - A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range. | 09-20-2012 |
20120284683 | TIMING DRIVEN ROUTING IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design. | 11-08-2012 |
20130086543 | MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design. | 04-04-2013 |
20130272126 | CONGESTION AWARE ROUTING USING RANDOM POINTS - In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin. | 10-17-2013 |
20130275934 | SOLVING CONGESTION USING NET GROUPING - A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure. | 10-17-2013 |
20140071827 | SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING - A method, system, and computer program product for solving a network traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested network route section is selected from a set of congested network route sections. A set of congesting devices is selected, where the set of congesting devices causes congestion in the selected congested network route sections by using the selected congested network route section. A vacancy data structure corresponding to the selected congested network route section is populated. A subset of the set of the congesting devices is selected. The subset of the set of the congesting devices is rerouted to a candidate network route section identified in the vacancy data structure. | 03-13-2014 |
20140074389 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-13-2014 |
20140081478 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-20-2014 |
20140088791 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-27-2014 |