Patents - stay tuned to the technology

Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Zheng, San Jose

Bo Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20150085586MEMORY DEVICE AND METHOD OF OPERATION OF SUCH A MEMORY DEVICE - A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.03-26-2015
20150117119MEMORY CIRCUITRY WITH WRITE ASSIST - Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.04-30-2015
20150138901MEMORY CIRCUITRY USING WRITE ASSIST VOLTAGE BOOST - Within a memory 05-21-2015
20160005448Memory Circuitry Using Write Assist Voltage Boost - Within a memory 01-07-2016

Chenchen Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20160124227SYSTEM AND METHOD FOR MOUNTING HEADS-UP DISPLAY MODULES - A device comprising means for engaging said device to at least a portion of an outside surface of a glass of a headwear, means for engaging said device to at least a portion of an inside surface of glass of said headwear, means for mounting a display module or video capturing device and said means for engaging said device to at least a portion of an inside surface of a headwear to said device, and means for adjusting a viewing angle of said display module or video capturing device with a generally 360 degrees rotation.05-05-2016

Chunguang Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20090138762COMPUTER-IMPLEMENTED METHOD OF PERFORMANCE TESTING SOFTWARE APPLICATIONS - A method of performance testing for software applications can include storing, in a network accessible location, options corresponding to functions for use in performance test cases and sending to a computer system an electronic document specifying at least one of the plurality of options. The computer system can be remotely located from the network accessible location. The method further can include receiving, from the computer system, input selecting at least one option from the electronic document and automatically generating a performance test case using functions corresponding to the selected option(s). The options can be selected through a Web-based shopping cart and/or system interface thereby easing the process of test case generation.05-28-2009

Fenghua Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20140198093LOW POWER DISPLAY DEVICE WITH VARIABLE REFRESH RATES - The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.07-17-2014
20140198114LOW POWER DISPLAY DEVICE WITH VARIABLE REFRESH RATES - The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.07-17-2014
20140198138LOW POWER DISPLAY DEVICE WITH VARIABLE REFRESH RATES - The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.07-17-2014
20150199292METHOD AND APPARATUS FOR SIMPLIFYING COMMUNICATION BETWEEN A HOST SYSTEM AND A DISPLAY SUBSYSTEM - A method for simplifying the host-to-display subsystem communications and consolidating the non-volatile memory requirements into a PMIC (power management integrated circuit) is disclosed. Hardware and software resource reduction in both the client devices (located in the display subsystem) and the host System on a Chip (SOC) can be realized with a novel PMIC design. The novel PMIC design achieves the resource reduction by providing for the following features: (1) Single-point communication, (2) Single-point notification, (3) Client device status storage, (4) Client device initialization from PMIC non-volatile memory, and (5) Subsystem calibration retrieval from PMIC non-volatile memory.07-16-2015
20150348487Electronic Device Display With Display Driver Power-Down Circuitry - Display driver circuitry loads data into display pixels. A regulator produces a power supply voltage for display driver circuitry that is measured by a monitor circuit. The monitor circuit asserts a mode selection signal in response to detection of a drop in power supply voltage during a power-down event. The display driver circuitry contains mode selection circuitry that is controlled by the mode selection signal. The mode selection circuit allows a controlled parallel driver shutdown sequence. During normal operation, the mode selection signal is deasserted and the display driver circuitry loads image data for the display into the display pixels. When the mode selection signal is asserted, mode selection circuitry and other circuitry in the display driver circuitry continue to operate during the power down so as to load safe data into the display pixels to avoid damaging the display when the display has been powered off.12-03-2015
20150364088POWER EFFICIENT ADAPTIVE PANEL PIXEL CHARGE SCHEME - This application relates to systems, methods, and apparatus for reducing the power consumption of a display panel. Specifically, the embodiments discussed herein relate to a panel pixel charge scheme that allows the current output of a display driver to be modified based on the content to be displayed at the display panel. The display driver can compare current and upcoming display content in order to determine how the line voltage for one or more output lines will change over time. If, based on the comparison, the voltage for an output line is not going to vary substantially over time, the bias current output from the display driver can be modified in order to save power. The modification to the bias current can depend on the amount of change the line voltage will undergo in subsequent executions of the content data.12-17-2015
20160117971INVERSION BALANCING COMPENSATION - System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.04-28-2016

Patent applications by Fenghua Zheng, San Jose, CA US

Leon Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20090100122SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS - Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.04-16-2009
20100169404FLEXIBLE ACCUMULATOR IN DIGITAL SIGNAL PROCESSING CIRCUITRY - A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.07-01-2010

Patent applications by Leon Zheng, San Jose, CA US

Mark Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20090128575Systems and Methods for Managing Texture Descriptors in a Shared Texture Engine - Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.05-21-2009

Mark S. Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20100225655Concurrent Encoding/Decoding of Tiled Data - Example embodiments of the present disclosure provide techniques for dividing bitmaps into tiles and processing the tiles concurrently using multiple tile engines. Data compression algorithms may be adapted so that the algorithms can be concurrently processed by multiple data slice engines. The algorithms may be further adapted so that the concurrent outputs for each stage may be passed to the next processing stage without delays or dead cycles. The reduction or elimination of delays or dead cycles may result in a lower latency.09-09-2010

Ping Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20100070751Preloader - This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer.03-18-2010
20130046966Preloader - This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer.02-21-2013

Qinghua Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20130304844SYSTEM AND METHOD FOR CACHING NETWORK FILE SYSTEMS - A network caching system has a multi-protocol caching filer coupled to an origin server to provide storage virtualization of data served by the filer in response to data access requests issued by multi-protocol clients over a computer network. The multi-protocol caching filer includes a file system configured to manage a sparse volume that “virtualizes” a storage space of the data to thereby provide a cache function that enables access to data by the multi-protocol clients. To that end, the caching filer further includes a multi-protocol engine configured to translate the multi-protocol client data access requests into generic file system primitive operations executable by both the caching filer and the origin server.11-14-2013

Wen-Chun Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20090211095Microgrooves as Wick Structures in Heat Pipes and Method for Fabricating the Same - Microgrooves (<0.2 mm wide) of various shapes used as wick structures in heat pipes can increase the capillary force to overcome the gravitational force on the working fluid so as to enable large working angles for the heat pipes. The microgrooves can be fabricated by two sequential steps use a first plowshare-like blade to turn up the material for large size grooves and then immediately use a second plowshare-like blade to rebury by the previously turned up material. The microgrooves and the fabrication method can be used to manufacture flat heat pipes (vapor chambers) as well as tubular heat pipes.08-27-2009
20090324403Impeller with Hybrid Blades for Blowers - An impeller with hybrid blades can be used in any blowers, which are applied in many fields such as cooling computers and HVAC. The impeller increases air flow as well as pressure. Each hybrid blade extends from the impeller hub with the shape of an axial fan blade and smoothly transforms at a proper radius of the impeller to the shape of a centrifugal blower blade. In addition, a dual-tunnel blower with multiple outlets is also presented.12-31-2009

Patent applications by Wen-Chun Zheng, San Jose, CA US

Xiayu Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20140307568METHOD AND APPARATUS FOR TESTING THE BEAMFORMING PERFORMANCE OF A WIRELESS COMMUNICATION DEVICE - Systems and techniques relating to beamforming testing for wireless communication are described. A described technique includes controlling a first wireless device to deactivate or activate a beamforming mode, the first device being configured to selectively use the beamforming mode to transmit data over multiple antennas; causing the first device to send a first portion of data traffic to a second wireless device via a wireless channel while the beamforming mode is deactivated; measuring first throughput values of the first portion of data traffic while the beamforming mode is deactivated; causing the first device to send a second portion of data traffic to the second device via the wireless channel while the beamforming mode is activated; measuring second throughput values of the second portion of the data traffic while the beamforming mode is activated; and producing a test result based on a comparison of the first and second throughput values, and predetermined criteria.10-16-2014
20150146808MEDIUM ACCESS PROTECTION AND BANDWIDTH NEGOTIATION IN A WIRELESS LOCAL AREA NETWORK - Respective sub-channels of an OFDM channel are allocated by a first device to second devices. A first control frame, transmitted from the first device to the second devices, indicates that the second devices are requested to transmit a second control frame to the first device. Respective second control frames are received from at the first device from least some of the second devices. A second control frame received from a particular second device indicates that at least a portion of the sub-channel allocated to the second device is available. An OFDMA data unit is transmitted by the first device. The OFDMA data unit includes respective OFDM data units transmitted to the at least some of the second devices. Each OFDM data unit is transmitted to a particular second device in the portion of the sub-channel indicated to be available by the second control frame received from the second device.05-28-2015
20150304077SIGNAL FIELD LENGTH INDICATION IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK (WLAN) - A physical layer (PHY) data unit is received via an orthogonal frequency division multiplexing (OFDM) communication channel. The PHY data unit includes (i) a first set of one or more short OFDM symbols generated using a normal tone spacing and (ii) a second set of one or more long OFDM symbols generated using a reduced tone spacing, (iii) an OFDM symbol indicator indicative of a number of OFDM symbols in at least one of (a) the first set of OFDM symbols and (b) the second set of OFDM symbols; Based at least in part on the OFDM symbol indicator, (i) a number of short OFDM symbols in the set of one or more short OFDM symbols and (ii) a number of long OFDM symbols in the set of one or more long OFDM symbols are determined.10-22-2015
20150304078SIGNAL FIELD LENGTH INDICATION IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK (WLAN) - A first set of orthogonal frequency domain multiplexing (OFDM) symbols for a first portion of a PHY data unit and a second set of OFDM symbols for a second portion of the PHY data unit are generated. OFDM symbols of the first set are generated with a first OFDM tone spacing. At least some OFDM symbols of the second set are generated with a second tone spacing different from the first tone spacing. A value for a length indicator indicative of a duration of the PHY data unit is determined based on the first tone spacing and the second tone spacing. The first portion of the PHY data unit is generated to include (i) the first set of OFDM symbols and (ii) the length indicator set to the determined value. The second portion of the PHY data unit is generated to include the second set of OFDM symbols.10-22-2015
20150365263COMPRESSED ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING (OFDM) SYMBOLS IN A WIRELESS COMMUNICATION SYSTEM - One or more first padding bits are added to information bits to be included in a data portion of a data unit such that the information bits, after being encoded, fill one or more OFDM symbols up to a boundary within a last OFDM symbol. The information bits and the first padding bits are encoded to generate coded bits. After encoding, coded bits corresponding to the last OFDM symbol are padded, or constellation points generated based on the coded bits corresponding to the last OFDM symbol are padded, such that the padded coded bits or the padded constellation points occupy a remaining portion of the last OFDM symbol after the boundary. The last OFDM symbol of the data portion is generated to include the coded information bits corresponding to the last OFDM symbol, the first padding bits and second padding bits or padding constellation points added after encoding.12-17-2015
20150365266COMPRESSED PREAMBLE FOR A WIRELESS COMMUNICATION SYSTEM - One or more long OFDM symbols for a data portion of a data unit data are generated. Each of the one or more long OFDM symbols is generated with a first number of OFDM tones. One or more short OFDM symbols for one or more long training fields of a preamble of the data unit are generated. Each of the one or more short OFDM symbols is generated with a second number of OFDM that is a fraction 1/N of the first number of OFDM tones, wherein N is a positive integer greater than one. The data unit is generated. Generating the data unit includes generating the preamble to include the one or more short OFDM symbols corresponding to the one or more training fields of the preamble and generating the data portion to include the one or more long OFDM symbols.12-17-2015
20160099798MEDIUM ACCESS PROTECTION AND BANDWIDTH NEGOTIATION IN A WIRELESS LOCAL AREA NETWORK - A first communication device transmits a first control frame to multiple second communication devices via a wireless communication medium, wherein the first control frame i) indicates to other communication devices that the wireless communication medium is reserved for a first time period, and ii) indicates that the second communication devices are requested to simultaneously transmit respective second control frames to the first communication device via the wireless communication medium, wherein the second control frames are to include information indicating to other communication devices that the wireless communication medium is reserved for a second time period that is a subset of the first time period.04-07-2016

Patent applications by Xiayu Zheng, San Jose, CA US

Yan Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20140278924SELECTIVELY ALTERING REQUESTS BASED ON COMPARISON OF POTENTIAL VALUE OF REQUESTS - The present invention is generally directed to methods, systems, and computer program products for selectively altering the processing of a request based on a potential value of the request. When an undesirably high number of requests are being received by a server system, the server system can identify requests that have a potential value greater than a potential value of one or more other requests. The server system can then alter the processing of the requests having the lower potential value thereby ensuring that requests with higher potential value are processed adequately.09-18-2014
20140279886INCREMENTALLY UPDATING A LARGE KEY-VALUE STORE - The present disclosure extends to incrementally updating a database in a production environment in a way that maintains data freshness and allows for high priority updates for critical changed values and regular updates for noncritical changed values in the database.09-18-2014
20140280033RULE TRIGGERING FOR SEARCH RULE ENGINE - A computer-implemented system and method of executing search queries by a search rule engine is disclosed. Embodiments of the present disclosure comprise a search engine that may evaluate an arbitrary number of rule triggering conditions with constant run-time complexity, which may result in increased efficiency and faster searching relative to traditional search rule engine methods.09-18-2014
20160092519SYSTEM AND METHOD FOR CAPTURING SEASONALITY AND NEWNESS IN DATABASE SEARCHES - A system and method for capturing seasonality in a database system is disclosed herein. A database system may comprise a first database cluster H and a second database cluster L, with records being divided between the first database cluster H and the second database cluster L by likelihood of the record being accessed. Several criteria may be used to determine the likelihood of a record being accessed. For example, one may review access history to determine the activity for the record during various time periods, such as comparing access history for the record the same day one year ago, in an attempt to determine seasonality of the record. One may also review the newness of a record, such that the newness of a record is part of the criteria being reviewed when assigning record to a database cluster. Other embodiments are also disclosed herein.03-31-2016
20160092520SYSTEM AND METHOD FOR USING PAST OR EXTERNAL INFORMATION FOR FUTURE SEARCH RESULTS - A system and method for using past information for future search results is disclosed. A database system may comprise a first database cluster H and a second database cluster L. Social media mentions are mapped to products in the database system. Thereafter, each record in the database system is tracked to determine if mentions on social media platforms are increasing or decreasing, using a social media popularity trend signal. The social media popularity trend signal is created by comparing social media mentions during one time period to social media mentions in another time period. Other embodiments are also disclosed herein.03-31-2016
20160092564SYSTEM AND METHOD FOR PRIORITIZED PRODUCT INDEX SEARCHING - A system and method for searching databases is disclosed herein. A database system may comprise a first database cluster H and a second database cluster L. After receiving a search request from a requester, the search request is executed in the first database cluster H to retrieve a first set of results. If the first set of results is greater than a minimum number of results, then the first set of results are presented to the requester. Otherwise, the second database cluster L is searched to retrieve a second set of results. Then the first set of results and the second set of results are presented to the requester. The first database cluster H is stored on a first database server; and the second database cluster L is stored on a second database server apart from the first database server. Other embodiments are also disclosed herein.03-31-2016
20160092577SYSTEM AND METHOD FOR INTEGRATING BUSINESS LOGIC INTO A HOT/COLD PREDICTION - A system and method for integrating business logic into a database system is disclosed herein. A database system may comprise a first database cluster H and a second database cluster L. After records are separated into the first database cluster H and the second database cluster L, the total number of records in the second database cluster L is compared to a target number of records. If there are too many records in the second database cluster L, a randomly generated number is used to randomly move records from second database cluster L into first database cluster H. In a situation where the first database cluster H is faster and accessed more often, such a method results in more products being placed in the faster database cluster and become more likely to become purchased. Other embodiments are also disclosed herein.03-31-2016
20160092772SYSTEM AND METHOD FOR CALCULATING SEARCH TERM PROBABILITY - A system and method for predicting search term popularity is disclosed herein. A database system may comprise a first database cluster H and a second database cluster L. A machine learning algorithm is trained to create a predictive model. Thereafter, for each record in a database system, the predictive model is used to calculate a probability of the record being accessed. If the calculated probability of the record being accessed is greater than a threshold value, then the record in the first database cluster H; otherwise, the record is placed in the second database cluster L. Training the machine learning algorithm comprises inputting a training feature vector associated with the record into the machine learning algorithm, inputting a cost vector into the machine learning algorithm, and iteratively operating the machine learning algorithm on each record in the set of records to create a predictive model. Other embodiments are also disclosed herein.03-31-2016

Yang Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20090041326LINE STRUCTURE DETECTION AND ANALYSIS FOR MAMMOGRAPHY CAD - A method for image linear structure detection in medical imaging. The method includes locating microcalcification (mcc) candidate spots in a mammographic image; forming candidate clusters; assigning ranks to the candidate clusters; identifying linear structures in the neighborhood where the candidate clusters reside; and altering the ranks of the candidate clusters for which linear structures have been identified in the neighborhood.02-12-2009

Patent applications by Yang Zheng, San Jose, CA US

Youfeng Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20130280556MAGNETIC RECORDING MEDIA WITH SOFT MAGNETIC UNDERLAYERS - Provided herein, is an apparatus that includes a nonmagnetic substrate having a surface; and a plurality of overlying thin film layers forming a layer stack on the substrate surface. The layer stack includes a magnetically hard perpendicular magnetic recording layer structure and an underlying soft magnetic underlayer (SUL), wherein the sum of a magnetic thickness of the layer stack is a magnetic thickness of up to about 2 memu/cm̂2.10-24-2013
20140168822MAGNETIC SENSOR WITH EXTENDED PINNED LAYER AND PARTIAL WRAP AROUND SHIELD - A magnetic read head that has improved pinned layer stability while also maintaining excellent free layer stability. The free layer has sides that define a trackwidth of the sensor and a back edge that defines a functional stripe height of the sensor. However, the pinned layer can extend significantly beyond both the width of the free layer and the back edge (e.g. stripe height) of the free layer. The sensor also has a soft magnetic bias structure that compensates for the reduced volume presented by the side extension of the pinned layer. The soft magnetic bias structure can be magnetically coupled with the trailing magnetic shield, either parallel coupled or anti-parallel coupled. In addition, all or a portion of the soft magnetic bias structure can be exchange coupled to a layer of anti-ferromagnetic material in order to improve the robustness of the soft magnetic bias structure.06-19-2014
20140313615APPARATUS COMPRISING MAGNETICALLY SOFT UNDERLAYER - Provided herein is an apparatus, including a magnetically soft underlayer (SUL); an interlayer stack overlying the SUL, wherein the interlayer stack comprises a seed layer of an fcc material; and a perpendicular magnetic recording layer overlying the interlayer stack, wherein a thickness of the SUL in combination with a distance of the SUL from the perpendicular recording layer is sufficient to orient a total magnetic field corresponding to a magnetic transducer head at an angle of about 45°.10-23-2014
20150062751MAGNETIC SENSOR HAVING AN EXTENDED PINNED LAYER WITH STITCHED ANTIFERROMAGNETIC PINNING LAYER - A magnetic sensor having a novel pinning structure resulting in a greatly reduced gap spacing. The sensor has a magnetic free layer structure that extends to a first stripe height and a magnetic pinned layer structure that extends to a second stripe height that is longer than the first stripe high. A layer of anti-ferromagnetic material is formed over the pinned layer structure in the region beyond the first stripe height location. In this way, the antiferromagnetic layer is between the pinned layer and the second or upper shield and does not contribute to gap spacing.03-05-2015

Patent applications by Youfeng Zheng, San Jose, CA US

Yuanwei Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20160071892DOPANT CONFIGURATION IN IMAGE SENSOR PIXELS - An image sensor pixel including a photodiode includes a first dopant region disposed within a semiconductor layer and a second dopant region disposed above the first dopant region and within the semiconductor layer. The second dopant region contacts the first dopant region and the second dopant region is of an opposite majority charge carrier type as the first dopant region. A third dopant region is disposed above the first dopant region and within the semiconductor layer. The third dopant region is of a same majority charge carrier type as the second dopant region but has a greater concentration of free charge carriers than the second dopant region. A transfer gate is positioned to transfer photogenerated charge from the photodiode. The second dopant region extends closer to an edge of the transfer gate than the third dopant region.03-10-2016

Yufeng Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20080244028Synchronization and Customization of a Clone Computer - A computer implemented method for maintaining synchronization between a master computer disk and a clone disk that includes cloning the clone disk from the master computer disk, the clone disk having a customization portion; and customizing the customization portion with information relevant to a clone computer that uses the clone disk.10-02-2008
20140282509MANAGING AN INDEPENDENT VIRTUAL DISK - A computer-implemented method for managing an independent virtual disk. The method includes creating an independent virtual disk; in response to the creating the independent virtual disk, creating a first virtual machine; and attaching an independent virtual disk to the first virtual machine; and managing the independent virtual disk by controlling the first virtual machine that is attached to the independent virtual disk.09-18-2014
20140282511PRESERVING AN INDEPENDENT VIRTUAL DISK - A computer-implemented method for preserving an independent virtual disk. The method, includes attaching an independent virtual disk to a first virtual machine, and preserving said independent virtual disk when the independent virtual disk is detached from the first virtual machine.09-18-2014

Yunfei Zheng, San Jose, CA US

Patent application numberDescriptionPublished
20140010295Methods and Apparatus for Geometric-Based Intra Prediction - Methods and apparatus are provided for geometric-based intra prediction. An apparatus includes a video encoder for encoding picture data for at least a portion of a block in a picture by detecting a local geometric pattern in a surrounding area with respect to the portion, and performing at least one of interpolation and extrapolation with respect to an edge direction of the local geometric pattern to generate an intra prediction for the portion.01-09-2014
20140341274CODING THE POSITION OF A LAST SIGNIFICANT COEFFICIENT WITHIN A VIDEO BLOCK BASED ON A SCANNING ORDER FOR THE BLOCK IN VIDEO CODING - In one example, an apparatus is disclosed for coding coefficients associated with a block of video data during a video coding process, wherein the apparatus includes a video coder configured to code x- and y-coordinates that indicate a position of a last non-zero coefficient within the block according to a scanning order associated with the block when the scanning order comprises a first scanning order, and code interchanged x- and y-coordinates that indicate the position of the last non-zero coefficient within the block according to the scanning order when the scanning order comprises a second scanning order, wherein the second scanning order is different than the first scanning order.11-20-2014
20160105673METHODS AND APPARATUS FOR DETERMINING QUANTIZATION PARAMETER PREDICTORS FROM A PLURALITY OF NEIGHBORING QUANTIZATION PARAMETERS - Methods and apparatus are provided for determining quantization parameter predictors from a plurality of neighboring quantization parameters. An apparatus includes an encoder for encoding image data for at least a portion of a picture using a quantization parameter predictor for a current quantization parameter to be applied to the image data. The quantization parameter predictor is determined using multiple quantization parameters from previously coded neighboring portions. A difference between the current quantization parameter and the quantization parameter predictor is encoded for signaling to a corresponding decoder.04-14-2016
Website © 2016 Advameg, Inc.